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net: switch to using PHY_INTERFACE_MODE_10GBASER rather than 10GKR

Browse source 
Switch network drivers, phy drivers, and SFP/phylink over to use the
more correct 10GBASE-R, rather than 10GBASE-KR. 10GBASE-KR is backplane
ethernet, which is 10GBASE-R with autonegotiation on top, which our
current usage on the affected platforms does not have.

The only remaining user of PHY_INTERFACE_MODE_10GKR is the Aquantia
PHY, which has a separate mode for 10GBASE-KR.

For Marvell mvpp2, we detect 10GBASE-KR, and rewrite it to 10GBASE-R
for compatibility with existing DT - this is the only network driver
at present that makes use of PHY_INTERFACE_MODE_10GKR.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King 2020-01-03 20:43:23 +00:00 committed by David S. Miller
parent c114574ebf
commit e0f909bc3a
7 changed files with 39 additions and 25 deletions
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19
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
View file

@ -1114,7 +1114,7 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
/* Port configuration routines */ /* Port configuration routines */
static bool mvpp2_is_xlg(phy_interface_t interface) static bool mvpp2_is_xlg(phy_interface_t interface)
{ {
return interface == PHY_INTERFACE_MODE_10GKR || return interface == PHY_INTERFACE_MODE_10GBASER ||
interface == PHY_INTERFACE_MODE_XAUI; interface == PHY_INTERFACE_MODE_XAUI;
} }
@ -1200,7 +1200,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_2500BASEX:
mvpp22_gop_init_sgmii(port); mvpp22_gop_init_sgmii(port);
break; break;
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
if (port->gop_id != 0) if (port->gop_id != 0)
goto invalid_conf; goto invalid_conf;
mvpp22_gop_init_10gkr(port); mvpp22_gop_init_10gkr(port);
@ -1649,7 +1649,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
switch (port->phy_interface) { switch (port->phy_interface) {
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
val = readl(mpcs + MVPP22_MPCS_CLK_RESET); val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
MAC_CLK_RESET_SD_TX; MAC_CLK_RESET_SD_TX;
@ -4758,7 +4758,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
/* Invalid combinations */ /* Invalid combinations */
switch (state->interface) { switch (state->interface) {
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_XAUI:
if (port->gop_id != 0) if (port->gop_id != 0)
goto empty_set; goto empty_set;
@ -4780,7 +4780,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
phylink_set(mask, Asym_Pause); phylink_set(mask, Asym_Pause);
switch (state->interface) { switch (state->interface) {
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_XAUI:
case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_NA:
if (port->gop_id == 0) { if (port->gop_id == 0) {
@ -5247,6 +5247,15 @@ static int mvpp2_port_probe(struct platform_device *pdev,
goto err_free_netdev; goto err_free_netdev;
} }
/*
* Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
* Existing usage of 10GBASE-KR is not correct; no backplane
* negotiation is done, and this driver does not actually support
* 10GBASE-KR.
*/
if (phy_mode == PHY_INTERFACE_MODE_10GKR)
phy_mode = PHY_INTERFACE_MODE_10GBASER;
if (port_node) { if (port_node) {
comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
if (IS_ERR(comphy)) { if (IS_ERR(comphy)) {

7
drivers/net/phy/aquantia_main.c
View file

@ -358,9 +358,11 @@ static int aqr107_read_status(struct phy_device *phydev)
switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
phydev->interface = PHY_INTERFACE_MODE_10GKR; phydev->interface = PHY_INTERFACE_MODE_10GKR;
break; break;
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
phydev->interface = PHY_INTERFACE_MODE_10GBASER;
break;
case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
phydev->interface = PHY_INTERFACE_MODE_USXGMII; phydev->interface = PHY_INTERFACE_MODE_USXGMII;
break; break;
@ -493,7 +495,8 @@ static int aqr107_config_init(struct phy_device *phydev)
phydev->interface != PHY_INTERFACE_MODE_2500BASEX && phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
phydev->interface != PHY_INTERFACE_MODE_XGMII && phydev->interface != PHY_INTERFACE_MODE_XGMII &&
phydev->interface != PHY_INTERFACE_MODE_USXGMII && phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
phydev->interface != PHY_INTERFACE_MODE_10GKR) phydev->interface != PHY_INTERFACE_MODE_10GKR &&
phydev->interface != PHY_INTERFACE_MODE_10GBASER)
return -ENODEV; return -ENODEV;
WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,

4
drivers/net/phy/bcm84881.c
View file

@ -53,7 +53,7 @@ static int bcm84881_config_init(struct phy_device *phydev)
switch (phydev->interface) { switch (phydev->interface) {
case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
break; break;
default: default:
return -ENODEV; return -ENODEV;
@ -218,7 +218,7 @@ static int bcm84881_read_status(struct phy_device *phydev)
if (mode == 1 || mode == 2) if (mode == 1 || mode == 2)
phydev->interface = PHY_INTERFACE_MODE_SGMII; phydev->interface = PHY_INTERFACE_MODE_SGMII;
else if (mode == 3) else if (mode == 3)
phydev->interface = PHY_INTERFACE_MODE_10GKR; phydev->interface = PHY_INTERFACE_MODE_10GBASER;
else if (mode == 4) else if (mode == 4)
phydev->interface = PHY_INTERFACE_MODE_2500BASEX; phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
switch (mode & 7) { switch (mode & 7) {

11
drivers/net/phy/marvell10g.c
View file

@ -216,7 +216,7 @@ static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
sfp_parse_support(phydev->sfp_bus, id, support); sfp_parse_support(phydev->sfp_bus, id, support);
iface = sfp_select_interface(phydev->sfp_bus, support); iface = sfp_select_interface(phydev->sfp_bus, support);
if (iface != PHY_INTERFACE_MODE_10GKR) { if (iface != PHY_INTERFACE_MODE_10GBASER) {
dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
return -EINVAL; return -EINVAL;
} }
@ -304,7 +304,7 @@ static int mv3310_config_init(struct phy_device *phydev)
phydev->interface != PHY_INTERFACE_MODE_2500BASEX && phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
phydev->interface != PHY_INTERFACE_MODE_XAUI && phydev->interface != PHY_INTERFACE_MODE_XAUI &&
phydev->interface != PHY_INTERFACE_MODE_RXAUI && phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
phydev->interface != PHY_INTERFACE_MODE_10GKR) phydev->interface != PHY_INTERFACE_MODE_10GBASER)
return -ENODEV; return -ENODEV;
return 0; return 0;
@ -386,16 +386,17 @@ static void mv3310_update_interface(struct phy_device *phydev)
{ {
if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
phydev->interface == PHY_INTERFACE_MODE_2500BASEX || phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) { phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
phydev->link) {
/* The PHY automatically switches its serdes interface (and /* The PHY automatically switches its serdes interface (and
* active PHYXS instance) between Cisco SGMII, 10GBase-KR and * active PHYXS instance) between Cisco SGMII, 10GBase-R and
* 2500BaseX modes according to the speed. Florian suggests * 2500BaseX modes according to the speed. Florian suggests
* setting phydev->interface to communicate this to the MAC. * setting phydev->interface to communicate this to the MAC.
* Only do this if we are already in one of the above modes. * Only do this if we are already in one of the above modes.
*/ */
switch (phydev->speed) { switch (phydev->speed) {
case SPEED_10000: case SPEED_10000:
phydev->interface = PHY_INTERFACE_MODE_10GKR; phydev->interface = PHY_INTERFACE_MODE_10GBASER;
break; break;
case SPEED_2500: case SPEED_2500:
phydev->interface = PHY_INTERFACE_MODE_2500BASEX; phydev->interface = PHY_INTERFACE_MODE_2500BASEX;

1
drivers/net/phy/phylink.c
View file

@ -298,6 +298,7 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
break; break;
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GKR:
case PHY_INTERFACE_MODE_10GBASER:
phylink_set(pl->supported, 10baseT_Half); phylink_set(pl->supported, 10baseT_Half);
phylink_set(pl->supported, 10baseT_Full); phylink_set(pl->supported, 10baseT_Full);
phylink_set(pl->supported, 100baseT_Half); phylink_set(pl->supported, 100baseT_Half);

2
drivers/net/phy/sfp-bus.c
View file

@ -373,7 +373,7 @@ phy_interface_t sfp_select_interface(struct sfp_bus *bus,
phylink_test(link_modes, 10000baseLRM_Full) || phylink_test(link_modes, 10000baseLRM_Full) ||
phylink_test(link_modes, 10000baseER_Full) || phylink_test(link_modes, 10000baseER_Full) ||
phylink_test(link_modes, 10000baseT_Full)) phylink_test(link_modes, 10000baseT_Full))
return PHY_INTERFACE_MODE_10GKR; return PHY_INTERFACE_MODE_10GBASER;
if (phylink_test(link_modes, 2500baseX_Full)) if (phylink_test(link_modes, 2500baseX_Full))
return PHY_INTERFACE_MODE_2500BASEX; return PHY_INTERFACE_MODE_2500BASEX;

20
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
View file

@ -221,7 +221,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII), ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI), ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI), ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),
GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
@ -235,14 +235,14 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 4 */ /* lane 4 */
ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII), ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII), ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI), ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI), ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D), GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII), ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI), ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */ /* lane 5 */
ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI), ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
@ -342,7 +342,7 @@ static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE); MVEBU_COMPHY_SERDES_CFG0_RXAUI_MODE);
switch (lane->submode) { switch (lane->submode) {
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe); MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
break; break;
@ -417,7 +417,7 @@ static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
/* refclk selection */ /* refclk selection */
val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL;
if (lane->submode == PHY_INTERFACE_MODE_10GKR) if (lane->submode == PHY_INTERFACE_MODE_10GBASER)
val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE;
writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
@ -564,7 +564,7 @@ static int mvebu_comphy_set_mode_rxaui(struct phy *phy)
return mvebu_comphy_init_plls(lane); return mvebu_comphy_init_plls(lane);
} }
static int mvebu_comphy_set_mode_10gkr(struct phy *phy) static int mvebu_comphy_set_mode_10gbaser(struct phy *phy)
{ {
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv; struct mvebu_comphy_priv *priv = lane->priv;
@ -735,8 +735,8 @@ static int mvebu_comphy_power_on_legacy(struct phy *phy)
case PHY_INTERFACE_MODE_RXAUI: case PHY_INTERFACE_MODE_RXAUI:
ret = mvebu_comphy_set_mode_rxaui(phy); ret = mvebu_comphy_set_mode_rxaui(phy);
break; break;
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
ret = mvebu_comphy_set_mode_10gkr(phy); ret = mvebu_comphy_set_mode_10gbaser(phy);
break; break;
default: default:
return -ENOTSUPP; return -ENOTSUPP;
@ -782,8 +782,8 @@ static int mvebu_comphy_power_on(struct phy *phy)
lane->id); lane->id);
fw_speed = COMPHY_FW_SPEED_3125; fw_speed = COMPHY_FW_SPEED_3125;
break; break;
case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER:
dev_dbg(priv->dev, "set lane %d to 10G-KR mode\n", dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
lane->id); lane->id);
fw_speed = COMPHY_FW_SPEED_103125; fw_speed = COMPHY_FW_SPEED_103125;
break; break;