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Most likely the last pull request from me for omap changes for 

v3.16 that's dts fixes for clocks and enabling few features
 that were still being discussed earlier:
 
 - A bunch of omap clock related dts fixes queued by Tero Kristo.
 
 - Enable parallel nand on am437x that was not merged earlier as
   I requested more information about the muxing for it. And
   we need to also enable ecc hardware support for am43xx.
 
 - Enable the modem support for n900 that was dropped earlier
   because we had to fix the related hwmod entry first with patch
   ARM: OMAP2+: Fix ssi hwmod entry to allow idling.
 
 - And finally, add the omap2 clock dts files. These will allow
   us to enable the dt clocks and drop the legacy clocks for omap2
   with a follow-up patch once the related clock driver binding
   changes are merged.
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Merge tag 'omap-for-v3.16/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Merge "omap dt fixes and and clocks for v3.16 merge window" from Tony Lindgren:

Most likely the last pull request from me for omap changes for
v3.16 that's dts fixes for clocks and enabling few features
that were still being discussed earlier:

- A bunch of omap clock related dts fixes queued by Tero Kristo.

- Enable parallel nand on am437x that was not merged earlier as
  I requested more information about the muxing for it. And
  we need to also enable ecc hardware support for am43xx.

- Enable the modem support for n900 that was dropped earlier
  because we had to fix the related hwmod entry first with patch
  ARM: OMAP2+: Fix ssi hwmod entry to allow idling.

- And finally, add the omap2 clock dts files. These will allow
  us to enable the dt clocks and drop the legacy clocks for omap2
  with a follow-up patch once the related clock driver binding
  changes are merged.

* tag 'omap-for-v3.16/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: omap2 clock data
  ARM: dts: am437x-gp-evm: add support for parallel NAND flash
  ARM: OMAP2+: gpmc: enable BCH_HW ecc-scheme for AM43xx platforms
  ARM: dts: omap3 a83x: fix duplicate usb pin config
  ARM: dts: omap3: set mcbsp2 status
  ARM: dts: omap3-n900: Add modem support
  ARM: dts: omap3-n900: Add SSI support
  ARM: OMAP2+: Fix ssi hwmod entry to allow idling
  ARM: dts: AM4372: clk: efuse based crystal frequency detect
  ARM: dts: am43xx-clocks.dtsi: add ti, set-rate-parent to display clock path
  ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk
  ARM: dts: omap4: add twd clock to DT
  ARM: dts: omap54xx-clocks: Correct abe_iclk clock node
  ARM: dts: omap54xx-clocks: remove the autoidle properties for clock nodes
  ARM: dts: am43x-clock: add tbclk data for ehrpwm
  ARM: dts: am33xx-clock: Fix ehrpwm tbclk data
  ARM: dts: set 'ti,set-rate-parent' for dpll4_m5 path
  ARM: dts: use ti,fixed-factor-clock for dpll4_m5x2_mul_ck
  ARM: dts: am43xx-clocks: use ti, fixed-factor-clock for dpll_per_clkdcoldo

Signed-off-by: Olof Johansson <olof@lixom.net>
hifive-unleashed-5.1
Olof Johansson 2014-05-29 12:43:43 -07:00
parent 81d1d392f3 43369f0fe8
commit e1134cb6b3
20 changed files with 2254 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -96,47 +96,29 @@
clock-div = <1>;
};
ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk {
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ehrpwm0_gate_tbclk>;
};
ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk {
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ehrpwm1_gate_tbclk>;
};
ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ehrpwm2_gate_tbclk>;
};
};
&prcm_clocks {
clk_32768_ck: clk_32768_ck {

108
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -150,6 +150,27 @@
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
};
&i2c0 {
@ -246,3 +267,90 @@
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
reg = <0 0 4>; /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <25>;
gpmc,adv-wr-off-ns = <25>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <3>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,wait-pin = <0>;
gpmc,wait-on-read;
gpmc,wait-on-write;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00080000 0x00040000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x000c0000 0x00040000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00100000 0x00080000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x00180000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x00280000 0x00040000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002c0000 0x00040000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00300000 0x00700000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x1f600000>;
};
};
};

75
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -9,6 +9,22 @@
*/
&scrm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
ti,bit-shift = <31>;
reg = <0x0040>;
};
crystal_freq_sel_ck: crystal_freq_sel_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <29>;
reg = <0x0040>;
};
sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@ -87,6 +103,54 @@
clock-mult = <1>;
clock-div = <1>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
ehrpwm3_tbclk: ehrpwm3_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
ehrpwm4_tbclk: ehrpwm4_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
ehrpwm5_tbclk: ehrpwm5_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
ti,bit-shift = <6>;
reg = <0x0664>;
};
};
&prcm_clocks {
clk_32768_ck: clk_32768_ck {
@ -229,6 +293,7 @@
reg = <0x2e30>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
ti,set-rate-parent;
};
dpll_per_ck: dpll_per_ck {
@ -511,6 +576,7 @@
compatible = "ti,mux-clock";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
reg = <0x4244>;
ti,set-rate-parent;
};
dpll_extdev_ck: dpll_extdev_ck {
@ -609,10 +675,13 @@
dpll_per_clkdcoldo: dpll_per_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_per_ck>;
clock-mult = <1>;
clock-div = <1>;
ti,clock-mult = <1>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
reg = <0x2e14>;
ti,invert-autoidle-bit;
};
dll_aging_clk_div: dll_aging_clk_div {

270
arch/arm/boot/dts/omap2420-clocks.dtsi 100644
View File

@ -0,0 +1,270 @@
/*
* Device Tree Source for OMAP2420 clock data
*
* Copyright (C) 2014 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&prcm_clocks {
sys_clkout2_src_gate: sys_clkout2_src_gate {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <15>;
reg = <0x0070>;
};
sys_clkout2_src_mux: sys_clkout2_src_mux {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
ti,bit-shift = <8>;
reg = <0x0070>;
};
sys_clkout2_src: sys_clkout2_src {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
};
sys_clkout2: sys_clkout2 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkout2_src>;
ti,bit-shift = <11>;
ti,max-div = <64>;
reg = <0x0070>;
ti,index-power-of-two;
};
dsp_gate_ick: dsp_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <1>;
reg = <0x0810>;
};
dsp_div_ick: dsp_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <5>;
ti,max-div = <3>;
reg = <0x0840>;
ti,index-starts-at-one;
};
dsp_ick: dsp_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
};
iva1_gate_ifck: iva1_gate_ifck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <10>;
reg = <0x0800>;
};
iva1_div_ifck: iva1_div_ifck {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
ti,bit-shift = <8>;
reg = <0x0840>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
};
iva1_ifck: iva1_ifck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
};
iva1_ifck_div: iva1_ifck_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&iva1_ifck>;
clock-mult = <1>;
clock-div = <2>;
};
iva1_mpu_int_ifck: iva1_mpu_int_ifck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&iva1_ifck_div>;
ti,bit-shift = <8>;
reg = <0x0800>;
};
wdt3_ick: wdt3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <28>;
reg = <0x0210>;
};
wdt3_fck: wdt3_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <28>;
reg = <0x0200>;
};
mmc_ick: mmc_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <26>;
reg = <0x0210>;
};
mmc_fck: mmc_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <26>;
reg = <0x0200>;
};
eac_ick: eac_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <24>;
reg = <0x0210>;
};
eac_fck: eac_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <24>;
reg = <0x0200>;
};
i2c1_fck: i2c1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
ti,bit-shift = <19>;
reg = <0x0200>;
};
i2c2_fck: i2c2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
ti,bit-shift = <20>;
reg = <0x0200>;
};
vlynq_ick: vlynq_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l3_ck>;
ti,bit-shift = <3>;
reg = <0x0210>;
};
vlynq_gate_fck: vlynq_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <3>;
reg = <0x0200>;
};
core_d18_ck: core_d18_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <18>;
};
vlynq_mux_fck: vlynq_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
ti,bit-shift = <15>;
reg = <0x0240>;
};
vlynq_fck: vlynq_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
};
};
&prcm_clockdomains {
gfx_clkdm: gfx_clkdm {
compatible = "ti,clockdomain";
clocks = <&gfx_ick>;
};
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
};
iva1_clkdm: iva1_clkdm {
compatible = "ti,clockdomain";
clocks = <&iva1_mpu_int_ifck>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_ick>, <&dss_54m_fck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
<&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
<&uart3_ick>, <&uart3_fck>, <&cam_ick>,
<&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
<&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
<&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
<&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
<&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
<&pka_ick>;
};
};
&func_96m_ck {
compatible = "fixed-factor-clock";
clocks = <&apll96_ck>;
clock-mult = <1>;
clock-div = <1>;
};
&dsp_div_fck {
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
};
&ssi_ssr_sst_div_fck {
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};

26
arch/arm/boot/dts/omap2420.dtsi
View File

@ -14,6 +14,32 @@
compatible = "ti,omap2420", "ti,omap2";
ocp {
prcm: prcm@48008000 {
compatible = "ti,omap2-prcm";
reg = <0x48008000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@48000000 {
compatible = "ti,omap2-scrm";
reg = <0x48000000 0x1000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@48004000 {
compatible = "ti,omap-counter32k";
reg = <0x48004000 0x20>;

344
arch/arm/boot/dts/omap2430-clocks.dtsi 100644
View File

@ -0,0 +1,344 @@
/*
* Device Tree Source for OMAP2430 clock data
*
* Copyright (C) 2014 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
mcbsp3_mux_fck: mcbsp3_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
reg = <0x02e8>;
};
mcbsp3_fck: mcbsp3_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
};
mcbsp4_mux_fck: mcbsp4_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x02e8>;
};
mcbsp4_fck: mcbsp4_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
};
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02e8>;
};
mcbsp5_fck: mcbsp5_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
};
};
&prcm_clocks {
iva2_1_gate_ick: iva2_1_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <0>;
reg = <0x0800>;
};
iva2_1_div_ick: iva2_1_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dsp_fck>;
ti,bit-shift = <5>;
ti,max-div = <3>;
reg = <0x0840>;
ti,index-starts-at-one;
};
iva2_1_ick: iva2_1_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
};
mdm_gate_ick: mdm_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&core_ck>;
ti,bit-shift = <0>;
reg = <0x0c10>;
};
mdm_div_ick: mdm_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
reg = <0x0c40>;
ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
};
mdm_ick: mdm_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
};
mdm_osc_ck: mdm_osc_ck {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&osc_ck>;
ti,bit-shift = <1>;
reg = <0x0c00>;
};
mcbsp3_ick: mcbsp3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <3>;
reg = <0x0214>;
};
mcbsp3_gate_fck: mcbsp3_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <3>;
reg = <0x0204>;
};
mcbsp4_ick: mcbsp4_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <4>;
reg = <0x0214>;
};
mcbsp4_gate_fck: mcbsp4_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x0204>;
};
mcbsp5_ick: mcbsp5_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <5>;
reg = <0x0214>;
};
mcbsp5_gate_fck: mcbsp5_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
ti,bit-shift = <5>;
reg = <0x0204>;
};
mcspi3_ick: mcspi3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <9>;
reg = <0x0214>;
};
mcspi3_fck: mcspi3_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
ti,bit-shift = <9>;
reg = <0x0204>;
};
icr_ick: icr_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
ti,bit-shift = <6>;
reg = <0x0410>;
};
i2chs1_fck: i2chs1_fck {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <19>;
reg = <0x0204>;
};
i2chs2_fck: i2chs2_fck {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <20>;
reg = <0x0204>;
};
usbhs_ick: usbhs_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l3_ck>;
ti,bit-shift = <6>;
reg = <0x0214>;
};
mmchs1_ick: mmchs1_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <7>;
reg = <0x0214>;
};
mmchs1_fck: mmchs1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <7>;
reg = <0x0204>;
};
mmchs2_ick: mmchs2_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <8>;
reg = <0x0214>;
};
mmchs2_fck: mmchs2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
ti,bit-shift = <8>;
reg = <0x0204>;
};
gpio5_ick: gpio5_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <10>;
reg = <0x0214>;
};
gpio5_fck: gpio5_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <10>;
reg = <0x0204>;
};
mdm_intc_ick: mdm_intc_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
ti,bit-shift = <11>;
reg = <0x0214>;
};
mmchsdb1_fck: mmchsdb1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <16>;
reg = <0x0204>;
};
mmchsdb2_fck: mmchsdb2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
ti,bit-shift = <17>;
reg = <0x0204>;
};
};
&prcm_clockdomains {
gfx_clkdm: gfx_clkdm {
compatible = "ti,clockdomain";
clocks = <&gfx_ick>;
};
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
<&icr_ick>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_ick>, <&dss_54m_fck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
<&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
<&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
<&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
<&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
<&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
<&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
<&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
<&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
<&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
<&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
<&mmchsdb2_fck>;
};
mdm_clkdm: mdm_clkdm {
compatible = "ti,clockdomain";
clocks = <&mdm_osc_ck>;
};
};
&func_96m_ck {
compatible = "ti,mux-clock";
clocks = <&apll96_ck>, <&alt_ck>;
ti,bit-shift = <4>;
reg = <0x0540>;
};
&dsp_div_fck {
ti,max-div = <4>;
ti,index-starts-at-one;
};
&ssi_ssr_sst_div_fck {
ti,max-div = <5>;
ti,index-starts-at-one;
};

26
arch/arm/boot/dts/omap2430.dtsi
View File

@ -14,6 +14,32 @@
compatible = "ti,omap2430", "ti,omap2";
ocp {
prcm: prcm@49006000 {
compatible = "ti,omap2-prcm";
reg = <0x49006000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@49002000 {
compatible = "ti,omap2-scrm";
reg = <0x49002000 0x1000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@49020000 {
compatible = "ti,omap-counter32k";
reg = <0x49020000 0x20>;

1244
arch/arm/boot/dts/omap24xx-clocks.dtsi 100644
View File

File diff suppressed because it is too large Load Diff

7
arch/arm/boot/dts/omap3-lilly-a83x.dtsi
View File

@ -176,9 +176,6 @@
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb1_2_pins
>;
hsusb1_2_pins: pinmux_hsusb1_2_pins {
pinctrl-single,pins = <
@ -357,6 +354,10 @@
power = <50>;
};
&mcbsp2 {
status = "okay";
};
&gpmc {
ranges = <0 0 0x30000000 0x1000000>,
<7 0 0x15000000 0x01000000>;

65
arch/arm/boot/dts/omap3-n900.dts
View File

@ -203,6 +203,30 @@
0x05a (PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
>;
};
ssi_pins: pinmux_ssi {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
0x14e (PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
0x152 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
0x14c (PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
0x154 (PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
0x156 (PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
0x158 (PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
0x15a (PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
>;
};
modem_pins: pinmux_modem {
pinctrl-single,pins = <
0x0ac (PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
0x0b0 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
0x0b2 (PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
0x0b4 (PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
0x0b6 (PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
0x15e (PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
>;
};
};
&i2c1 {
@ -720,3 +744,44 @@
&mcbsp2 {
status = "ok";
};
&ssi_port1 {
pinctrl-names = "default";
pinctrl-0 = <&ssi_pins>;
ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
modem: hsi-client {
compatible = "nokia,n900-modem";
pinctrl-names = "default";
pinctrl-0 = <&modem_pins>;
hsi-channel-ids = <0>, <1>, <2>, <3>;
hsi-channel-names = "mcsaab-control",
"speech-control",
"speech-data",
"mcsaab-data";
hsi-speed-kbps = <55000>;
hsi-mode = "frame";
hsi-flow = "synchronized";
hsi-arb-mode = "round-robin";
interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
<&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
<&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
<&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
<&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
gpio-names = "cmt_apeslpx",
"cmt_rst_rq",
"cmt_en",
"cmt_rst",
"cmt_bsi";
};
};
&ssi_port2 {
status = "disabled";
};

45
arch/arm/boot/dts/omap3.dtsi
View File

@ -757,6 +757,51 @@
clock-names = "fck";
};
};
ssi: ssi-controller@48058000 {
compatible = "ti,omap3-ssi";
ti,hwmods = "ssi";
status = "disabled";
reg = <0x48058000 0x1000>,
<0x48059000 0x1000>;
reg-names = "sys",
"gdd";
interrupts = <71>;
interrupt-names = "gdd_mpu";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ssi_port1: ssi-port@4805a000 {
compatible = "ti,omap3-ssi-port";
reg = <0x4805a000 0x800>,
<0x4805a800 0x800>;
reg-names = "tx",
"rx";
interrupt-parent = <&intc>;
interrupts = <67>,
<68>;
};
ssi_port2: ssi-port@4805b000 {
compatible = "ti,omap3-ssi-port";
reg = <0x4805b000 0x800>,
<0x4805b800 0x800>;
reg-names = "tx",
"rx";
interrupt-parent = <&intc>;
interrupts = <69>,
<70>;
};
};
};
};

11
arch/arm/boot/dts/omap34xx.dtsi
View File

@ -40,6 +40,17 @@
};
};
&ssi {
status = "ok";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,
<&ssi_ick>;
clock-names = "ssi_ssr_fck",
"ssi_sst_fck",
"ssi_ick";
};
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

2
arch/arm/boot/dts/omap36xx-clocks.dtsi
View File

@ -83,7 +83,7 @@
};
&dpll4_m5x2_mul_ck {
clock-mult = <1>;
ti,clock-mult = <1>;
};
&dpll4_m6x2_mul_ck {

11
arch/arm/boot/dts/omap36xx.dtsi
View File

@ -78,6 +78,17 @@
clock-names = "fck", "tv_dac_clk";
};
&ssi {
status = "ok";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,
<&ssi_ick>;
clock-names = "ssi_ssr_fck",
"ssi_sst_fck",
"ssi_ick";
};
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

7
arch/arm/boot/dts/omap3xxx-clocks.dtsi
View File

@ -453,10 +453,11 @@
dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
compatible = "ti,fixed-factor-clock";
clocks = <&dpll4_m5_ck>;
clock-mult = <2>;
clock-div = <1>;
ti,clock-mult = <2>;
ti,clock-div = <1>;
ti,set-rate-parent;
};
dpll4_m5x2_ck: dpll4_m5x2_ck {

1
arch/arm/boot/dts/omap4.dtsi
View File

@ -67,6 +67,7 @@
local-timer@48240600 {
compatible = "arm,cortex-a9-twd-timer";
clocks = <&mpu_periphclk>;
reg = <0x48240600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
};

58
arch/arm/boot/dts/omap54xx-clocks.dtsi
View File

@ -120,10 +120,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
abe_24m_fclk: abe_24m_fclk {
@ -145,10 +143,11 @@
abe_iclk: abe_iclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&abe_clk>;
clock-mult = <1>;
clock-div = <2>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
ti,bit-shift = <24>;
reg = <0x0528>;
ti,dividers = <2>, <1>;
};
abe_lp_clk_div: abe_lp_clk_div {
@ -164,10 +163,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x01f4>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_ck: dpll_core_ck {
@ -188,10 +185,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0150>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
c2c_fclk: c2c_fclk {
@ -215,10 +210,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0138>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h12x2_ck: dpll_core_h12x2_ck {
@ -226,10 +219,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x013c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h13x2_ck: dpll_core_h13x2_ck {
@ -237,10 +228,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0140>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h14x2_ck: dpll_core_h14x2_ck {
@ -248,10 +237,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0144>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h22x2_ck: dpll_core_h22x2_ck {
@ -259,10 +246,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0154>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h23x2_ck: dpll_core_h23x2_ck {
@ -270,10 +255,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0158>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_h24x2_ck: dpll_core_h24x2_ck {
@ -281,10 +264,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x015c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_m2_ck: dpll_core_m2_ck {
@ -292,10 +273,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0130>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_core_m3x2_ck: dpll_core_m3x2_ck {
@ -303,10 +282,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0134>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@ -335,10 +312,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x01b8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
@ -346,10 +321,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x01bc>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
@ -372,10 +345,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0170>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
per_dpll_hs_clk_div: per_dpll_hs_clk_div {
@ -642,10 +613,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0158>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h12x2_ck: dpll_per_h12x2_ck {
@ -653,10 +622,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x015c>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_h14x2_ck: dpll_per_h14x2_ck {
@ -664,10 +631,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
ti,autoidle-shift = <8>;
reg = <0x0164>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_m2_ck: dpll_per_m2_ck {
@ -675,10 +640,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0150>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_m2x2_ck: dpll_per_m2x2_ck {
@ -686,10 +649,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0150>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_per_m3x2_ck: dpll_per_m3x2_ck {
@ -697,10 +658,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
reg = <0x0154>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_unipro1_ck: dpll_unipro1_ck {
@ -723,10 +682,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_unipro1_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
reg = <0x0210>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_unipro2_ck: dpll_unipro2_ck {
@ -749,10 +706,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_unipro2_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
reg = <0x01d0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
dpll_usb_ck: dpll_usb_ck {
@ -775,10 +730,8 @@
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
reg = <0x0190>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
};
func_128m_clk: func_128m_clk {
@ -851,6 +804,7 @@
clocks = <&dpll_per_h12x2_ck>;
ti,bit-shift = <8>;
reg = <0x1420>;
ti,set-rate-parent;
};
dss_sys_clk: dss_sys_clk {

2
arch/arm/mach-omap2/gpmc-nand.c
View File

@ -46,7 +46,7 @@ static struct platform_device gpmc_nand_device = {
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
{
/* platforms which support all ECC schemes */
if (soc_is_am33xx() || cpu_is_omap44xx() ||
if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
soc_is_omap54xx() || soc_is_dra7xx())
return 1;

9
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -3689,12 +3689,9 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};

6
drivers/clk/ti/clk-43xx.c
View File

@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
{ .node_name = NULL },
};