clk: at91: move sam9x60's PLL register offsets to PMC header
Move SAM9X60's PLL register offsets to PMC header so that the definitions would also be available from arch/arm/mach-at91/pm_suspend.S. This is necessary to disable/enable PLLA for SAM9X60 on suspend/resume. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-7-git-send-email-claudiu.beznea@microchip.comalistair/sensors
Claudiu Beznea
Alexandre Belloni
parent
4a877560fe
commit
e13208ab5d
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@ -14,27 +14,8 @@
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#include "pmc.h"
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#define PMC_PLL_CTRL0 0xc
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#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
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#define PMC_PLL_CTRL0_ENPLL BIT(28)
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#define PMC_PLL_CTRL0_ENPLLCK BIT(29)
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#define PMC_PLL_CTRL0_ENLOCK BIT(31)
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#define PMC_PLL_CTRL1 0x10
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#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
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#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
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#define PMC_PLL_ACR 0x18
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#define PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL
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#define PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL
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#define PMC_PLL_ACR_UTMIVR BIT(12)
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#define PMC_PLL_ACR_UTMIBG BIT(13)
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#define PMC_PLL_ACR_LOOP_FILTER_MSK GENMASK(31, 24)
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#define PMC_PLL_UPDT 0x1c
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#define PMC_PLL_UPDT_UPDATE BIT(8)
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#define PMC_PLL_ISR0 0xec
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#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
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#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
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#define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
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#define UPLL_DIV 2
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@ -59,7 +40,7 @@ static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
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{
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unsigned int status;
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regmap_read(regmap, PMC_PLL_ISR0, &status);
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regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
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return !!(status & BIT(id));
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}
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@ -74,12 +55,12 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
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u32 val;
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spin_lock_irqsave(pll->lock, flags);
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regmap_write(regmap, PMC_PLL_UPDT, pll->id);
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regmap_write(regmap, AT91_PMC_PLL_UPDT, pll->id);
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regmap_read(regmap, PMC_PLL_CTRL0, &val);
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regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
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div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
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regmap_read(regmap, PMC_PLL_CTRL1, &val);
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regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
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mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
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if (sam9x60_pll_ready(regmap, pll->id) &&
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@ -88,39 +69,39 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
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return 0;
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}
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/* Recommended value for PMC_PLL_ACR */
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/* Recommended value for AT91_PMC_PLL_ACR */
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if (pll->characteristics->upll)
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val = PMC_PLL_ACR_DEFAULT_UPLL;
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val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
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else
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val = PMC_PLL_ACR_DEFAULT_PLLA;
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regmap_write(regmap, PMC_PLL_ACR, val);
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val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
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regmap_write(regmap, AT91_PMC_PLL_ACR, val);
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regmap_write(regmap, PMC_PLL_CTRL1,
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regmap_write(regmap, AT91_PMC_PLL_CTRL1,
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FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
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if (pll->characteristics->upll) {
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/* Enable the UTMI internal bandgap */
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val |= PMC_PLL_ACR_UTMIBG;
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regmap_write(regmap, PMC_PLL_ACR, val);
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val |= AT91_PMC_PLL_ACR_UTMIBG;
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regmap_write(regmap, AT91_PMC_PLL_ACR, val);
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udelay(10);
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/* Enable the UTMI internal regulator */
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val |= PMC_PLL_ACR_UTMIVR;
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regmap_write(regmap, PMC_PLL_ACR, val);
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val |= AT91_PMC_PLL_ACR_UTMIVR;
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regmap_write(regmap, AT91_PMC_PLL_ACR, val);
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udelay(10);
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}
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regmap_update_bits(regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
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regmap_write(regmap, PMC_PLL_CTRL0,
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PMC_PLL_CTRL0_ENLOCK | PMC_PLL_CTRL0_ENPLL |
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PMC_PLL_CTRL0_ENPLLCK | pll->div);
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regmap_write(regmap, AT91_PMC_PLL_CTRL0,
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AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL |
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AT91_PMC_PLL_CTRL0_ENPLLCK | pll->div);
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regmap_update_bits(regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
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while (!sam9x60_pll_ready(regmap, pll->id))
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cpu_relax();
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@ -144,22 +125,24 @@ static void sam9x60_pll_unprepare(struct clk_hw *hw)
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spin_lock_irqsave(pll->lock, flags);
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regmap_write(pll->regmap, PMC_PLL_UPDT, pll->id);
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regmap_write(pll->regmap, AT91_PMC_PLL_UPDT, pll->id);
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regmap_update_bits(pll->regmap, PMC_PLL_CTRL0,
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PMC_PLL_CTRL0_ENPLLCK, 0);
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regmap_update_bits(pll->regmap, AT91_PMC_PLL_CTRL0,
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AT91_PMC_PLL_CTRL0_ENPLLCK, 0);
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regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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regmap_update_bits(pll->regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
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regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, PMC_PLL_CTRL0_ENPLL, 0);
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regmap_update_bits(pll->regmap, AT91_PMC_PLL_CTRL0,
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AT91_PMC_PLL_CTRL0_ENPLL, 0);
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if (pll->characteristics->upll)
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regmap_update_bits(pll->regmap, PMC_PLL_ACR,
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PMC_PLL_ACR_UTMIBG | PMC_PLL_ACR_UTMIVR, 0);
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regmap_update_bits(pll->regmap, AT91_PMC_PLL_ACR,
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AT91_PMC_PLL_ACR_UTMIBG |
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AT91_PMC_PLL_ACR_UTMIVR, 0);
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regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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regmap_update_bits(pll->regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_UPDATE, AT91_PMC_PLL_UPDT_UPDATE);
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spin_unlock_irqrestore(pll->lock, flags);
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}
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@ -316,10 +299,10 @@ sam9x60_clk_register_pll(struct regmap *regmap, spinlock_t *lock,
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pll->regmap = regmap;
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pll->lock = lock;
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regmap_write(regmap, PMC_PLL_UPDT, id);
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regmap_read(regmap, PMC_PLL_CTRL0, &pllr);
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regmap_write(regmap, AT91_PMC_PLL_UPDT, id);
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regmap_read(regmap, AT91_PMC_PLL_CTRL0, &pllr);
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pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr);
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regmap_read(regmap, PMC_PLL_CTRL1, &pllr);
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regmap_read(regmap, AT91_PMC_PLL_CTRL1, &pllr);
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pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr);
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hw = &pll->hw;
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@ -33,16 +33,34 @@
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#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
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#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
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#define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */
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#define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */
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#define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
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#define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */
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#define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */
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#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
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#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
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#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
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#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
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#define AT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL /* Default PLL ACR value for UPLL */
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#define AT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL /* Default PLL ACR value for PLLA */
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#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
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#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
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#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
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#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
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#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
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#define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */
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#define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */
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#define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */
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#define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */
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#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
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@ -183,6 +201,8 @@
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#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
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#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
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#define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */
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#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
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#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
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#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
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