MLK-20328-1: ASoC: fsl_sai: map number of pins to dataline masks
The patch enable mapping the number of pins required to play or record
a specific number of channels to a specific dataline mask.
Three consequent elements in "fsl,dataline" and "fsl,dataline,dsd" defines a
particular mapping, for instance for: fsl,dataline = "0 0xff 0xff 2 0x11 0x11"
there are two mappings defined:
default (0 pins) "rx" and "tx" dataline masks: 0 0xff 0xff
2 pins "rx" and "tx" dataline masks: 2 0x11 0x11
In case if property is missing, then default value "0 0x1 0x1" is considered.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This commit is contained in:
Viorel Suman
Dong Aisheng
parent
34ef089c73
commit
e138a5378b
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@ -621,17 +621,35 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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u32 slots = (channels == 1) ? 2 : channels;
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u32 slot_width = word_width;
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u32 pins, bclk;
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int ret;
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int i;
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int trce_mask = 0;
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int ret, i, trce_mask = 0, dl_cfg_cnt, dl_cfg_idx = 0;
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struct fsl_sai_dl_cfg *dl_cfg;
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if (sai->slots)
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slots = sai->slots;
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pins = DIV_ROUND_UP(channels, slots);
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sai->is_dsd = fsl_is_dsd(params);
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if (sai->is_dsd)
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if (sai->is_dsd) {
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pins = channels;
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dl_cfg = sai->dsd_dl_cfg;
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dl_cfg_cnt = sai->dsd_dl_cfg_cnt;
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} else {
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dl_cfg = sai->pcm_dl_cfg;
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dl_cfg_cnt = sai->pcm_dl_cfg_cnt;
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}
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for (i = 0; i < dl_cfg_cnt; i++) {
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if (dl_cfg[i].pins == pins) {
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dl_cfg_idx = i;
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break;
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}
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}
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if (dl_cfg_idx >= dl_cfg_cnt) {
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dev_err(cpu_dai->dev, "fsl,dataline%s invalid or not provided.\n",
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sai->is_dsd ? ",dsd" : "");
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return -EINVAL;
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}
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if (sai->slot_width)
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slot_width = sai->slot_width;
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@ -713,7 +731,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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if (sai->soc->dataline != 0x1) {
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if (sai->dataline[tx] <= 1 || sai->is_multi_lane)
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if (dl_cfg[dl_cfg_idx].mask[tx] <= 1 || sai->is_multi_lane)
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
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FSL_SAI_CR4_FCOMB_MASK, 0);
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else
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@ -724,21 +742,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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if (tx) {
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sai->dma_params_tx.maxburst =
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FSL_SAI_MAXBURST_TX * pins;
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if (sai->is_dsd)
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sai->dma_params_tx.fifo_num = pins +
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(sai->dataline_off_dsd[tx] << 4);
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else
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sai->dma_params_tx.fifo_num = pins +
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(sai->dataline_off[tx] << 4);
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sai->dma_params_tx.fifo_num = pins +
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(dl_cfg[dl_cfg_idx].offset[tx] << 4);
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} else {
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sai->dma_params_rx.maxburst =
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FSL_SAI_MAXBURST_RX * pins;
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if (sai->is_dsd)
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sai->dma_params_rx.fifo_num = pins +
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(sai->dataline_off_dsd[tx] << 4);
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else
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sai->dma_params_rx.fifo_num = pins +
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(sai->dataline_off[tx] << 4);
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sai->dma_params_rx.fifo_num = pins +
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(dl_cfg[dl_cfg_idx].offset[tx] << 4);
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}
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}
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@ -746,38 +756,22 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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&sai->dma_params_rx);
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}
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if (sai->is_dsd) {
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if (__sw_hweight8(sai->dataline_dsd[tx] & 0xFF) < pins) {
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dev_err(cpu_dai->dev, "channel not supported\n");
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return -EINVAL;
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}
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/*find a proper tcre setting*/
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for (i = 0; i < 8; i++) {
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trce_mask = (1 << (i + 1)) - 1;
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if (__sw_hweight8(sai->dataline_dsd[tx] & trce_mask) == pins)
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break;
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset),
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FSL_SAI_CR3_TRCE_MASK,
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FSL_SAI_CR3_TRCE((sai->dataline_dsd[tx] & trce_mask)));
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} else {
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if (__sw_hweight8(sai->dataline[tx] & 0xFF) < pins) {
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dev_err(cpu_dai->dev, "channel not supported\n");
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return -EINVAL;
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}
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/*find a proper tcre setting*/
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for (i = 0; i < 8; i++) {
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trce_mask = (1 << (i + 1)) - 1;
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if (__sw_hweight8(sai->dataline[tx] & trce_mask) == pins)
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break;
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset),
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FSL_SAI_CR3_TRCE_MASK,
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FSL_SAI_CR3_TRCE((sai->dataline[tx] & trce_mask)));
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if (__sw_hweight8(dl_cfg[dl_cfg_idx].mask[tx] & 0xFF) < pins) {
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dev_err(cpu_dai->dev, "channel not supported\n");
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return -EINVAL;
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}
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/*find a proper tcre setting*/
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for (i = 0; i < 8; i++) {
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trce_mask = (1 << (i + 1)) - 1;
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if (__sw_hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
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break;
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, offset),
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FSL_SAI_CR3_TRCE_MASK,
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FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
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FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
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FSL_SAI_CR4_CHMOD_MASK,
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@ -820,15 +814,32 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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u32 slots = (channels == 1) ? 2 : channels;
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u32 xcsr, count = 100;
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u32 pins;
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int i = 0, j = 0, k = 0;
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int i = 0, j = 0, k = 0, dl_cfg_cnt, dl_cfg_idx = 0;
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struct fsl_sai_dl_cfg *dl_cfg;
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if (sai->slots)
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slots = sai->slots;
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pins = DIV_ROUND_UP(channels, slots);
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if (sai->is_dsd)
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if (sai->is_dsd) {
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pins = channels;
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dl_cfg = sai->dsd_dl_cfg;
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dl_cfg_cnt = sai->dsd_dl_cfg_cnt;
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} else {
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dl_cfg = sai->pcm_dl_cfg;
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dl_cfg_cnt = sai->pcm_dl_cfg_cnt;
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}
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for (i = 0; i < dl_cfg_cnt; i++) {
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if (dl_cfg[i].pins == pins) {
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dl_cfg_idx = i;
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break;
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}
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}
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i = 0;
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/*
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* Asynchronous mode: Clear SYNC for both Tx and Rx.
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* Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
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@ -849,7 +860,7 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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while (tx && i < channels) {
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if ((sai->is_dsd ? sai->dataline_dsd[tx] : sai->dataline[tx]) & (1 << j)) {
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if (dl_cfg[dl_cfg_idx].mask[tx] & (1 << j)) {
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regmap_write(sai->regmap, FSL_SAI_TDR0 + j * 0x4, 0x0);
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i++;
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k++;
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@ -1262,6 +1273,77 @@ static const struct of_device_id fsl_sai_ids[] = {
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};
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MODULE_DEVICE_TABLE(of, fsl_sai_ids);
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static unsigned int fsl_sai_calc_dl_off(unsigned int* dl_mask)
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{
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int fbidx, nbidx, offset;
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fbidx = find_first_bit((const unsigned long *)dl_mask, 8);
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nbidx = find_next_bit((const unsigned long *)dl_mask, 8, fbidx+1);
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offset = nbidx - fbidx - 1;
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return (offset < 0 || offset >= 7 ? 0 : offset);
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}
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static int fsl_sai_read_dlcfg(struct platform_device *pdev, char *pn,
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struct fsl_sai_dl_cfg **rcfg, unsigned int soc_dl)
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{
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int ret, elems, i, index, num_cfg;
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struct device_node *np = pdev->dev.of_node;
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struct fsl_sai_dl_cfg *cfg;
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u32 rx, tx, pins;
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*rcfg = NULL;
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elems = of_property_count_u32_elems(np, pn);
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/* consider default value "0 0x1 0x1" if property is missing */
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if (elems <= 0)
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elems = 3;
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if (elems % 3) {
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dev_err(&pdev->dev,
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"Number of elements in %s must be divisible to 3.\n", pn);
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return -EINVAL;
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}
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num_cfg = elems / 3;
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cfg = devm_kzalloc(&pdev->dev, num_cfg * sizeof(*cfg), GFP_KERNEL);
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if (cfg == NULL) {
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dev_err(&pdev->dev, "Cannot allocate memory for %s.\n", pn);
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return -ENOMEM;
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}
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for (i = 0, index = 0; i < num_cfg; i++) {
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ret = of_property_read_u32_index(np, pn, index++, &pins);
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if (ret)
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pins = 0;
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ret = of_property_read_u32_index(np, pn, index++, &rx);
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if (ret)
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rx = 1;
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ret = of_property_read_u32_index(np, pn, index++, &tx);
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if (ret)
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tx = 1;
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if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
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dev_err(&pdev->dev,
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"%s: dataline cfg[%d] setting error, mask is 0x%x\n",
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pn, i, soc_dl);
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return -EINVAL;
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}
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cfg[i].pins = pins;
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cfg[i].mask[0] = rx;
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cfg[i].offset[0] = fsl_sai_calc_dl_off(&rx);
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cfg[i].mask[1] = tx;
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cfg[i].offset[1] = fsl_sai_calc_dl_off(&tx);
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}
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*rcfg = cfg;
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return num_cfg;
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}
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static int fsl_sai_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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@ -1273,7 +1355,6 @@ static int fsl_sai_probe(struct platform_device *pdev)
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char tmp[8];
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int irq, ret, i;
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int index;
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int firstbitidx, nextbitidx, offset;
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struct regmap_config fsl_sai_regmap_config = fsl_sai_v2_regmap_config;
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unsigned long irqflags = 0;
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@ -1340,45 +1421,19 @@ static int fsl_sai_probe(struct platform_device *pdev)
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sai->is_multi_lane = true;
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/*dataline mask for rx and tx*/
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ret = of_property_read_u32_index(np, "fsl,dataline", 0, &sai->dataline[0]);
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if (ret)
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sai->dataline[0] = 1;
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ret = fsl_sai_read_dlcfg(pdev, "fsl,dataline", &sai->pcm_dl_cfg,
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sai->soc->dataline);
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if (ret < 0)
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return ret;
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ret = of_property_read_u32_index(np, "fsl,dataline", 1, &sai->dataline[1]);
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if (ret)
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sai->dataline[1] = 1;
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sai->pcm_dl_cfg_cnt = ret;
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if ((sai->dataline[0] & (~sai->soc->dataline)) || sai->dataline[1] & (~sai->soc->dataline)) {
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dev_err(&pdev->dev, "dataline setting error, Mask is 0x%x\n", sai->soc->dataline);
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return -EINVAL;
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}
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ret = fsl_sai_read_dlcfg(pdev, "fsl,dataline,dsd", &sai->dsd_dl_cfg,
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sai->soc->dataline);
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if (ret < 0)
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return ret;
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for (i = 0; i < 2; i++) {
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firstbitidx = find_first_bit((const unsigned long *)&sai->dataline[i], 8);
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nextbitidx = find_next_bit((const unsigned long *)&sai->dataline[i], 8, firstbitidx+1);
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offset = nextbitidx - firstbitidx - 1;
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sai->dataline_off[i] = (offset < 0 || offset >= 7 ? 0 : offset);
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}
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ret = of_property_read_u32_index(np, "fsl,dataline,dsd", 0, &sai->dataline_dsd[0]);
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if (ret)
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sai->dataline_dsd[0] = 1;
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ret = of_property_read_u32_index(np, "fsl,dataline,dsd", 1, &sai->dataline_dsd[1]);
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if (ret)
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sai->dataline_dsd[1] = 1;
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if ((sai->dataline_dsd[0] & (~sai->soc->dataline)) || sai->dataline_dsd[1] & (~sai->soc->dataline)) {
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dev_err(&pdev->dev, "dataline setting error, Mask is 0x%x\n", sai->soc->dataline);
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return -EINVAL;
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}
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for (i = 0; i < 2; i++) {
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firstbitidx = find_first_bit((const unsigned long *)&sai->dataline_dsd[i], 8);
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nextbitidx = find_next_bit((const unsigned long *)&sai->dataline_dsd[i], 8, firstbitidx+1);
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offset = nextbitidx - firstbitidx - 1;
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sai->dataline_off_dsd[i] = (offset < 0 || offset >= 7 ? 0 : offset);
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}
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sai->dsd_dl_cfg_cnt = ret;
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if ((of_find_property(np, "fsl,i2s-xtor", NULL) != NULL) ||
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(of_find_property(np, "fsl,txm-rxs", NULL) != NULL))
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@ -234,6 +234,12 @@ struct fsl_sai_param {
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u32 dln; /* number of datalines implemented */
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};
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struct fsl_sai_dl_cfg {
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unsigned int pins;
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unsigned int mask[2];
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unsigned int offset[2];
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};
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struct fsl_sai {
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struct platform_device *pdev;
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struct regmap *regmap;
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@ -249,10 +255,12 @@ struct fsl_sai {
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bool synchronous[2];
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bool is_stream_opened[2];
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bool is_dsd;
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unsigned int dataline[2];
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unsigned int dataline_dsd[2];
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unsigned int dataline_off[2];
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unsigned int dataline_off_dsd[2];
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int pcm_dl_cfg_cnt;
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int dsd_dl_cfg_cnt;
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struct fsl_sai_dl_cfg *pcm_dl_cfg;
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struct fsl_sai_dl_cfg *dsd_dl_cfg;
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unsigned int masterflag[2];
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unsigned int mclk_id[2];
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