drm/radeon/si: restructure cg code (v3)
Resturcture clockgating code so that it can be enabled/disabled from other components such as dpm. v2: make function static v3: add fine grained cg controls Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
0116e1efaf
commit
e16866ecfb
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@ -159,6 +159,7 @@ extern int radeon_aspm;
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#define RADEON_CG_BLOCK_UVD (1 << 3)
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#define RADEON_CG_BLOCK_VCE (1 << 4)
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#define RADEON_CG_BLOCK_HDP (1 << 5)
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#define RADEON_CG_BLOCK_BIF (1 << 6)
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/* CG flags */
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#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
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@ -2340,7 +2340,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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rdev->cg_flags =
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RADEON_CG_SUPPORT_GFX_MGCG |
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RADEON_CG_SUPPORT_GFX_MGLS |
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RADEON_CG_SUPPORT_GFX_CGCG |
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/*RADEON_CG_SUPPORT_GFX_CGCG |*/
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RADEON_CG_SUPPORT_GFX_CGLS |
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RADEON_CG_SUPPORT_GFX_CGTS |
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RADEON_CG_SUPPORT_GFX_CP_LS |
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@ -2357,7 +2357,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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rdev->cg_flags =
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RADEON_CG_SUPPORT_GFX_MGCG |
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RADEON_CG_SUPPORT_GFX_MGLS |
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RADEON_CG_SUPPORT_GFX_CGCG |
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/*RADEON_CG_SUPPORT_GFX_CGCG |*/
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RADEON_CG_SUPPORT_GFX_CGLS |
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RADEON_CG_SUPPORT_GFX_CGTS |
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RADEON_CG_SUPPORT_GFX_CP_LS |
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@ -2376,7 +2376,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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rdev->cg_flags =
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RADEON_CG_SUPPORT_GFX_MGCG |
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RADEON_CG_SUPPORT_GFX_MGLS |
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RADEON_CG_SUPPORT_GFX_CGCG |
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/*RADEON_CG_SUPPORT_GFX_CGCG |*/
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RADEON_CG_SUPPORT_GFX_CGLS |
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RADEON_CG_SUPPORT_GFX_CGTS |
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RADEON_CG_SUPPORT_GFX_CP_LS |
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@ -2397,7 +2397,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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rdev->cg_flags =
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RADEON_CG_SUPPORT_GFX_MGCG |
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RADEON_CG_SUPPORT_GFX_MGLS |
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RADEON_CG_SUPPORT_GFX_CGCG |
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/*RADEON_CG_SUPPORT_GFX_CGCG |*/
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RADEON_CG_SUPPORT_GFX_CGLS |
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RADEON_CG_SUPPORT_GFX_CGTS |
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RADEON_CG_SUPPORT_GFX_CP_LS |
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@ -2415,7 +2415,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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rdev->cg_flags =
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RADEON_CG_SUPPORT_GFX_MGCG |
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RADEON_CG_SUPPORT_GFX_MGLS |
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RADEON_CG_SUPPORT_GFX_CGCG |
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/*RADEON_CG_SUPPORT_GFX_CGCG |*/
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RADEON_CG_SUPPORT_GFX_CGLS |
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RADEON_CG_SUPPORT_GFX_CGTS |
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RADEON_CG_SUPPORT_GFX_CP_LS |
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@ -4844,7 +4844,7 @@ static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
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u32 data, orig;
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orig = data = RREG32(DMA_PG);
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if (enable)
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if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
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data |= PG_CNTL_ENABLE;
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else
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data &= ~PG_CNTL_ENABLE;
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@ -4868,7 +4868,7 @@ static void si_enable_gfx_cgpg(struct radeon_device *rdev,
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{
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u32 tmp;
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if (enable) {
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if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
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tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
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WREG32(RLC_TTOP_D, tmp);
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@ -4973,7 +4973,7 @@ static void si_enable_cgcg(struct radeon_device *rdev,
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si_enable_gui_idle_interrupt(rdev, enable);
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if (enable) {
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
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WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
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tmp = si_halt_rlc(rdev);
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@ -5007,16 +5007,18 @@ static void si_enable_mgcg(struct radeon_device *rdev,
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{
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u32 data, orig, tmp = 0;
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if (enable) {
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
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orig = data = RREG32(CGTS_SM_CTRL_REG);
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data = 0x96940200;
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if (orig != data)
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WREG32(CGTS_SM_CTRL_REG, data);
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orig = data = RREG32(CP_MEM_SLP_CNTL);
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data |= CP_MEM_LS_EN;
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if (orig != data)
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WREG32(CP_MEM_SLP_CNTL, data);
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if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
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orig = data = RREG32(CP_MEM_SLP_CNTL);
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data |= CP_MEM_LS_EN;
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if (orig != data)
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WREG32(CP_MEM_SLP_CNTL, data);
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}
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orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
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data &= 0xffffffc0;
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@ -5061,7 +5063,7 @@ static void si_enable_uvd_mgcg(struct radeon_device *rdev,
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{
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u32 orig, data, tmp;
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if (enable) {
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
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tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
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tmp |= 0x3fff;
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WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
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@ -5109,7 +5111,7 @@ static void si_enable_mc_ls(struct radeon_device *rdev,
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for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
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orig = data = RREG32(mc_cg_registers[i]);
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if (enable)
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
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data |= MC_LS_ENABLE;
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else
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data &= ~MC_LS_ENABLE;
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@ -5118,19 +5120,158 @@ static void si_enable_mc_ls(struct radeon_device *rdev,
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}
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}
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static void si_enable_mc_mgcg(struct radeon_device *rdev,
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bool enable)
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{
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int i;
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u32 orig, data;
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for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
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orig = data = RREG32(mc_cg_registers[i]);
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
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data |= MC_CG_ENABLE;
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else
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data &= ~MC_CG_ENABLE;
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if (data != orig)
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WREG32(mc_cg_registers[i], data);
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}
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}
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static void si_enable_dma_mgcg(struct radeon_device *rdev,
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bool enable)
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{
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u32 orig, data, offset;
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int i;
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
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for (i = 0; i < 2; i++) {
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if (i == 0)
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offset = DMA0_REGISTER_OFFSET;
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else
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offset = DMA1_REGISTER_OFFSET;
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orig = data = RREG32(DMA_POWER_CNTL + offset);
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data &= ~MEM_POWER_OVERRIDE;
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if (data != orig)
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WREG32(DMA_POWER_CNTL + offset, data);
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WREG32(DMA_CLK_CTRL + offset, 0x00000100);
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}
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} else {
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for (i = 0; i < 2; i++) {
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if (i == 0)
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offset = DMA0_REGISTER_OFFSET;
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else
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offset = DMA1_REGISTER_OFFSET;
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orig = data = RREG32(DMA_POWER_CNTL + offset);
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data |= MEM_POWER_OVERRIDE;
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if (data != orig)
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WREG32(DMA_POWER_CNTL + offset, data);
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orig = data = RREG32(DMA_CLK_CTRL + offset);
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data = 0xff000000;
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if (data != orig)
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WREG32(DMA_CLK_CTRL + offset, data);
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}
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}
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}
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static void si_enable_bif_mgls(struct radeon_device *rdev,
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bool enable)
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{
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u32 orig, data;
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orig = data = RREG32_PCIE(PCIE_CNTL2);
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
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data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
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REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
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else
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data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
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REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
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if (orig != data)
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WREG32_PCIE(PCIE_CNTL2, data);
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}
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static void si_enable_hdp_mgcg(struct radeon_device *rdev,
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bool enable)
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{
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u32 orig, data;
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orig = data = RREG32(HDP_HOST_PATH_CNTL);
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
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data &= ~CLOCK_GATING_DIS;
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else
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data |= CLOCK_GATING_DIS;
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if (orig != data)
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WREG32(HDP_HOST_PATH_CNTL, data);
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}
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static void si_enable_hdp_ls(struct radeon_device *rdev,
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bool enable)
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{
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u32 orig, data;
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orig = data = RREG32(HDP_MEM_POWER_LS);
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
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data |= HDP_LS_ENABLE;
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else
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data &= ~HDP_LS_ENABLE;
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if (orig != data)
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WREG32(HDP_MEM_POWER_LS, data);
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}
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void si_update_cg(struct radeon_device *rdev,
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u32 block, bool enable)
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{
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if (block & RADEON_CG_BLOCK_GFX) {
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/* order matters! */
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if (enable) {
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si_enable_mgcg(rdev, true);
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si_enable_cgcg(rdev, true);
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} else {
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si_enable_cgcg(rdev, false);
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si_enable_mgcg(rdev, false);
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}
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}
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if (block & RADEON_CG_BLOCK_MC) {
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si_enable_mc_mgcg(rdev, enable);
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si_enable_mc_ls(rdev, enable);
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}
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if (block & RADEON_CG_BLOCK_SDMA) {
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si_enable_dma_mgcg(rdev, enable);
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}
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if (block & RADEON_CG_BLOCK_BIF) {
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si_enable_bif_mgls(rdev, enable);
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}
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if (block & RADEON_CG_BLOCK_UVD) {
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if (rdev->has_uvd) {
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si_enable_uvd_mgcg(rdev, enable);
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}
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}
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if (block & RADEON_CG_BLOCK_HDP) {
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si_enable_hdp_mgcg(rdev, enable);
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si_enable_hdp_ls(rdev, enable);
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}
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}
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static void si_init_cg(struct radeon_device *rdev)
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{
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if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)
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si_enable_mgcg(rdev, true);
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if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)
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si_enable_cgcg(rdev, false/*true*/);
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/* Disable MC LS on tahiti */
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if (!(rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
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si_enable_mc_ls(rdev, false);
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si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_MC |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), true);
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if (rdev->has_uvd) {
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if (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)
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si_enable_uvd_mgcg(rdev, true);
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si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
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si_init_uvd_internal_cg(rdev);
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}
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}
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@ -5138,13 +5279,20 @@ static void si_init_cg(struct radeon_device *rdev)
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static void si_fini_cg(struct radeon_device *rdev)
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{
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if (rdev->has_uvd) {
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if (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)
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si_enable_uvd_mgcg(rdev, false);
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si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
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}
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if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)
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si_enable_cgcg(rdev, false);
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if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)
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si_enable_mgcg(rdev, false);
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si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_MC |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), false);
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}
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void si_update_pg(struct radeon_device *rdev,
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bool enable)
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{
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si_enable_dma_pg(rdev, enable);
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si_enable_gfx_cgpg(rdev, enable);
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}
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static void si_init_pg(struct radeon_device *rdev)
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@ -5152,13 +5300,12 @@ static void si_init_pg(struct radeon_device *rdev)
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if (rdev->pg_flags) {
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if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
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si_init_dma_pg(rdev);
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si_enable_dma_pg(rdev, true);
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}
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si_init_ao_cu_mask(rdev);
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
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si_init_gfx_cgpg(rdev);
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si_enable_gfx_cgpg(rdev, true);
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}
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si_update_pg(rdev, false);
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} else {
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WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
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WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
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@ -6308,6 +6455,8 @@ int si_suspend(struct radeon_device *rdev)
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uvd_v1_0_fini(rdev);
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radeon_uvd_suspend(rdev);
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}
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si_fini_pg(rdev);
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si_fini_cg(rdev);
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si_irq_suspend(rdev);
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radeon_wb_disable(rdev);
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si_pcie_gart_disable(rdev);
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@ -6439,10 +6588,10 @@ void si_fini(struct radeon_device *rdev)
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{
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si_cp_fini(rdev);
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cayman_dma_fini(rdev);
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si_fini_pg(rdev);
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si_fini_cg(rdev);
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si_irq_fini(rdev);
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sumo_rlc_fini(rdev);
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si_fini_cg(rdev);
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si_fini_pg(rdev);
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radeon_wb_fini(rdev);
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radeon_vm_manager_fini(rdev);
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radeon_ib_pool_fini(rdev);
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@ -581,6 +581,7 @@
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#define CLKS_MASK (0xfff << 0)
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define CLOCK_GATING_DIS (1 << 23)
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#define HDP_NONSURFACE_BASE 0x2C04
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#define HDP_NONSURFACE_INFO 0x2C08
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#define HDP_NONSURFACE_SIZE 0x2C0C
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@ -588,6 +589,8 @@
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#define HDP_ADDR_CONFIG 0x2F48
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#define HDP_MISC_CNTL 0x2F4C
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#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
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#define HDP_MEM_POWER_LS 0x2F50
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#define HDP_LS_ENABLE (1 << 0)
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#define ATC_MISC_CG 0x3350
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@ -1354,6 +1357,7 @@
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/* PCIE registers idx/data 0x30/0x34 */
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#define PCIE_CNTL2 0x1c /* PCIE */
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# define SLV_MEM_LS_EN (1 << 16)
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# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
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# define MST_MEM_LS_EN (1 << 18)
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# define REPLAY_MEM_LS_EN (1 << 19)
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#define PCIE_LC_STATUS1 0x28 /* PCIE */
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@ -1703,6 +1707,10 @@
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# define DMA_IDLE (1 << 0)
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#define DMA_TILING_CONFIG 0xd0b8
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#define DMA_POWER_CNTL 0xd0bc
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# define MEM_POWER_OVERRIDE (1 << 8)
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#define DMA_CLK_CTRL 0xd0c0
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#define DMA_PG 0xd0d4
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# define PG_CNTL_ENABLE (1 << 0)
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#define DMA_PGFSM_CONFIG 0xd0d8
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