Clean up of hwmod to shrink down the IP block interconnections
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPqEK+AAoJEBvUPslcq6VzXKcP/03HGFNdBiO+V4QaaSY1YBJN DYZriahwtu2fwBGeo/y72Ol/ZShmiFWf7EKdn9HpvakoLL848rmiIB/6D1vk0MUb ywI+/ZIiiqpzaErPLmtGRNreNNJhnYSt7DhHmNQOOq+1uR5TsMNXF9IuRe6By+sv Kr1aiLMYK1UYkBTDg3wibctcMMF/f01/tJHnGTcOlqbF/pLlh8Q2QUQJ08QfLAdE ceAi6Vo7j2gnQ5rpNYdxa2T5iMiyJXLSazbrIpOx97Q6eWUZNaJdu5SQWbvcwBG2 MnErRbOPNixY43ht1FqBK7Idm9goNLeWjU6PM6iuVxfO9Q5JiL2+6gMCwGozFYX/ yuGdPSA430OMtLU2mMGbyRNPrXwnCe+/OGsJpLqqyw7X6mZisfhF6J+06BeIEk5N XI/3EH3TgientoCNYFunGBGwd/stRSqV8jjaX/TV7858ZQM2xtZp38zAK1E9wvDk D8HOGH77Tu7xXoWDL3G2kAX2gL/khqvrcUAJGFseuUmeyoEmHM/yhKlFy30Bl+MQ yRmqCghfisHsLTWKJGRLE3/tMg0M4PAaKo3IiE9LVlsg9tPJBE4hxKepi3WSNeUW qlzoiIMzpqSxkk1kPXnvfDdwWQMsrXvDEeaDO/aYuUFMEDNWbNN6Fvr8YJae7NCr cRRcnFFoebiyqamUybQo =qEmC -----END PGP SIGNATURE----- Merge tag 'omap-cleanup-hwmod-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup Clean up of hwmod to shrink down the IP block interconnections By Paul Walmsley via Paul Walmsley (1) and Tony Lindgren (1) * tag 'omap-cleanup-hwmod-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (29 commits) ARM: OMAP2xxx: hwmod data: start to fix the IVA1, IVA2 and DSP ARM: OMAP3: hwmod data: add IVA hard reset lines, main clock, clockdomain ARM: OMAP3: hwmod data: fix IVA interface clock ARM: OMAP2xxx: hwmod data: share common interface data ARM: OMAP2xxx: hwmod data: share common hwmods between OMAP2420 and OMAP2430 ARM: OMAP2+: hwmod data: remove forward declarations, reorganize ARM: OMAP: hwmod: remove code support for direct hwmod registration ARM: OMAP2+: hwmod data: convert to link registration ARM: OMAP2+: hwmod: add support for link registration ARM: OMAP2+: hwmod: consolidate finding the MPU port index and storing it ARM: OMAP2+: hwmod: add function to iterate over struct omap_hwmod_ocp_if ARM: OMAP2+: hwmod: add _find_mpu_rt_port() ARM: OMAP2+: hwmod: extend OCP_* register offsets from 16 to 32 bits ARM: OMAP4: hwmod data: uncomment some "excluded" hwmods ARM: OMAP4: hwmod data: add OCP_USER_DSP; mark omap44xx_dsp__iva appropriately ARM: OMAP4: hwmod data: remove bandgap hwmod ARM: OMAP3: hwmod data: GPTIMER12 is attached to a separate interconnect ARM: OMAP3: hwmod data: add DSS->L3 interconnect for 3430ES1 ARM: OMAP3: hwmod data: fix interfaces for the MMC hwmods ARM: OMAP2/3: hwmod data: update old names ... Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Olof Johansson
commit
e1851240a8
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@ -15,10 +15,12 @@
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#include <plat/omap_hwmod.h>
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#include <plat/serial.h>
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#include <plat/l3_2xxx.h>
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#include <plat/l4_2xxx.h>
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#include "omap_hwmod_common_data.h"
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struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
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static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
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{
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.pa_start = OMAP2_UART1_BASE,
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.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
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@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
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static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
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{
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.pa_start = OMAP2_UART2_BASE,
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.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
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@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
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static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
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{
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.pa_start = OMAP2_UART3_BASE,
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.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
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@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
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{
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.pa_start = 0x4802a000,
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.pa_end = 0x4802a000 + SZ_1K - 1,
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@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
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{
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.pa_start = 0x48078000,
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.pa_end = 0x48078000 + SZ_1K - 1,
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@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
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{
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.pa_start = 0x4807a000,
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.pa_end = 0x4807a000 + SZ_1K - 1,
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@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
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{
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.pa_start = 0x4807c000,
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.pa_end = 0x4807c000 + SZ_1K - 1,
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@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
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{
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.pa_start = 0x4807e000,
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.pa_end = 0x4807e000 + SZ_1K - 1,
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@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
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{
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.pa_start = 0x48080000,
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.pa_end = 0x48080000 + SZ_1K - 1,
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@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
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{
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.pa_start = 0x48082000,
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.pa_end = 0x48082000 + SZ_1K - 1,
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@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
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{ }
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};
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struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
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static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
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{
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.pa_start = 0x48084000,
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.pa_end = 0x48084000 + SZ_1K - 1,
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@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
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{ }
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};
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/*
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* Common interconnect data
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*/
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/* L3 -> L4_CORE interface */
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struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2xxx_l4_core_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* MPU -> L3 interface */
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struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
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.master = &omap2xxx_mpu_hwmod,
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.slave = &omap2xxx_l3_main_hwmod,
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.user = OCP_USER_MPU,
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};
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/* DSS -> l3 */
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struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
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.master = &omap2xxx_dss_core_hwmod,
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.slave = &omap2xxx_l3_main_hwmod,
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.fw = {
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.omap2 = {
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.l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
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.flags = OMAP_FIREWALL_L3,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4_CORE -> L4_WKUP interface */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_l4_wkup_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART1 interface */
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struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_uart1_hwmod,
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.clk = "uart1_ick",
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.addr = omap2xxx_uart1_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART2 interface */
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struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_uart2_hwmod,
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.clk = "uart2_ick",
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.addr = omap2xxx_uart2_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 PER -> UART3 interface */
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struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_uart3_hwmod,
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.clk = "uart3_ick",
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.addr = omap2xxx_uart3_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4 core -> mcspi1 interface */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_mcspi1_hwmod,
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.clk = "mcspi1_ick",
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.addr = omap2_mcspi1_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4 core -> mcspi2 interface */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_mcspi2_hwmod,
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.clk = "mcspi2_ick",
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.addr = omap2_mcspi2_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer2 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer2_hwmod,
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.clk = "gpt2_ick",
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.addr = omap2xxx_timer2_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer3 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer3_hwmod,
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.clk = "gpt3_ick",
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.addr = omap2xxx_timer3_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer4 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer4_hwmod,
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.clk = "gpt4_ick",
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.addr = omap2xxx_timer4_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer5 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer5_hwmod,
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.clk = "gpt5_ick",
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.addr = omap2xxx_timer5_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer6 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer6_hwmod,
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.clk = "gpt6_ick",
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.addr = omap2xxx_timer6_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer7 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer7_hwmod,
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.clk = "gpt7_ick",
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.addr = omap2xxx_timer7_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer8 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer8_hwmod,
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.clk = "gpt8_ick",
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.addr = omap2xxx_timer8_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer9 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer9_hwmod,
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.clk = "gpt9_ick",
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.addr = omap2xxx_timer9_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer10 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer10_hwmod,
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.clk = "gpt10_ick",
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.addr = omap2_timer10_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer11 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer11_hwmod,
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.clk = "gpt11_ick",
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.addr = omap2_timer11_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> timer12 */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_timer12_hwmod,
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.clk = "gpt12_ick",
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.addr = omap2xxx_timer12_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> dss */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_dss_core_hwmod,
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.clk = "dss_ick",
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.addr = omap2_dss_addrs,
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> dss_dispc */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_dss_dispc_hwmod,
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.clk = "dss_ick",
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.addr = omap2_dss_dispc_addrs,
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
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.flags = OMAP_FIREWALL_L4,
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}
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},
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> dss_rfbi */
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struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2xxx_dss_rfbi_hwmod,
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.clk = "dss_ick",
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.addr = omap2_dss_rfbi_addrs,
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.fw = {
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.omap2 = {
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.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
|
||||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> dss_venc */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_dss_venc_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2_dss_venc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
|
||||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.flags = OCPIF_SWSUP_IDLE,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
*/
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
#include <plat/gpio.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dmtimer.h>
|
||||
#include <plat/mcspi.h>
|
||||
|
|
@ -17,6 +18,8 @@
|
|||
#include <mach/irqs.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
#include "wd_timer.h"
|
||||
|
||||
struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
|
||||
|
|
@ -170,3 +173,562 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
|
|||
.sysc = &omap2xxx_mcspi_sysc,
|
||||
.rev = OMAP2_MCSPI_REV,
|
||||
};
|
||||
|
||||
/*
|
||||
* IP blocks
|
||||
*/
|
||||
|
||||
/* L3 */
|
||||
struct omap_hwmod omap2xxx_l3_main_hwmod = {
|
||||
.name = "l3_main",
|
||||
.class = &l3_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* L4 CORE */
|
||||
struct omap_hwmod omap2xxx_l4_core_hwmod = {
|
||||
.name = "l4_core",
|
||||
.class = &l4_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* L4 WKUP */
|
||||
struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
|
||||
.name = "l4_wkup",
|
||||
.class = &l4_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* MPU */
|
||||
struct omap_hwmod omap2xxx_mpu_hwmod = {
|
||||
.name = "mpu",
|
||||
.class = &mpu_hwmod_class,
|
||||
.main_clk = "mpu_ck",
|
||||
};
|
||||
|
||||
/* IVA2 */
|
||||
struct omap_hwmod omap2xxx_iva_hwmod = {
|
||||
.name = "iva",
|
||||
.class = &iva_hwmod_class,
|
||||
};
|
||||
|
||||
/* always-on timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_ALWON,
|
||||
};
|
||||
|
||||
/* pwm timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_HAS_PWM,
|
||||
};
|
||||
|
||||
/* timer1 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer1_hwmod = {
|
||||
.name = "timer1",
|
||||
.mpu_irqs = omap2_timer1_mpu_irqs,
|
||||
.main_clk = "gpt1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT1_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer2 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer2_hwmod = {
|
||||
.name = "timer2",
|
||||
.mpu_irqs = omap2_timer2_mpu_irqs,
|
||||
.main_clk = "gpt2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT2_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer3 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer3_hwmod = {
|
||||
.name = "timer3",
|
||||
.mpu_irqs = omap2_timer3_mpu_irqs,
|
||||
.main_clk = "gpt3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT3_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer4 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer4_hwmod = {
|
||||
.name = "timer4",
|
||||
.mpu_irqs = omap2_timer4_mpu_irqs,
|
||||
.main_clk = "gpt4_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT4_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer5 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer5_hwmod = {
|
||||
.name = "timer5",
|
||||
.mpu_irqs = omap2_timer5_mpu_irqs,
|
||||
.main_clk = "gpt5_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT5_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer6 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer6_hwmod = {
|
||||
.name = "timer6",
|
||||
.mpu_irqs = omap2_timer6_mpu_irqs,
|
||||
.main_clk = "gpt6_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT6_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer7 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer7_hwmod = {
|
||||
.name = "timer7",
|
||||
.mpu_irqs = omap2_timer7_mpu_irqs,
|
||||
.main_clk = "gpt7_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT7_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer8 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer8_hwmod = {
|
||||
.name = "timer8",
|
||||
.mpu_irqs = omap2_timer8_mpu_irqs,
|
||||
.main_clk = "gpt8_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT8_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer9 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer9_hwmod = {
|
||||
.name = "timer9",
|
||||
.mpu_irqs = omap2_timer9_mpu_irqs,
|
||||
.main_clk = "gpt9_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT9_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer10 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer10_hwmod = {
|
||||
.name = "timer10",
|
||||
.mpu_irqs = omap2_timer10_mpu_irqs,
|
||||
.main_clk = "gpt10_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT10_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer11 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer11_hwmod = {
|
||||
.name = "timer11",
|
||||
.mpu_irqs = omap2_timer11_mpu_irqs,
|
||||
.main_clk = "gpt11_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT11_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer12 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer12_hwmod = {
|
||||
.name = "timer12",
|
||||
.mpu_irqs = omap2xxx_timer12_mpu_irqs,
|
||||
.main_clk = "gpt12_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT12_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* wd_timer2 */
|
||||
struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
|
||||
.name = "wd_timer2",
|
||||
.class = &omap2xxx_wd_timer_hwmod_class,
|
||||
.main_clk = "mpu_wdt_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
|
||||
struct omap_hwmod omap2xxx_uart1_hwmod = {
|
||||
.name = "uart1",
|
||||
.mpu_irqs = omap2_uart1_mpu_irqs,
|
||||
.sdma_reqs = omap2_uart1_sdma_reqs,
|
||||
.main_clk = "uart1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_UART1_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2_uart_class,
|
||||
};
|
||||
|
||||
/* UART2 */
|
||||
|
||||
struct omap_hwmod omap2xxx_uart2_hwmod = {
|
||||
.name = "uart2",
|
||||
.mpu_irqs = omap2_uart2_mpu_irqs,
|
||||
.sdma_reqs = omap2_uart2_sdma_reqs,
|
||||
.main_clk = "uart2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_UART2_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2_uart_class,
|
||||
};
|
||||
|
||||
/* UART3 */
|
||||
|
||||
struct omap_hwmod omap2xxx_uart3_hwmod = {
|
||||
.name = "uart3",
|
||||
.mpu_irqs = omap2_uart3_mpu_irqs,
|
||||
.sdma_reqs = omap2_uart3_sdma_reqs,
|
||||
.main_clk = "uart3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 2,
|
||||
.module_bit = OMAP24XX_EN_UART3_SHIFT,
|
||||
.idlest_reg_id = 2,
|
||||
.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2_uart_class,
|
||||
};
|
||||
|
||||
/* dss */
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
|
||||
/*
|
||||
* The DSS HW needs all DSS clocks enabled during reset. The dss_core
|
||||
* driver does not use these clocks.
|
||||
*/
|
||||
{ .role = "tv_clk", .clk = "dss_54m_fck" },
|
||||
{ .role = "sys_clk", .clk = "dss2_fck" },
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_core_hwmod = {
|
||||
.name = "dss_core",
|
||||
.class = &omap2_dss_hwmod_class,
|
||||
.main_clk = "dss1_fck", /* instead of dss_fck */
|
||||
.sdma_reqs = omap2xxx_dss_sdma_chs,
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
|
||||
.flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
|
||||
.name = "dss_dispc",
|
||||
.class = &omap2_dispc_hwmod_class,
|
||||
.mpu_irqs = omap2_dispc_irqs,
|
||||
.main_clk = "dss1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
|
||||
},
|
||||
},
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
.dev_attr = &omap2_3_dss_dispc_dev_attr
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
|
||||
{ .role = "ick", .clk = "dss_ick" },
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
|
||||
.name = "dss_rfbi",
|
||||
.class = &omap2_rfbi_hwmod_class,
|
||||
.main_clk = "dss1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_rfbi_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_venc_hwmod = {
|
||||
.name = "dss_venc",
|
||||
.class = &omap2_venc_hwmod_class,
|
||||
.main_clk = "dss_54m_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
},
|
||||
},
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* gpio dev_attr */
|
||||
struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
|
||||
.bank_width = 32,
|
||||
.dbck_flag = false,
|
||||
};
|
||||
|
||||
/* gpio1 */
|
||||
struct omap_hwmod omap2xxx_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio1_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* gpio2 */
|
||||
struct omap_hwmod omap2xxx_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio2_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* gpio3 */
|
||||
struct omap_hwmod omap2xxx_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio3_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* gpio4 */
|
||||
struct omap_hwmod omap2xxx_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio4_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* mcspi1 */
|
||||
static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
|
||||
.num_chipselect = 4,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_mcspi1_hwmod = {
|
||||
.name = "mcspi1",
|
||||
.mpu_irqs = omap2_mcspi1_mpu_irqs,
|
||||
.sdma_reqs = omap2_mcspi1_sdma_reqs,
|
||||
.main_clk = "mcspi1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi1_dev_attr,
|
||||
};
|
||||
|
||||
/* mcspi2 */
|
||||
static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
|
||||
.num_chipselect = 2,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_mcspi2_hwmod = {
|
||||
.name = "mcspi2",
|
||||
.mpu_irqs = omap2_mcspi2_mpu_irqs,
|
||||
.sdma_reqs = omap2_mcspi2_sdma_reqs,
|
||||
.main_clk = "mcspi2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi2_dev_attr,
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -19,18 +19,6 @@
|
|||
#include "display.h"
|
||||
|
||||
/* Common address space across OMAP2xxx */
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
|
||||
|
||||
/* Common address space across OMAP2xxx/3xxx */
|
||||
|
|
@ -54,6 +42,64 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
|
|||
/* Common IP block data across OMAP2xxx */
|
||||
extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
|
||||
extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
|
||||
extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
|
||||
extern struct omap_hwmod omap2xxx_l3_main_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_l4_core_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_mpu_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_iva_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer3_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer4_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer5_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer6_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer7_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer8_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer9_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer10_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer11_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer12_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_uart1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_uart2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_uart3_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_core_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio3_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio4_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
|
||||
|
||||
/* Common interface data across OMAP2xxx */
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
|
||||
extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
|
||||
extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
|
||||
extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
|
||||
|
||||
/* Common IP block data */
|
||||
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
|
||||
|
|
@ -94,6 +140,7 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
|
|||
extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
|
||||
|
||||
/* OMAP hwmod classes - forward declarations */
|
||||
extern struct omap_hwmod_class l3_hwmod_class;
|
||||
|
|
|
|||
|
|
@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
|||
{
|
||||
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
|
||||
struct omap_hwmod *oh;
|
||||
struct resource irq_rsrc, mem_rsrc;
|
||||
size_t size;
|
||||
int res = 0;
|
||||
int r;
|
||||
|
||||
sprintf(name, "timer%d", gptimer_id);
|
||||
omap_hwmod_setup_one(name);
|
||||
|
|
@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
|||
if (!oh)
|
||||
return -ENODEV;
|
||||
|
||||
timer->irq = oh->mpu_irqs[0].irq;
|
||||
timer->phys_base = oh->slaves[0]->addr->pa_start;
|
||||
size = oh->slaves[0]->addr->pa_end - timer->phys_base;
|
||||
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
|
||||
if (r)
|
||||
return -ENXIO;
|
||||
timer->irq = irq_rsrc.start;
|
||||
|
||||
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
|
||||
if (r)
|
||||
return -ENXIO;
|
||||
timer->phys_base = mem_rsrc.start;
|
||||
size = mem_rsrc.end - mem_rsrc.start;
|
||||
|
||||
/* Static mapping, never released */
|
||||
timer->io_base = ioremap(timer->phys_base, size);
|
||||
|
|
|
|||
|
|
@ -213,11 +213,16 @@ struct omap_hwmod_addr_space {
|
|||
*/
|
||||
#define OCP_USER_MPU (1 << 0)
|
||||
#define OCP_USER_SDMA (1 << 1)
|
||||
#define OCP_USER_DSP (1 << 2)
|
||||
|
||||
/* omap_hwmod_ocp_if.flags bits */
|
||||
#define OCPIF_SWSUP_IDLE (1 << 0)
|
||||
#define OCPIF_CAN_BURST (1 << 1)
|
||||
|
||||
/* omap_hwmod_ocp_if._int_flags possibilities */
|
||||
#define _OCPIF_INT_FLAGS_REGISTERED (1 << 0)
|
||||
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_ocp_if - OCP interface data
|
||||
* @master: struct omap_hwmod that initiates OCP transactions on this link
|
||||
|
|
@ -229,6 +234,7 @@ struct omap_hwmod_addr_space {
|
|||
* @width: OCP data width
|
||||
* @user: initiators using this interface (see OCP_USER_* macros above)
|
||||
* @flags: OCP interface flags (see OCPIF_* macros above)
|
||||
* @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
|
||||
*
|
||||
* It may also be useful to add a tag_cnt field for OCP2.x devices.
|
||||
*
|
||||
|
|
@ -247,6 +253,7 @@ struct omap_hwmod_ocp_if {
|
|||
u8 width;
|
||||
u8 user;
|
||||
u8 flags;
|
||||
u8 _int_flags;
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -327,9 +334,9 @@ struct omap_hwmod_sysc_fields {
|
|||
* then this field has to be populated with the correct offset structure.
|
||||
*/
|
||||
struct omap_hwmod_class_sysconfig {
|
||||
u16 rev_offs;
|
||||
u16 sysc_offs;
|
||||
u16 syss_offs;
|
||||
u32 rev_offs;
|
||||
u32 sysc_offs;
|
||||
u32 syss_offs;
|
||||
u16 sysc_flags;
|
||||
struct omap_hwmod_sysc_fields *sysc_fields;
|
||||
u8 srst_udelay;
|
||||
|
|
@ -475,6 +482,16 @@ struct omap_hwmod_class {
|
|||
int (*reset)(struct omap_hwmod *oh);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs
|
||||
* @ocp_if: OCP interface structure record pointer
|
||||
* @node: list_head pointing to next struct omap_hwmod_link in a list
|
||||
*/
|
||||
struct omap_hwmod_link {
|
||||
struct omap_hwmod_ocp_if *ocp_if;
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
|
||||
* @name: name of the hwmod
|
||||
|
|
@ -487,12 +504,10 @@ struct omap_hwmod_class {
|
|||
* @_clk: pointer to the main struct clk (filled in at runtime)
|
||||
* @opt_clks: other device clocks that drivers can request (0..*)
|
||||
* @voltdm: pointer to voltage domain (filled in at runtime)
|
||||
* @masters: ptr to array of OCP ifs that this hwmod can initiate on
|
||||
* @slaves: ptr to array of OCP ifs that this hwmod can respond on
|
||||
* @dev_attr: arbitrary device attributes that can be passed to the driver
|
||||
* @_sysc_cache: internal-use hwmod flags
|
||||
* @_mpu_rt_va: cached register target start address (internal use)
|
||||
* @_mpu_port_index: cached MPU register target slave ID (internal use)
|
||||
* @_mpu_port: cached MPU register target slave (internal use)
|
||||
* @opt_clks_cnt: number of @opt_clks
|
||||
* @master_cnt: number of @master entries
|
||||
* @slaves_cnt: number of @slave entries
|
||||
|
|
@ -511,6 +526,8 @@ struct omap_hwmod_class {
|
|||
*
|
||||
* Parameter names beginning with an underscore are managed internally by
|
||||
* the omap_hwmod code and should not be set during initialization.
|
||||
*
|
||||
* @masters and @slaves are now deprecated.
|
||||
*/
|
||||
struct omap_hwmod {
|
||||
const char *name;
|
||||
|
|
@ -529,15 +546,15 @@ struct omap_hwmod {
|
|||
struct omap_hwmod_opt_clk *opt_clks;
|
||||
char *clkdm_name;
|
||||
struct clockdomain *clkdm;
|
||||
struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
|
||||
struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
|
||||
struct list_head master_ports; /* connect to *_IA */
|
||||
struct list_head slave_ports; /* connect to *_TA */
|
||||
void *dev_attr;
|
||||
u32 _sysc_cache;
|
||||
void __iomem *_mpu_rt_va;
|
||||
spinlock_t _lock;
|
||||
struct list_head node;
|
||||
struct omap_hwmod_ocp_if *_mpu_port;
|
||||
u16 flags;
|
||||
u8 _mpu_port_index;
|
||||
u8 response_lat;
|
||||
u8 rst_lines_cnt;
|
||||
u8 opt_clks_cnt;
|
||||
|
|
@ -549,7 +566,6 @@ struct omap_hwmod {
|
|||
u8 _postsetup_state;
|
||||
};
|
||||
|
||||
int omap_hwmod_register(struct omap_hwmod **ohs);
|
||||
struct omap_hwmod *omap_hwmod_lookup(const char *name);
|
||||
int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
|
||||
void *data);
|
||||
|
|
@ -581,6 +597,8 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
|
|||
|
||||
int omap_hwmod_count_resources(struct omap_hwmod *oh);
|
||||
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
|
||||
int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
|
||||
const char *name, struct resource *res);
|
||||
|
||||
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
|
||||
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
|
||||
|
|
@ -619,4 +637,6 @@ extern int omap2430_hwmod_init(void);
|
|||
extern int omap3xxx_hwmod_init(void);
|
||||
extern int omap44xx_hwmod_init(void);
|
||||
|
||||
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue