ath9k: Handle 2-ANT AR9565 in MCI reset
The value programmed in the BTCOEX control register is different for each chip. This patch adds support for 2-ANT, 1-ANT solutions based on AR9565. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -821,6 +821,61 @@ static void ar9003_mci_osla_setup(struct ath_hw *ah, bool enable)
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AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1);
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}
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static void ar9003_mci_set_btcoex_ctrl_9565_1ANT(struct ath_hw *ah)
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{
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u32 regval;
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regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
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SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
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SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
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SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
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SM(1, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
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SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
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REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
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AR_BTCOEX_CTRL2_TX_CHAIN_MASK, 0x1);
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REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
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}
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static void ar9003_mci_set_btcoex_ctrl_9565_2ANT(struct ath_hw *ah)
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{
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u32 regval;
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regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
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SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
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SM(0, AR_BTCOEX_CTRL_PA_SHARED) |
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SM(0, AR_BTCOEX_CTRL_LNA_SHARED) |
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SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
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SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
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REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
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AR_BTCOEX_CTRL2_TX_CHAIN_MASK, 0x0);
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REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
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}
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static void ar9003_mci_set_btcoex_ctrl_9462(struct ath_hw *ah)
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{
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u32 regval;
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regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
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SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
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SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
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SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
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SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
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SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
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REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
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}
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int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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bool is_full_sleep)
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{
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@ -845,25 +900,16 @@ int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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* To avoid MCI state machine be affected by incoming remote MCI msgs,
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* MCI mode will be enabled later, right before reset the MCI TX and RX.
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*/
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regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
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SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
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SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
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SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
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SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
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SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
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if (AR_SREV_9565(ah)) {
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regval |= SM(1, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK);
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REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
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AR_BTCOEX_CTRL2_TX_CHAIN_MASK, 0x1);
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} else {
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regval |= SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
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SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK);
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}
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u8 ant = MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH);
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REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
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if (ant == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED)
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ar9003_mci_set_btcoex_ctrl_9565_1ANT(ah);
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else
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ar9003_mci_set_btcoex_ctrl_9565_2ANT(ah);
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} else {
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ar9003_mci_set_btcoex_ctrl_9462(ah);
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}
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if (is_2g && !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA))
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ar9003_mci_osla_setup(ah, true);
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@ -109,8 +109,15 @@ enum mci_gpm_coex_bt_update_flags_op {
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#define ATH_MCI_CONFIG_MCI_OBS_MASK (ATH_MCI_CONFIG_MCI_OBS_MCI | \
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ATH_MCI_CONFIG_MCI_OBS_TXRX | \
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ATH_MCI_CONFIG_MCI_OBS_BT)
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#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
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#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
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#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01
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#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
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#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03
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#define ATH_MCI_ANT_ARCH_3_ANT 0x04
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enum mci_message_header { /* length of payload */
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MCI_LNA_CTRL = 0x10, /* len = 0 */
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MCI_CONT_NACK = 0x20, /* len = 0 */
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