Blackfin: fix MPU page permission masks overflow when dealing with async memory
Attempting to use the MPU while doing XIP out of parallel flash hooked up to the async memory bus would often result in random crashes as the MPU slowly corrupted memory. The fallout here is that the async banks gain MPU protection from user space too. So any accesses have to go through the mmap() interface rather than just using hardcoded pointers. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -13,6 +13,7 @@
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/cplbinit.h>
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#include <asm/sections.h>
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/* Note: L1 stacks are CPU-private things, so we bluntly disable this
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feature in SMP mode, and use the per-CPU scratch SRAM bank only to
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@ -117,9 +118,16 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr,
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unsigned long flags)
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{
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unsigned long *mask = mm->context.page_rwx_mask;
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unsigned long page = addr >> 12;
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unsigned long idx = page >> 5;
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unsigned long bit = 1 << (page & 31);
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unsigned long page;
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unsigned long idx;
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unsigned long bit;
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if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
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page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
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else
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page = addr >> 12;
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idx = page >> 5;
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bit = 1 << (page & 31);
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if (flags & VM_READ)
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mask[idx] |= bit;
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@ -114,10 +114,15 @@ static noinline int dcplb_miss(unsigned int cpu)
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d_data = L2_DMEMORY;
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} else if (addr >= physical_mem_end) {
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
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addr &= ~(4 * 1024 * 1024 - 1);
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d_data &= ~PAGE_SIZE_4KB;
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d_data |= PAGE_SIZE_4MB;
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d_data |= CPLB_USER_RD | CPLB_USER_WR;
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mask = current_rwx_mask[cpu];
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if (mask) {
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int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
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int idx = page >> 5;
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int bit = 1 << (page & 31);
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if (mask[idx] & bit)
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d_data |= CPLB_USER_RD;
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}
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} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
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&& (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
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addr &= ~(1 * 1024 * 1024 - 1);
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@ -204,10 +209,19 @@ static noinline int icplb_miss(unsigned int cpu)
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i_data = L2_IMEMORY;
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} else if (addr >= physical_mem_end) {
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
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addr &= ~(4 * 1024 * 1024 - 1);
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i_data &= ~PAGE_SIZE_4KB;
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i_data |= PAGE_SIZE_4MB;
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i_data |= CPLB_USER_RD;
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if (!(status & FAULT_USERSUPV)) {
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unsigned long *mask = current_rwx_mask[cpu];
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if (mask) {
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int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
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int idx = page >> 5;
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int bit = 1 << (page & 31);
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mask += 2 * page_mask_nelts;
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if (mask[idx] & bit)
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i_data |= CPLB_USER_RD;
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}
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}
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} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
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&& (status & FAULT_USERSUPV)) {
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addr &= ~(1 * 1024 * 1024 - 1);
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@ -597,7 +597,12 @@ static __init void memory_setup(void)
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}
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#ifdef CONFIG_MPU
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#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
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page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
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ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
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#else
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page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
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#endif
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page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
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#endif
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