MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address
Though BCM6345 does not technically have the same MPI register layout than the other SoCs, reading the chip-select registers is done the same way, and particularly for chip-select 0, which is the boot flash. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -709,15 +709,9 @@ void __init board_prom_init(void)
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char cfe_version[32];
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u32 val;
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/* read base address of boot chip select (0)
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* 6345 does not have MPI but boots from standard
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* MIPS Flash address */
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if (BCMCPU_IS_6345())
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val = 0x1fc00000;
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else {
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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}
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/* read base address of boot chip select (0) */
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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boot_addr = (u8 *)KSEG1ADDR(val);
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/* dump cfe version */
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@ -893,12 +887,9 @@ int __init board_register_devices(void)
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bcm63xx_dsp_register(&board.dsp);
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/* read base address of boot chip select (0) */
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if (BCMCPU_IS_6345())
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val = 0x1fc00000;
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else {
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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}
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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mtd_resources[0].start = val;
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mtd_resources[0].end = 0x1FFFFFFF;
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@ -215,7 +215,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
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#define BCM_6345_ENETSW_BASE (0xdeadbeef)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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#define BCM_6345_MPI_BASE (0xdeadbeef)
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#define BCM_6345_MPI_BASE (0xfffe2000)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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