m68knommu: make ColdFire SYPCR and RSR register definitions absolute addresses
Make all definitions of the ColdFire Reset and System registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the abolsute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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@ -43,8 +43,8 @@
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#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
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#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
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#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
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#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
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#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
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@ -25,8 +25,8 @@
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/*
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* Define the 5249 SIM register set addresses.
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*/
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#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
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#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
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#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
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#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
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@ -26,8 +26,8 @@
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/*
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* Define the 525x SIM register set addresses.
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*/
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#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
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#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
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#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
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#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
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@ -23,8 +23,8 @@
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/*
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* Define the 5307 SIM register set addresses.
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*/
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#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
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#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
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#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
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#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
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@ -23,8 +23,8 @@
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/*
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* Define the 5407 SIM register set addresses.
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*/
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#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
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#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
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#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
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#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
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@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
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{
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local_irq_disable();
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/* Set watchdog to soft reset, and enabled */
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__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
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__raw_writeb(0xc0, MCFSIM_SYPCR);
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for (;;)
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/* wait for watchdog to timeout */;
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}
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