soc/tegra: pmc: Support systems where PMC is marked secure
On Tegra210 systems with new enough boot software, direct register accesses to PMC register space from the non-secure world are not allowed. Instead a monitor call may be used to read and write PMC registers. Add code to detect such a system by attempting to write a scratch register and detecting if the write happened or not. If not, we switch to doing all register accesses through the monitor call. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com>hifive-unleashed-5.1
Mikko Perttunen
Thierry Reding
parent
fa3bc04ef8
commit
e247deae1a
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@ -20,6 +20,7 @@
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#define pr_fmt(fmt) "tegra-pmc: " fmt
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#include <linux/arm-smccc.h>
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/debugfs.h>
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@ -145,6 +146,11 @@
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#define WAKE_AOWAKE_CTRL 0x4f4
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#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
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/* for secure PMC */
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#define TEGRA_SMC_PMC 0xc2fffe00
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#define TEGRA_SMC_PMC_READ 0xaa
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#define TEGRA_SMC_PMC_WRITE 0xbb
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struct tegra_powergate {
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struct generic_pm_domain genpd;
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struct tegra_pmc *pmc;
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@ -216,6 +222,7 @@ struct tegra_pmc_soc {
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bool has_gpu_clamps;
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bool needs_mbist_war;
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bool has_impl_33v_pwr;
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bool maybe_tz_only;
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const struct tegra_io_pad_soc *io_pads;
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unsigned int num_io_pads;
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@ -278,6 +285,7 @@ static const char * const tegra30_reset_sources[] = {
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* @scratch: pointer to I/O remapped region for scratch registers
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* @clk: pointer to pclk clock
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* @soc: pointer to SoC data structure
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* @tz_only: flag specifying if the PMC can only be accessed via TrustZone
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* @debugfs: pointer to debugfs entry
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* @rate: currently configured rate of pclk
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* @suspend_mode: lowest suspend mode available
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@ -308,6 +316,7 @@ struct tegra_pmc {
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struct dentry *debugfs;
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const struct tegra_pmc_soc *soc;
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bool tz_only;
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unsigned long rate;
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@ -346,13 +355,62 @@ to_powergate(struct generic_pm_domain *domain)
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static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
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{
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struct arm_smccc_res res;
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if (pmc->tz_only) {
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
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0, 0, 0, &res);
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if (res.a0) {
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if (pmc->dev)
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dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
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__func__, res.a0);
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else
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pr_warn("%s(): SMC failed: %lu\n", __func__,
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res.a0);
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}
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return res.a1;
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}
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return readl(pmc->base + offset);
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}
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static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
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unsigned long offset)
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{
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writel(value, pmc->base + offset);
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struct arm_smccc_res res;
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if (pmc->tz_only) {
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
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value, 0, 0, 0, 0, &res);
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if (res.a0) {
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if (pmc->dev)
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dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
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__func__, res.a0);
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else
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pr_warn("%s(): SMC failed: %lu\n", __func__,
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res.a0);
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}
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} else {
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writel(value, pmc->base + offset);
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}
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}
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static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
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{
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if (pmc->tz_only)
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return tegra_pmc_readl(pmc, offset);
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return readl(pmc->scratch + offset);
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}
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static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
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unsigned long offset)
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{
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if (pmc->tz_only)
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tegra_pmc_writel(pmc, value, offset);
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else
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writel(value, pmc->scratch + offset);
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}
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/*
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@ -776,7 +834,7 @@ static int tegra_pmc_restart_notify(struct notifier_block *this,
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const char *cmd = data;
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u32 value;
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value = readl(pmc->scratch + pmc->soc->regs->scratch0);
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value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
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value &= ~PMC_SCRATCH0_MODE_MASK;
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if (cmd) {
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@ -790,7 +848,7 @@ static int tegra_pmc_restart_notify(struct notifier_block *this,
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value |= PMC_SCRATCH0_MODE_RCM;
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}
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writel(value, pmc->scratch + pmc->soc->regs->scratch0);
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tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
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/* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
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value = tegra_pmc_readl(pmc, PMC_CNTRL);
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@ -2071,6 +2129,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
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.has_gpu_clamps = false,
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.needs_mbist_war = false,
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.has_impl_33v_pwr = false,
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.maybe_tz_only = false,
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.num_io_pads = 0,
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.io_pads = NULL,
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.num_pin_descs = 0,
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@ -2117,6 +2176,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
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.has_gpu_clamps = false,
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.needs_mbist_war = false,
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.has_impl_33v_pwr = false,
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.maybe_tz_only = false,
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.num_io_pads = 0,
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.io_pads = NULL,
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.num_pin_descs = 0,
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@ -2167,6 +2227,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
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.has_gpu_clamps = false,
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.needs_mbist_war = false,
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.has_impl_33v_pwr = false,
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.maybe_tz_only = false,
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.num_io_pads = 0,
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.io_pads = NULL,
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.num_pin_descs = 0,
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@ -2277,6 +2338,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
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.has_gpu_clamps = true,
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.needs_mbist_war = false,
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.has_impl_33v_pwr = false,
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.maybe_tz_only = false,
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.num_io_pads = ARRAY_SIZE(tegra124_io_pads),
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.io_pads = tegra124_io_pads,
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.num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
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@ -2382,6 +2444,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
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.has_gpu_clamps = true,
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.needs_mbist_war = true,
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.has_impl_33v_pwr = false,
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.maybe_tz_only = true,
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.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
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.io_pads = tegra210_io_pads,
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.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
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@ -2506,6 +2569,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
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.has_gpu_clamps = false,
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.needs_mbist_war = false,
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.has_impl_33v_pwr = true,
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.maybe_tz_only = false,
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.num_io_pads = ARRAY_SIZE(tegra186_io_pads),
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.io_pads = tegra186_io_pads,
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.num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
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@ -2585,6 +2649,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
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.has_gpu_clamps = false,
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.needs_mbist_war = false,
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.has_impl_33v_pwr = false,
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.maybe_tz_only = false,
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.num_io_pads = ARRAY_SIZE(tegra194_io_pads),
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.io_pads = tegra194_io_pads,
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.regs = &tegra186_pmc_regs,
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@ -2619,6 +2684,32 @@ static struct platform_driver tegra_pmc_driver = {
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};
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builtin_platform_driver(tegra_pmc_driver);
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static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
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{
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u32 value, saved;
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saved = readl(pmc->base + pmc->soc->regs->scratch0);
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value = saved ^ 0xffffffff;
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if (value == 0xffffffff)
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value = 0xdeadbeef;
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/* write pattern and read it back */
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writel(value, pmc->base + pmc->soc->regs->scratch0);
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value = readl(pmc->base + pmc->soc->regs->scratch0);
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/* if we read all-zeroes, access is restricted to TZ only */
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if (value == 0) {
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pr_info("access to PMC is restricted to TZ\n");
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return true;
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}
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/* restore original value */
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writel(saved, pmc->base + pmc->soc->regs->scratch0);
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return false;
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}
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/*
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* Early initialization to allow access to registers in the very early boot
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* process.
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@ -2681,6 +2772,9 @@ static int __init tegra_pmc_early_init(void)
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if (np) {
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pmc->soc = match->data;
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if (pmc->soc->maybe_tz_only)
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pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
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tegra_powergate_init(pmc, np);
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/*
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