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mach-davinci cleanup to make it easy to add PM support 

for DT-boot.
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Merge tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc

Pull DaVinci cleanup for v4.10 from Sekhar Nori:

mach-davinci cleanup to make it easy to add PM support
for DT-boot.

* tag 'davinci-for-v4.10/cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: PM: fix build when da850 not compiled in
  ARM: davinci: PM: cleanup: remove references to pdata
  ARM: davinci: PM: rework init, remove platform device
hifive-unleashed-5.1
Arnd Bergmann 2016-11-30 14:45:31 +01:00
parent e70a13e7d7 f7715b2999
commit e264ae280c
7 changed files with 62 additions and 117 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-davinci/Makefile
View File

@ -36,5 +36,7 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
# Power Management
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_HAVE_CLK) += pm_domain.o
ifeq ($(CONFIG_SUSPEND),y)
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pm.o sleep.o
endif

17
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -196,18 +196,6 @@ static struct platform_device da850_evm_norflash_device = {
.resource = da850_evm_norflash_resource,
};
static struct davinci_pm_config da850_pm_pdata = {
.sleepcount = 128,
};
static struct platform_device da850_pm_device = {
.name = "pm-davinci",
.dev = {
.platform_data = &da850_pm_pdata,
},
.id = -1,
};
/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
* (128K blocks). It may be used instead of the (default) SPI flash
* to boot, using TI's tools to install the secondary boot loader
@ -1457,10 +1445,7 @@ static __init void da850_evm_init(void)
if (ret)
pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
ret = da850_register_pm(&da850_pm_device);
if (ret)
pr_warn("%s: suspend registration failed: %d\n", __func__, ret);
davinci_pm_init();
da850_vpif_init();
ret = spi_register_board_info(da850evm_spi_info,

16
arch/arm/mach-davinci/board-mityomapl138.c
View File

@ -498,18 +498,6 @@ static void __init mityomapl138_config_emac(void)
pr_warn("emac registration failed: %d\n", ret);
}
static struct davinci_pm_config da850_pm_pdata = {
.sleepcount = 128,
};
static struct platform_device da850_pm_device = {
.name = "pm-davinci",
.dev = {
.platform_data = &da850_pm_pdata,
},
.id = -1,
};
static void __init mityomapl138_init(void)
{
int ret;
@ -559,9 +547,7 @@ static void __init mityomapl138_init(void)
if (ret)
pr_warn("cpuidle registration failed: %d\n", ret);
ret = da850_register_pm(&da850_pm_device);
if (ret)
pr_warn("suspend registration failed: %d\n", ret);
davinci_pm_init();
}
#ifdef CONFIG_SERIAL_8250_CONSOLE

1
arch/arm/mach-davinci/common.c
View File

@ -118,6 +118,5 @@ err:
void __init davinci_init_late(void)
{
davinci_cpufreq_init();
davinci_pm_init();
davinci_clk_disable_unused();
}

38
arch/arm/mach-davinci/da850.c
View File

@ -1172,44 +1172,6 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
}
#endif
int __init da850_register_pm(struct platform_device *pdev)
{
int ret;
struct davinci_pm_config *pdata = pdev->dev.platform_data;
ret = davinci_cfg_reg(DA850_RTC_ALARM);
if (ret)
return ret;
pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
if (!pdata->cpupll_reg_base)
return -ENOMEM;
pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
if (!pdata->ddrpll_reg_base) {
ret = -ENOMEM;
goto no_ddrpll_mem;
}
pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
if (!pdata->ddrpsc_reg_base) {
ret = -ENOMEM;
goto no_ddrpsc_mem;
}
return platform_device_register(pdev);
no_ddrpsc_mem:
iounmap(pdata->ddrpll_reg_base);
no_ddrpll_mem:
iounmap(pdata->cpupll_reg_base);
return ret;
}
/* VPIF resource, platform data */
static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);

1
arch/arm/mach-davinci/include/mach/da8xx.h
View File

@ -106,7 +106,6 @@ int da8xx_register_gpio(void *pdata);
int da850_register_cpufreq(char *async_clk);
int da8xx_register_cpuidle(void);
void __iomem *da8xx_get_mem_ctlr(void);
int da850_register_pm(struct platform_device *pdev);
int da850_register_sata(unsigned long refclkpn);
int da850_register_vpif(void);
int da850_register_vpif_display

102
arch/arm/mach-davinci/pm.c
View File

@ -21,15 +21,22 @@
#include <mach/common.h>
#include <mach/da8xx.h>
#include "sram.h"
#include <mach/mux.h>
#include <mach/pm.h>
#include "clock.h"
#include "psc.h"
#include "sram.h"
#define DA850_PLL1_BASE 0x01e1a000
#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
#define DEEPSLEEP_SLEEPCOUNT 128
static void (*davinci_sram_suspend) (struct davinci_pm_config *);
static struct davinci_pm_config *pdata;
static struct davinci_pm_config pm_config = {
.sleepcount = DEEPSLEEP_SLEEPCOUNT,
.ddrpsc_num = DA8XX_LPSC1_EMIF3C,
};
static void davinci_sram_push(void *dest, void *src, unsigned int size)
{
@ -41,58 +48,58 @@ static void davinci_pm_suspend(void)
{
unsigned val;
if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
/* Switch CPU PLL to bypass mode */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
udelay(PLL_BYPASS_TIME);
/* Powerdown CPU PLL */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val |= PLLCTL_PLLPWRDN;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
}
/* Configure sleep count in deep sleep register */
val = __raw_readl(pdata->deepsleep_reg);
val = __raw_readl(pm_config.deepsleep_reg);
val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
val |= pdata->sleepcount;
__raw_writel(val, pdata->deepsleep_reg);
val |= pm_config.sleepcount;
__raw_writel(val, pm_config.deepsleep_reg);
/* System goes to sleep in this call */
davinci_sram_suspend(pdata);
davinci_sram_suspend(&pm_config);
if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
/* put CPU PLL in reset */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLRST;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* put CPU PLL in power down */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLPWRDN;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* wait for CPU PLL reset */
udelay(PLL_RESET_TIME);
/* bring CPU PLL out of reset */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val |= PLLCTL_PLLRST;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* Wait for CPU PLL to lock */
udelay(PLL_LOCK_TIME);
/* Remove CPU PLL from bypass mode */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLENSRC;
val |= PLLCTL_PLLEN;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
}
}
@ -117,17 +124,36 @@ static const struct platform_suspend_ops davinci_pm_ops = {
.valid = suspend_valid_only_mem,
};
static int __init davinci_pm_probe(struct platform_device *pdev)
int __init davinci_pm_init(void)
{
pdata = pdev->dev.platform_data;
if (!pdata) {
dev_err(&pdev->dev, "cannot get platform data\n");
return -ENOENT;
int ret;
ret = davinci_cfg_reg(DA850_RTC_ALARM);
if (ret)
return ret;
pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
if (!pm_config.cpupll_reg_base)
return -ENOMEM;
pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
if (!pm_config.ddrpll_reg_base) {
ret = -ENOMEM;
goto no_ddrpll_mem;
}
pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
if (!pm_config.ddrpsc_reg_base) {
ret = -ENOMEM;
goto no_ddrpsc_mem;
}
davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
if (!davinci_sram_suspend) {
dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
pr_err("PM: cannot allocate SRAM memory\n");
return -ENOMEM;
}
@ -136,23 +162,9 @@ static int __init davinci_pm_probe(struct platform_device *pdev)
suspend_set_ops(&davinci_pm_ops);
return 0;
}
static int __exit davinci_pm_remove(struct platform_device *pdev)
{
sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
return 0;
}
static struct platform_driver davinci_pm_driver = {
.driver = {
.name = "pm-davinci",
},
.remove = __exit_p(davinci_pm_remove),
};
int __init davinci_pm_init(void)
{
return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
no_ddrpsc_mem:
iounmap(pm_config.ddrpll_reg_base);
no_ddrpll_mem:
iounmap(pm_config.cpupll_reg_base);
return ret;
}