powerpc/64: Clean up ppc64_caches using a struct per cache
We have two set of identical struct members for the I and D sides and mostly identical bunches of code to parse the device-tree to populate them. Instead make a ppc_cache_info structure with one copy for I and one for D Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>hifive-unleashed-5.1
Benjamin Herrenschmidt
Michael Ellerman
parent
5d451a87e5
commit
e2827fe5c1
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@ -30,19 +30,19 @@
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#define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT)
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#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
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struct ppc_cache_info {
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u32 size;
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u32 line_size;
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u32 block_size; /* L1 only */
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u32 log_block_size;
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u32 blocks_per_page;
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u32 sets;
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};
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struct ppc64_caches {
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u32 dsize; /* L1 d-cache size */
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u32 dline_size; /* L1 d-cache line size */
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u32 dblock_size; /* L1 d-cache block size */
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u32 log_dblock_size;
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u32 dblocks_per_page;
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u32 dsets;
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u32 isize; /* L1 i-cache size */
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u32 iline_size; /* L1 d-cache line size */
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u32 iblock_size; /* L1 i-cache block size */
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u32 log_iblock_size;
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u32 iblocks_per_page;
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u32 isets;
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struct ppc_cache_info l1d;
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struct ppc_cache_info l1i;
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};
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extern struct ppc64_caches ppc64_caches;
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@ -47,14 +47,14 @@ static inline void clear_page(void *addr)
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unsigned long iterations;
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unsigned long onex, twox, fourx, eightx;
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iterations = ppc64_caches.dblocks_per_page / 8;
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iterations = ppc64_caches.l1d.blocks_per_page / 8;
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/*
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* Some verisions of gcc use multiply instructions to
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* calculate the offsets so lets give it a hand to
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* do better.
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*/
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onex = ppc64_caches.dblock_size;
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onex = ppc64_caches.l1d.block_size;
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twox = onex << 1;
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fourx = onex << 2;
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eightx = onex << 3;
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@ -204,7 +204,7 @@ static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
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int i, size;
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#ifdef __powerpc64__
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size = ppc64_caches.dblock_size;
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size = ppc64_caches.l1d.block_size;
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#else
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size = L1_CACHE_BYTES;
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#endif
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@ -163,12 +163,12 @@ int main(void)
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DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
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#ifdef CONFIG_PPC64
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DEFINE(DCACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, dblock_size));
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DEFINE(DCACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, log_dblock_size));
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DEFINE(DCACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, dblocks_per_page));
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DEFINE(ICACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, iblock_size));
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DEFINE(ICACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, log_iblock_size));
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DEFINE(ICACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, iblocks_per_page));
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DEFINE(DCACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, l1d.block_size));
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DEFINE(DCACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, l1d.log_block_size));
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DEFINE(DCACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, l1d.blocks_per_page));
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DEFINE(ICACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, l1i.block_size));
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DEFINE(ICACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, l1i.log_block_size));
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DEFINE(ICACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, l1i.blocks_per_page));
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/* paca */
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DEFINE(PACA_SIZE, sizeof(struct paca_struct));
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DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index));
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@ -78,10 +78,14 @@ int spinning_secondaries;
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u64 ppc64_pft_size;
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struct ppc64_caches ppc64_caches = {
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.dblock_size = 0x40,
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.log_dblock_size = 6,
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.iblock_size = 0x40,
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.log_iblock_size = 6
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.l1d = {
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.block_size = 0x40,
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.log_block_size = 6,
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},
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.l1i = {
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.block_size = 0x40,
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.log_block_size = 6
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},
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};
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EXPORT_SYMBOL_GPL(ppc64_caches);
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@ -397,105 +401,98 @@ void smp_release_cpus(void)
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* cache informations about the CPU that will be used by cache flush
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* routines and/or provided to userland
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*/
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static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
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u32 bsize, u32 sets)
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{
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info->size = size;
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info->sets = sets;
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info->line_size = lsize;
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info->block_size = bsize;
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info->log_block_size = __ilog2(bsize);
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info->blocks_per_page = PAGE_SIZE / bsize;
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}
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static bool __init parse_cache_info(struct device_node *np,
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bool icache,
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struct ppc_cache_info *info)
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{
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static const char *ipropnames[] __initdata = {
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"i-cache-size",
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"i-cache-sets",
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"i-cache-block-size",
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"i-cache-line-size",
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};
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static const char *dpropnames[] __initdata = {
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"d-cache-size",
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"d-cache-sets",
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"d-cache-block-size",
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"d-cache-line-size",
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};
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const char **propnames = icache ? ipropnames : dpropnames;
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const __be32 *sizep, *lsizep, *bsizep, *setsp;
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u32 size, lsize, bsize, sets;
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bool success = true;
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size = 0;
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sets = -1u;
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lsize = bsize = cur_cpu_spec->dcache_bsize;
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sizep = of_get_property(np, propnames[0], NULL);
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if (sizep != NULL)
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size = be32_to_cpu(*sizep);
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setsp = of_get_property(np, propnames[1], NULL);
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if (setsp != NULL)
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sets = be32_to_cpu(*setsp);
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bsizep = of_get_property(np, propnames[2], NULL);
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lsizep = of_get_property(np, propnames[3], NULL);
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if (bsizep == NULL)
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bsizep = lsizep;
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if (lsizep != NULL)
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lsize = be32_to_cpu(*lsizep);
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if (bsizep != NULL)
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bsize = be32_to_cpu(*bsizep);
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if (sizep == NULL || bsizep == NULL || lsizep == NULL)
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success = false;
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/*
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* OF is weird .. it represents fully associative caches
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* as "1 way" which doesn't make much sense and doesn't
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* leave room for direct mapped. We'll assume that 0
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* in OF means direct mapped for that reason.
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*/
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if (sets == 1)
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sets = 0;
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else if (sets == 0)
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sets = 1;
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init_cache_info(info, size, lsize, bsize, sets);
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return success;
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}
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void __init initialize_cache_info(void)
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{
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struct device_node *np;
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unsigned long num_cpus = 0;
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DBG(" -> initialize_cache_info()\n");
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for_each_node_by_type(np, "cpu") {
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num_cpus += 1;
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np = of_find_node_by_type(NULL, "cpu");
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/*
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* We're assuming *all* of the CPUs have the same
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* d-cache and i-cache sizes... -Peter
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*/
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if (num_cpus == 1) {
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const __be32 *sizep, *lsizep, *bsizep, *setsp;
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u32 size, lsize, bsize, sets;
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/*
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* We're assuming *all* of the CPUs have the same
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* d-cache and i-cache sizes... -Peter
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*/
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if (np) {
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if (!parse_cache_info(np, false, &ppc64_caches.l1d))
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DBG("Argh, can't find dcache properties !\n");
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size = 0;
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sets = -1u;
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lsize = bsize = cur_cpu_spec->dcache_bsize;
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sizep = of_get_property(np, "d-cache-size", NULL);
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if (sizep != NULL)
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size = be32_to_cpu(*sizep);
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setsp = of_get_property(np, "d-cache-sets", NULL);
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if (setsp != NULL)
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sets = be32_to_cpu(*setsp);
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bsizep = of_get_property(np, "d-cache-block-size",
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NULL);
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lsizep = of_get_property(np, "d-cache-line-size",
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NULL);
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if (bsizep == NULL)
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bsizep = lsizep;
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if (lsizep != NULL)
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lsize = be32_to_cpu(*lsizep);
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if (bsizep != NULL)
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bsize = be32_to_cpu(*bsizep);
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if (sizep == NULL || bsizep == NULL || lsizep == NULL)
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DBG("Argh, can't find dcache properties ! "
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"sizep: %p, bsizep: %p, lsizep: %p\n",
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sizep, bsizep, lsizep);
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/*
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* OF is weird .. it represents fully associative caches
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* as "1 way" which doesn't make much sense and doesn't
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* leave room for direct mapped. We'll assume that 0
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* in OF means direct mapped for that reason.
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*/
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if (sets == 1)
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sets = 0;
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else if (sets == 0)
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sets = 1;
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ppc64_caches.dsize = size;
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ppc64_caches.dsets = sets;
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ppc64_caches.dline_size = lsize;
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ppc64_caches.dblock_size = bsize;
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ppc64_caches.log_dblock_size = __ilog2(bsize);
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ppc64_caches.dblocks_per_page = PAGE_SIZE / bsize;
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size = 0;
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sets = -1u;
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lsize = bsize = cur_cpu_spec->icache_bsize;
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sizep = of_get_property(np, "i-cache-size", NULL);
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if (sizep != NULL)
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size = be32_to_cpu(*sizep);
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setsp = of_get_property(np, "i-cache-sets", NULL);
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if (setsp != NULL)
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sets = be32_to_cpu(*setsp);
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bsizep = of_get_property(np, "i-cache-block-size",
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NULL);
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lsizep = of_get_property(np, "i-cache-line-size",
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NULL);
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if (bsizep == NULL)
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bsizep = lsizep;
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if (lsizep != NULL)
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lsize = be32_to_cpu(*lsizep);
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if (bsizep != NULL)
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bsize = be32_to_cpu(*bsizep);
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if (sizep == NULL || bsizep == NULL || lsizep == NULL)
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DBG("Argh, can't find icache properties ! "
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"sizep: %p, bsizep: %p, lsizep: %p\n",
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sizep, bsizep, lsizep);
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if (sets == 1)
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sets = 0;
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else if (sets == 0)
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sets = 1;
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ppc64_caches.isize = size;
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ppc64_caches.isets = sets;
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ppc64_caches.iline_size = lsize;
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ppc64_caches.iblock_size = bsize;
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ppc64_caches.log_iblock_size = __ilog2(bsize);
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ppc64_caches.iblocks_per_page = PAGE_SIZE / bsize;
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}
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if (!parse_cache_info(np, true, &ppc64_caches.l1i))
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DBG("Argh, can't find icache properties !\n");
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}
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/* For use by binfmt_elf */
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dcache_bsize = ppc64_caches.dblock_size;
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icache_bsize = ppc64_caches.iblock_size;
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dcache_bsize = ppc64_caches.l1d.block_size;
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icache_bsize = ppc64_caches.l1i.block_size;
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DBG(" <- initialize_cache_info()\n");
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}
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@ -736,14 +736,14 @@ static int __init vdso_init(void)
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if (firmware_has_feature(FW_FEATURE_LPAR))
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vdso_data->platform |= 1;
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vdso_data->physicalMemorySize = memblock_phys_mem_size();
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vdso_data->dcache_size = ppc64_caches.dsize;
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vdso_data->dcache_line_size = ppc64_caches.dline_size;
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vdso_data->icache_size = ppc64_caches.isize;
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vdso_data->icache_line_size = ppc64_caches.iline_size;
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vdso_data->dcache_block_size = ppc64_caches.dblock_size;
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vdso_data->icache_block_size = ppc64_caches.iblock_size;
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vdso_data->dcache_log_block_size = ppc64_caches.log_dblock_size;
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vdso_data->icache_log_block_size = ppc64_caches.log_iblock_size;
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vdso_data->dcache_size = ppc64_caches.l1d.size;
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vdso_data->dcache_line_size = ppc64_caches.l1d.line_size;
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vdso_data->icache_size = ppc64_caches.l1i.size;
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vdso_data->icache_line_size = ppc64_caches.l1i.line_size;
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vdso_data->dcache_block_size = ppc64_caches.l1d.block_size;
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vdso_data->icache_block_size = ppc64_caches.l1i.block_size;
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vdso_data->dcache_log_block_size = ppc64_caches.l1d.log_block_size;
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vdso_data->icache_log_block_size = ppc64_caches.l1i.log_block_size;
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/*
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* Calculate the size of the 64 bits vDSO
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