drop Marco and add init dts stuff for Atlas7
CSR Marco SoC has never shipped to customers that could be interested in mainline support. and new Atlas7 is a replacement SoC that is in development. so we drop Marco dts stuff, and add dts stuff for Atlas7. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJUtmPZAAoJEDIv4aC191Rh3ZEQAI0kUJqgUAK8te3zHnQ0rUBp zawNk6N5D6KIFEue3hNDE6XlBhhKz8o5Npr7Wlp3WDRlA9gvSn0BYd5iQhRQjg3F hXRLPpK47pUPlq0RMLFNiYO4EwNQlA6ANBDe1sAUDWPiDplfkF0w5WXW8ZvPk3FL YXbumzH6JOrCzyMijOXKfJEtN/8qkgbm8mEQxwiuwLzzfmsuryOTbJbSvv8ogP4K hZEnfAP6MfR9Kk87a1XKMgs3DMuaWou6RXh6Vah4z0OlvtWLOmAy/j0tXs0Qe8Eh Kcms+zHHrmT9QyT82x/FK3ZCj0Q+HuI9mf3Gf54DKfYh9zMhjZH/y3ORFxHMiQFi ycSVO/LuLEB9J2X/3UDmnsl2YVds7v9Bf+8ZkMTprA1MKEpxWnZDIEH7cX5e192+ pgVBh7N9dbeLxgH6i6VtRXSRtjNqE+893o4qKYGagvzJhQ0XO5Dk1Em+LrkJIQeh pdpmgpKCWfT5RPJLpdUC93TUvpex+LlcCC5Obk107aEjGDeZCqJDYMl6J3YQdVIC 2oY5+hAmq5rxQ3D4KrXoSLmFr9pXQSNEav18dM00LZMnpoQlC/2EiuIsCv/b45EF w31fW0CM0C8kXDabkQjZOTcItz+nkJCb1KLvhm20Zcir2g9zM9iqW8QVcg6BYm10 KC+gpZpQvAszle4KW+v0 =wbyB -----END PGP SIGNATURE----- Merge tag 'atlas7-init-dts-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into next/dt Merge "CSR atlas7 init dts for 3.20" from Barry Song: Drop Marco and add init dts stuff for Atlas7 CSR Marco SoC has never shipped to customers that could be interested in mainline support. and new Atlas7 is a replacement SoC that is in development. So we drop Marco dts stuff, and add dts stuff for Atlas7. * tag 'atlas7-init-dts-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux: ARM: dts: add init dts file for CSR atlas7 SoC ARM: dts: drop MARCO platform DT stuff Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Olof Johansson
commit
e2a77c7ce4
|
|
@ -3,7 +3,9 @@ CSR SiRFprimaII and SiRFmarco device tree bindings.
|
|||
|
||||
Required root node properties:
|
||||
- compatible:
|
||||
- "sirf,atlas6-cb" : atlas6 "cb" evaluation board
|
||||
- "sirf,atlas6" : atlas6 device based board
|
||||
- "sirf,atlas7-cb" : atlas7 "cb" evaluation board
|
||||
- "sirf,atlas7" : atlas7 device based board
|
||||
- "sirf,prima2-cb" : prima2 "cb" evaluation board
|
||||
- "sirf,marco-cb" : marco "cb" evaluation board
|
||||
- "sirf,prima2" : prima2 device based board
|
||||
- "sirf,marco" : marco device based board
|
||||
|
|
|
|||
|
|
@ -53,6 +53,8 @@ dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
|
|||
|
||||
dtb-$(CONFIG_ARCH_ATLAS6) += \
|
||||
atlas6-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ATLAS7) += \
|
||||
atlas7-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_AXXIA) += \
|
||||
axm5516-amarillo.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += \
|
||||
|
|
@ -195,8 +197,6 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
|
|||
kirkwood-ts419-6282.dtb
|
||||
dtb-$(CONFIG_ARCH_LPC32XX) += \
|
||||
ea3250.dtb phy3250.dtb
|
||||
dtb-$(CONFIG_ARCH_MARCO) += \
|
||||
marco-evb.dtb
|
||||
dtb-$(CONFIG_MACH_MESON6) += \
|
||||
meson6-atv1200.dtb
|
||||
dtb-$(CONFIG_ARCH_MMP) += \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* DTS file for CSR SiRFatlas7 Evaluation Board
|
||||
*
|
||||
* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "atlas7.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CSR SiRFatlas7 Evaluation Board";
|
||||
compatible = "sirf,atlas7-cb", "sirf,atlas7";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySiRF1,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x20000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
vpp_reserved: vpp_mem@5e800000 {
|
||||
compatible = "sirf,reserved-memory";
|
||||
reg = <0x5e800000 0x800000>;
|
||||
};
|
||||
|
||||
nanddisk_reserved: nanddisk@46000000 {
|
||||
reg = <0x46000000 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
noc {
|
||||
mediam {
|
||||
nand@17050000 {
|
||||
memory-region = <&nanddisk_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
gnssm {
|
||||
spi1: spi@18200000 {
|
||||
status = "okay";
|
||||
spiflash: macronix@0{
|
||||
status = "okay";
|
||||
compatible = "macronix,mx25l6405d";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <37500000>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partitions@0 {
|
||||
label = "myspiboot";
|
||||
reg = <0x0 0x800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
btm {
|
||||
uart6: uart@11000000 {
|
||||
status = "okay";
|
||||
sirf,uart-has-rtscts;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg {
|
||||
vpp@13110000 {
|
||||
memory-region = <&vpp_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
display0: display@0 {
|
||||
compatible = "lvds-panel";
|
||||
source = "lvds.0";
|
||||
|
||||
bl-gpios = <&gpio_1 63 0>;
|
||||
data-lines = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <60000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hfront-porch = <220>;
|
||||
hback-porch = <100>;
|
||||
hsync-len = <1>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <25>;
|
||||
vsync-len = <1>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,813 @@
|
|||
/*
|
||||
* DTS file for CSR SiRFatlas7 SoC
|
||||
*
|
||||
* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
compatible = "sirf,atlas7";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
serial6 = &uart6;
|
||||
serial9 = &usp2;
|
||||
};
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
noc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10000000 0x10000000 0xc0000000>;
|
||||
|
||||
gic: interrupt-controller@10301000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x10301000 0x1000>,
|
||||
<0x10302000 0x0100>;
|
||||
};
|
||||
|
||||
pmu_regulator: pmu_regulator@10E30020 {
|
||||
compatible = "sirf,atlas7-pmu-ldo";
|
||||
reg = <0x10E30020 0x4>;
|
||||
ldo: ldo {
|
||||
regulator-name = "ldo";
|
||||
};
|
||||
};
|
||||
|
||||
atlas7_codec: atlas7_codec@10E30000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "sirf,atlas7-codec";
|
||||
reg = <0x10E30000 0x400>;
|
||||
clocks = <&car 62>;
|
||||
ldo-supply = <&ldo>;
|
||||
};
|
||||
|
||||
atlas7_iacc: atlas7_iacc@10D01000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "sirf,atlas7-iacc";
|
||||
reg = <0x10D01000 0x100>;
|
||||
dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
|
||||
<&dmac3 3>, <&dmac3 9>;
|
||||
dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
|
||||
clocks = <&car 62>;
|
||||
};
|
||||
|
||||
ipc@13240000 {
|
||||
compatible = "sirf,atlas7-ipc";
|
||||
ranges = <0x13240000 0x13240000 0x00010000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
hwspinlock {
|
||||
compatible = "sirf,hwspinlock";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
|
||||
num-spinlocks = <30>;
|
||||
};
|
||||
|
||||
ns_m3_rproc@0 {
|
||||
compatible = "sirf,ns2m30-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 123 0>;
|
||||
};
|
||||
|
||||
ns_m3_rproc@1 {
|
||||
compatible = "sirf,ns2m31-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 126 0>;
|
||||
};
|
||||
|
||||
ns_kal_rproc@0 {
|
||||
compatible = "sirf,ns2kal0-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 124 0>;
|
||||
};
|
||||
|
||||
ns_kal_rproc@1 {
|
||||
compatible = "sirf,ns2kal1-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 127 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl: ioc@18880000 {
|
||||
compatible = "sirf,atlas7-ioc";
|
||||
reg = <0x18880000 0x1000>,
|
||||
<0x10E40000 0x1000>;
|
||||
};
|
||||
|
||||
pmipc {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13240000 0x13240000 0x00010000>;
|
||||
pmipc@0x13240000 {
|
||||
compatible = "sirf,atlas7-pmipc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
dramfw {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10830000 0x10830000 0x18000>;
|
||||
dramfw@10820000 {
|
||||
compatible = "sirf,nocfw-dramfw";
|
||||
reg = <0x10830000 0x18000>;
|
||||
};
|
||||
};
|
||||
|
||||
spramfw {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10250000 0x10250000 0x3000>;
|
||||
spramfw@10820000 {
|
||||
compatible = "sirf,nocfw-spramfw";
|
||||
reg = <0x10250000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpum {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10200000 0x10200000 0x3000>;
|
||||
cpum@10200000 {
|
||||
compatible = "sirf,nocfw-cpum";
|
||||
reg = <0x10200000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
cgum {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x18641000 0x18641000 0x3000>,
|
||||
<0x18620000 0x18620000 0x1000>;
|
||||
|
||||
cgum@18641000 {
|
||||
compatible = "sirf,nocfw-cgum";
|
||||
reg = <0x18641000 0x3000>;
|
||||
};
|
||||
|
||||
car: clock-controller@18620000 {
|
||||
compatible = "sirf,atlas7-car";
|
||||
reg = <0x18620000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gnssm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x18000000 0x18000000 0x0000ffff>,
|
||||
<0x18010000 0x18010000 0x1000>,
|
||||
<0x18020000 0x18020000 0x1000>,
|
||||
<0x18030000 0x18030000 0x1000>,
|
||||
<0x18040000 0x18040000 0x1000>,
|
||||
<0x18050000 0x18050000 0x1000>,
|
||||
<0x18060000 0x18060000 0x1000>,
|
||||
<0x18100000 0x18100000 0x3000>,
|
||||
<0x18250000 0x18250000 0x10000>,
|
||||
<0x18200000 0x18200000 0x1000>;
|
||||
|
||||
dmac0: dma-controller@18000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x18000000 0x1000>;
|
||||
interrupts = <0 12 0>;
|
||||
clocks = <&car 89>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
gnssmfw@0x18100000 {
|
||||
compatible = "sirf,nocfw-gnssm";
|
||||
reg = <0x18100000 0x3000>;
|
||||
};
|
||||
|
||||
uart0: uart@18010000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18010000 0x1000>;
|
||||
interrupts = <0 17 0>;
|
||||
clocks = <&car 90>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 3>, <&dmac0 2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
uart1: uart@18020000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18020000 0x1000>;
|
||||
interrupts = <0 18 0>;
|
||||
clocks = <&car 88>;
|
||||
fifosize = <32>;
|
||||
};
|
||||
|
||||
uart2: uart@18030000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18030000 0x1000>;
|
||||
interrupts = <0 19 0>;
|
||||
clocks = <&car 91>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 6>, <&dmac0 7>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
uart3: uart@18040000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18040000 0x1000>;
|
||||
interrupts = <0 66 0>;
|
||||
clocks = <&car 92>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 4>, <&dmac0 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
uart4: uart@18050000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18050000 0x1000>;
|
||||
interrupts = <0 69 0>;
|
||||
clocks = <&car 93>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 0>, <&dmac0 1>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
uart5: uart@18060000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18060000 0x1000>;
|
||||
interrupts = <0 71 0>;
|
||||
clocks = <&car 94>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 8>, <&dmac0 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
dspub@18250000 {
|
||||
compatible = "dx,cc44p";
|
||||
reg = <0x18250000 0x10000>;
|
||||
interrupts = <0 27 0>;
|
||||
};
|
||||
|
||||
spi1: spi@18200000 {
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0x18200000 0x1000>;
|
||||
interrupts = <0 16 0>;
|
||||
clocks = <&car 95>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&dmac0 12>, <&dmac0 13>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
gpum {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13000000 0x13000000 0x3000>;
|
||||
gpum@0x13000000 {
|
||||
compatible = "sirf,nocfw-gpum";
|
||||
reg = <0x13000000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
mediam {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x16000000 0x16000000 0x00200000>,
|
||||
<0x17020000 0x17020000 0x1000>,
|
||||
<0x17030000 0x17030000 0x1000>,
|
||||
<0x17040000 0x17040000 0x1000>,
|
||||
<0x17050000 0x17050000 0x10000>,
|
||||
<0x17060000 0x17060000 0x200>,
|
||||
<0x17060200 0x17060200 0x100>,
|
||||
<0x17070000 0x17070000 0x200>,
|
||||
<0x17070200 0x17070200 0x100>,
|
||||
<0x170A0000 0x170A0000 0x3000>;
|
||||
|
||||
mediam@170A0000 {
|
||||
compatible = "sirf,nocfw-mediam";
|
||||
reg = <0x170A0000 0x3000>;
|
||||
};
|
||||
|
||||
gpio_0: gpio_mediam@17040000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas7-gpio";
|
||||
reg = <0x17040000 0x1000>;
|
||||
interrupts = <0 13 0>, <0 14 0>;
|
||||
clocks = <&car 107>;
|
||||
clock-names = "gpio0_io";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
nand@17050000 {
|
||||
compatible = "sirf,atlas7-nand";
|
||||
reg = <0x17050000 0x10000>;
|
||||
interrupts = <0 41 0>;
|
||||
clocks = <&car 108>, <&car 112>;
|
||||
clock-names = "nand_io", "nand_nand";
|
||||
};
|
||||
|
||||
sd0: sdhci@16000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x16000000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
clocks = <&car 109>, <&car 111>;
|
||||
clock-names = "core", "iface";
|
||||
wp-inverted;
|
||||
non-removable;
|
||||
status = "disabled";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
sd1: sdhci@16100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x16100000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
clocks = <&car 109>, <&car 111>;
|
||||
clock-names = "core", "iface";
|
||||
non-removable;
|
||||
status = "disabled";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
usb0: usb@17060000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-usb";
|
||||
reg = <0x17060000 0x200>;
|
||||
interrupts = <0 10 0>;
|
||||
clocks = <&car 113>;
|
||||
sirf,usbphy = <&usbphy0>;
|
||||
phy_type = "utmi";
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: usb@17070000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,atlas7-usb";
|
||||
reg = <0x17070000 0x200>;
|
||||
interrupts = <0 11 0>;
|
||||
clocks = <&car 114>;
|
||||
sirf,usbphy = <&usbphy1>;
|
||||
phy_type = "utmi";
|
||||
dr_mode = "host";
|
||||
maximum-speed = "high-speed";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
compatible = "sirf,atlas7-usbphy";
|
||||
reg = <0x17060200 0x100>;
|
||||
clocks = <&car 115>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@1 {
|
||||
compatible = "sirf,atlas7-usbphy";
|
||||
reg = <0x17070200 0x100>;
|
||||
clocks = <&car 116>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@17020000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0x17020000 0x1000>;
|
||||
interrupts = <0 24 0>;
|
||||
clocks = <&car 105>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
vdifm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13290000 0x13290000 0x3000>,
|
||||
<0x13300000 0x13300000 0x1000>,
|
||||
<0x14200000 0x14200000 0x600000>;
|
||||
|
||||
vdifm@13290000 {
|
||||
compatible = "sirf,nocfw-vdifm";
|
||||
reg = <0x13290000 0x3000>;
|
||||
};
|
||||
|
||||
gpio_1: gpio_vdifm@13300000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas7-gpio";
|
||||
reg = <0x13300000 0x1000>;
|
||||
interrupts = <0 43 0>, <0 44 0>, <0 45 0>;
|
||||
clocks = <&car 84>;
|
||||
clock-names = "gpio1_io";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sd2: sdhci@14200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14200000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
clocks = <&car 70>, <&car 75>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
vqmmc-supply = <&vqmmc>;
|
||||
vqmmc: vqmmc@2 {
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-name = "vqmmc-ldo";
|
||||
regulator-type = "voltage";
|
||||
regulator-boot-on;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
};
|
||||
|
||||
sd3: sdhci@14300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14300000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
clocks = <&car 76>, <&car 81>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sd5: sdhci@14500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14500000 0x100000>;
|
||||
interrupts = <0 39 0>;
|
||||
clocks = <&car 71>, <&car 76>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
loop-dma;
|
||||
};
|
||||
|
||||
sd6: sdhci@14600000 {
|
||||
cell-index = <6>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14600000 0x100000>;
|
||||
interrupts = <0 98 0>;
|
||||
clocks = <&car 72>, <&car 77>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sd7: sdhci@14700000 {
|
||||
cell-index = <7>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14700000 0x100000>;
|
||||
interrupts = <0 98 0>;
|
||||
clocks = <&car 72>, <&car 77>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
audiom {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10d50000 0x10d50000 0x0000ffff>,
|
||||
<0x10d60000 0x10d60000 0x0000ffff>,
|
||||
<0x10d80000 0x10d80000 0x0000ffff>,
|
||||
<0x10d90000 0x10d90000 0x0000ffff>,
|
||||
<0x10ED0000 0x10ED0000 0x3000>,
|
||||
<0x10dc8000 0x10dc8000 0x1000>,
|
||||
<0x10dc0000 0x10dc0000 0x1000>,
|
||||
<0x10db0000 0x10db0000 0x4000>,
|
||||
<0x10d40000 0x10d40000 0x1000>,
|
||||
<0x10d30000 0x10d30000 0x1000>;
|
||||
|
||||
timer@10dc0000 {
|
||||
compatible = "sirf,atlas7-tick";
|
||||
reg = <0x10dc0000 0x1000>;
|
||||
interrupts = <0 0 0>,
|
||||
<0 1 0>,
|
||||
<0 2 0>,
|
||||
<0 49 0>,
|
||||
<0 50 0>,
|
||||
<0 51 0>;
|
||||
clocks = <&car 47>;
|
||||
};
|
||||
|
||||
timerb@10dc8000 {
|
||||
compatible = "sirf,atlas7-tick";
|
||||
reg = <0x10dc8000 0x1000>;
|
||||
interrupts = <0 74 0>,
|
||||
<0 75 0>,
|
||||
<0 76 0>,
|
||||
<0 77 0>,
|
||||
<0 78 0>,
|
||||
<0 79 0>;
|
||||
clocks = <&car 47>;
|
||||
};
|
||||
|
||||
vip0@10db0000 {
|
||||
compatible = "sirf,atlas7-vip0";
|
||||
reg = <0x10db0000 0x2000>;
|
||||
interrupts = <0 85 0>;
|
||||
sirf,vip_cma_size = <0xC00000>;
|
||||
};
|
||||
|
||||
cvd@10db2000 {
|
||||
compatible = "sirf,cvd";
|
||||
reg = <0x10db2000 0x2000>;
|
||||
clocks = <&car 46>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@10d50000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x10d50000 0xffff>;
|
||||
interrupts = <0 55 0>;
|
||||
clocks = <&car 60>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
dmac3: dma-controller@10d60000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x10d60000 0xffff>;
|
||||
interrupts = <0 56 0>;
|
||||
clocks = <&car 61>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
adc: adc@10d80000 {
|
||||
compatible = "sirf,atlas7-adc";
|
||||
reg = <0x10d80000 0xffff>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&car 49>;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
pulsec@10d90000 {
|
||||
compatible = "sirf,prima2-pulsec";
|
||||
reg = <0x10d90000 0xffff>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&car 54>;
|
||||
};
|
||||
|
||||
audiom@10ED0000 {
|
||||
compatible = "sirf,nocfw-audiom";
|
||||
reg = <0x10ED0000 0x3000>;
|
||||
interrupts = <0 102 0>;
|
||||
};
|
||||
|
||||
usp1: usp@10d30000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x10d30000 0x1000>;
|
||||
fifosize = <512>;
|
||||
clocks = <&car 58>;
|
||||
dmas = <&dmac2 6>, <&dmac2 7>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
usp2: usp@10d40000 {
|
||||
cell-index = <2>;
|
||||
reg = <0x10d40000 0x1000>;
|
||||
interrupts = <0 22 0>;
|
||||
clocks = <&car 59>;
|
||||
dmas = <&dmac2 12>, <&dmac2 13>;
|
||||
dma-names = "rx", "tx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ddrm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10820000 0x10820000 0x3000>,
|
||||
<0x10800000 0x10800000 0x2000>;
|
||||
ddrm@10820000 {
|
||||
compatible = "sirf,nocfw-ddrm";
|
||||
reg = <0x10820000 0x3000>;
|
||||
interrupts = <0 105 0>;
|
||||
};
|
||||
|
||||
memory-controller@0x10800000 {
|
||||
compatible = "sirf,atlas7-memc";
|
||||
reg = <0x10800000 0x2000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
btm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x11002000 0x11002000 0x0000ffff>,
|
||||
<0x11010000 0x11010000 0x3000>,
|
||||
<0x11000000 0x11000000 0x1000>,
|
||||
<0x11001000 0x11001000 0x1000>;
|
||||
|
||||
dmac4: dma-controller@11002000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x11002000 0x1000>;
|
||||
interrupts = <0 99 0>;
|
||||
clocks = <&car 130>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
uart6: uart@11000000 {
|
||||
cell-index = <6>;
|
||||
compatible = "sirf,atlas7-bt-uart",
|
||||
"sirf,atlas7-uart";
|
||||
reg = <0x11000000 0x1000>;
|
||||
interrupts = <0 100 0>;
|
||||
clocks = <&car 131>, <&car 133>, <&car 134>;
|
||||
clock-names = "uart", "general", "noc";
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac4 12>, <&dmac4 13>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp3: usp@11001000 {
|
||||
compatible = "sirf,atlas7-bt-usp",
|
||||
"sirf,prima2-usp-pcm";
|
||||
cell-index = <3>;
|
||||
reg = <0x11001000 0x1000>;
|
||||
fifosize = <512>;
|
||||
clocks = <&car 132>, <&car 129>, <&car 133>,
|
||||
<&car 134>, <&car 135>;
|
||||
clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
|
||||
"noc_btm_io", "thbtm_io";
|
||||
dmas = <&dmac4 0>, <&dmac4 1>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
btm@11010000 {
|
||||
compatible = "sirf,nocfw-btm";
|
||||
reg = <0x11010000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
rtcm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x18810000 0x18810000 0x3000>,
|
||||
<0x18840000 0x18840000 0x1000>,
|
||||
<0x18890000 0x18890000 0x1000>,
|
||||
<0x188B0000 0x188B0000 0x10000>,
|
||||
<0x188D0000 0x188D0000 0x1000>;
|
||||
rtcm@18810000 {
|
||||
compatible = "sirf,nocfw-rtcm";
|
||||
reg = <0x18810000 0x3000>;
|
||||
interrupts = <0 109 0>;
|
||||
};
|
||||
|
||||
gpio_2: gpio_rtcm@18890000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas7-gpio";
|
||||
reg = <0x18890000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
rtc-iobg@18840000 {
|
||||
compatible = "sirf,prima2-rtciobg",
|
||||
"sirf-prima2-rtciobg-bus",
|
||||
"simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x18840000 0x1000>;
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,prima2-sysrtc";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
};
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,atlas7-pwrc";
|
||||
reg = <0x3000 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi: flash@188B0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-qspi-nor";
|
||||
reg = <0x188B0000 0x10000>;
|
||||
interrupts = <0 15 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
retain@0x188D0000 {
|
||||
compatible = "sirf,atlas7-retain";
|
||||
reg = <0x188D0000 0x1000>;
|
||||
};
|
||||
|
||||
};
|
||||
disp-iobg {
|
||||
/* lcdc0 */
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13100000 0x13100000 0x20000>,
|
||||
<0x10e10000 0x10e10000 0x10000>;
|
||||
|
||||
lcd@13100000 {
|
||||
compatible = "sirf,atlas7-lcdc";
|
||||
reg = <0x13100000 0x10000>;
|
||||
interrupts = <0 30 0>;
|
||||
clocks = <&car 79>;
|
||||
};
|
||||
vpp@13110000 {
|
||||
compatible = "sirf,atlas7-vpp";
|
||||
reg = <0x13110000 0x10000>;
|
||||
interrupts = <0 31 0>;
|
||||
clocks = <&car 78>;
|
||||
resets = <&car 29>;
|
||||
};
|
||||
lvds@10e10000 {
|
||||
compatible = "sirf,atlas7-lvdsc";
|
||||
reg = <0x10e10000 0x10000>;
|
||||
interrupts = <0 64 0>;
|
||||
clocks = <&car 54>;
|
||||
resets = <&car 29>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x12000000 0x12000000 0x1000000>;
|
||||
|
||||
graphics@12000000 {
|
||||
compatible = "powervr,sgx531";
|
||||
reg = <0x12000000 0x1000000>;
|
||||
interrupts = <0 6 0>;
|
||||
clocks = <&car 126>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* DTS file for CSR SiRFmarco Evaluation Board
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "marco.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CSR SiRFmarco Evaluation Board";
|
||||
compatible = "sirf,marco-cb", "sirf,marco";
|
||||
|
||||
memory {
|
||||
reg = <0x40000000 0x60000000>;
|
||||
};
|
||||
|
||||
axi {
|
||||
peri-iobg {
|
||||
uart1: uart@cc060000 {
|
||||
status = "okay";
|
||||
};
|
||||
uart2: uart@cc070000 {
|
||||
status = "okay";
|
||||
};
|
||||
i2c0: i2c@cc0e0000 {
|
||||
status = "okay";
|
||||
fpga-cpld@4d {
|
||||
compatible = "sirf,fpga-cpld";
|
||||
reg = <0x4d>;
|
||||
};
|
||||
};
|
||||
spi1: spi@cc170000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
spi@0 {
|
||||
compatible = "spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
pci-iobg {
|
||||
sd0: sdhci@cd000000 {
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,757 +0,0 @@
|
|||
/*
|
||||
* DTS file for CSR SiRFmarco SoC
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
compatible = "sirf,marco";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x40000000 0xa0000000>;
|
||||
|
||||
l2-cache-controller@c0030000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xc0030000 0x1000>;
|
||||
interrupts = <0 59 0>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,filter-ranges = <0x40000000 0x80000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@c0011000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xc0011000 0x1000>,
|
||||
<0xc0010100 0x0100>;
|
||||
};
|
||||
|
||||
rstc-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc2000000 0xc2000000 0x1000000>;
|
||||
|
||||
rstc: reset-controller@c2000000 {
|
||||
compatible = "sirf,marco-rstc";
|
||||
reg = <0xc2000000 0x10000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
sys-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc3000000 0xc3000000 0x1000000>;
|
||||
|
||||
clock-controller@c3000000 {
|
||||
compatible = "sirf,marco-clkc";
|
||||
reg = <0xc3000000 0x1000>;
|
||||
interrupts = <0 3 0>;
|
||||
};
|
||||
|
||||
rsc-controller@c3010000 {
|
||||
compatible = "sirf,marco-rsc";
|
||||
reg = <0xc3010000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
mem-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc4000000 0xc4000000 0x1000000>;
|
||||
|
||||
memory-controller@c4000000 {
|
||||
compatible = "sirf,marco-memc";
|
||||
reg = <0xc4000000 0x10000>;
|
||||
interrupts = <0 27 0>;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc5000000 0xc5000000 0x1000000>;
|
||||
|
||||
display0@c5000000 {
|
||||
compatible = "sirf,marco-lcd";
|
||||
reg = <0xc5000000 0x10000>;
|
||||
interrupts = <0 30 0>;
|
||||
};
|
||||
|
||||
vpp0@c5010000 {
|
||||
compatible = "sirf,marco-vpp";
|
||||
reg = <0xc5010000 0x10000>;
|
||||
interrupts = <0 31 0>;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg1 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc6000000 0xc6000000 0x1000000>;
|
||||
|
||||
display1@c6000000 {
|
||||
compatible = "sirf,marco-lcd";
|
||||
reg = <0xc6000000 0x10000>;
|
||||
interrupts = <0 62 0>;
|
||||
};
|
||||
|
||||
vpp1@c6010000 {
|
||||
compatible = "sirf,marco-vpp";
|
||||
reg = <0xc6010000 0x10000>;
|
||||
interrupts = <0 63 0>;
|
||||
};
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc8000000 0xc8000000 0x1000000>;
|
||||
|
||||
graphics@c8000000 {
|
||||
compatible = "powervr,sgx540";
|
||||
reg = <0xc8000000 0x1000000>;
|
||||
interrupts = <0 6 0>;
|
||||
};
|
||||
};
|
||||
|
||||
multimedia-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc9000000 0xc9000000 0x1000000>;
|
||||
|
||||
multimedia@a0000000 {
|
||||
compatible = "sirf,marco-video-codec";
|
||||
reg = <0xc9000000 0x1000000>;
|
||||
interrupts = <0 5 0>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xca000000 0xca000000 0x2000000>;
|
||||
|
||||
dspif@ca000000 {
|
||||
compatible = "sirf,marco-dspif";
|
||||
reg = <0xca000000 0x10000>;
|
||||
interrupts = <0 9 0>;
|
||||
};
|
||||
|
||||
gps@ca010000 {
|
||||
compatible = "sirf,marco-gps";
|
||||
reg = <0xca010000 0x10000>;
|
||||
interrupts = <0 7 0>;
|
||||
};
|
||||
|
||||
dsp@cb000000 {
|
||||
compatible = "sirf,marco-dsp";
|
||||
reg = <0xcb000000 0x1000000>;
|
||||
interrupts = <0 8 0>;
|
||||
};
|
||||
};
|
||||
|
||||
peri-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xcc000000 0xcc000000 0x2000000>;
|
||||
|
||||
timer@cc020000 {
|
||||
compatible = "sirf,marco-tick";
|
||||
reg = <0xcc020000 0x1000>;
|
||||
interrupts = <0 0 0>,
|
||||
<0 1 0>,
|
||||
<0 2 0>,
|
||||
<0 49 0>,
|
||||
<0 50 0>,
|
||||
<0 51 0>;
|
||||
};
|
||||
|
||||
nand@cc030000 {
|
||||
compatible = "sirf,marco-nand";
|
||||
reg = <0xcc030000 0x10000>;
|
||||
interrupts = <0 41 0>;
|
||||
};
|
||||
|
||||
audio@cc040000 {
|
||||
compatible = "sirf,marco-audio";
|
||||
reg = <0xcc040000 0x10000>;
|
||||
interrupts = <0 35 0>;
|
||||
};
|
||||
|
||||
uart0: uart@cc050000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc050000 0x1000>;
|
||||
interrupts = <0 17 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@cc060000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc060000 0x1000>;
|
||||
interrupts = <0 18 0>;
|
||||
fifosize = <32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@cc070000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc070000 0x1000>;
|
||||
interrupts = <0 19 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@cc190000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc190000 0x1000>;
|
||||
interrupts = <0 66 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: uart@cc1a0000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,marco-uart";
|
||||
reg = <0xcc1a0000 0x1000>;
|
||||
interrupts = <0 69 0>;
|
||||
fifosize = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp0: usp@cc080000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-usp";
|
||||
reg = <0xcc080000 0x10000>;
|
||||
interrupts = <0 20 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp1: usp@cc090000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-usp";
|
||||
reg = <0xcc090000 0x10000>;
|
||||
interrupts = <0 21 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp2: usp@cc0a0000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,marco-usp";
|
||||
reg = <0xcc0a0000 0x10000>;
|
||||
interrupts = <0 22 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac0: dma-controller@cc0b0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-dmac";
|
||||
reg = <0xcc0b0000 0x10000>;
|
||||
interrupts = <0 12 0>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@cc160000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-dmac";
|
||||
reg = <0xcc160000 0x10000>;
|
||||
interrupts = <0 13 0>;
|
||||
};
|
||||
|
||||
vip@cc0c0000 {
|
||||
compatible = "sirf,marco-vip";
|
||||
reg = <0xcc0c0000 0x10000>;
|
||||
};
|
||||
|
||||
spi0: spi@cc0d0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-spi";
|
||||
reg = <0xcc0d0000 0x10000>;
|
||||
interrupts = <0 15 0>;
|
||||
sirf,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio 0 0>;
|
||||
sirf,spi-dma-rx-channel = <25>;
|
||||
sirf,spi-dma-tx-channel = <20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@cc170000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-spi";
|
||||
reg = <0xcc170000 0x10000>;
|
||||
interrupts = <0 16 0>;
|
||||
sirf,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio 0 0>;
|
||||
sirf,spi-dma-rx-channel = <12>;
|
||||
sirf,spi-dma-tx-channel = <13>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@cc0e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-i2c";
|
||||
reg = <0xcc0e0000 0x10000>;
|
||||
interrupts = <0 24 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@cc0f0000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-i2c";
|
||||
reg = <0xcc0f0000 0x10000>;
|
||||
interrupts = <0 25 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsc@cc110000 {
|
||||
compatible = "sirf,marco-tsc";
|
||||
reg = <0xcc110000 0x10000>;
|
||||
interrupts = <0 33 0>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@cc120000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,marco-pinctrl";
|
||||
reg = <0xcc120000 0x10000>;
|
||||
interrupts = <0 43 0>,
|
||||
<0 44 0>,
|
||||
<0 45 0>,
|
||||
<0 46 0>,
|
||||
<0 47 0>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
||||
lcd_16pins_a: lcd0_0 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_16bitsgrp";
|
||||
sirf,function = "lcd_16bits";
|
||||
};
|
||||
};
|
||||
lcd_18pins_a: lcd0_1 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_18bitsgrp";
|
||||
sirf,function = "lcd_18bits";
|
||||
};
|
||||
};
|
||||
lcd_24pins_a: lcd0_2 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_24bitsgrp";
|
||||
sirf,function = "lcd_24bits";
|
||||
};
|
||||
};
|
||||
lcdrom_pins_a: lcdrom0_0 {
|
||||
lcd {
|
||||
sirf,pins = "lcdromgrp";
|
||||
sirf,function = "lcdrom";
|
||||
};
|
||||
};
|
||||
uart0_pins_a: uart0_0 {
|
||||
uart {
|
||||
sirf,pins = "uart0grp";
|
||||
sirf,function = "uart0";
|
||||
};
|
||||
};
|
||||
uart1_pins_a: uart1_0 {
|
||||
uart {
|
||||
sirf,pins = "uart1grp";
|
||||
sirf,function = "uart1";
|
||||
};
|
||||
};
|
||||
uart2_pins_a: uart2_0 {
|
||||
uart {
|
||||
sirf,pins = "uart2grp";
|
||||
sirf,function = "uart2";
|
||||
};
|
||||
};
|
||||
uart2_noflow_pins_a: uart2_1 {
|
||||
uart {
|
||||
sirf,pins = "uart2_nostreamctrlgrp";
|
||||
sirf,function = "uart2_nostreamctrl";
|
||||
};
|
||||
};
|
||||
spi0_pins_a: spi0_0 {
|
||||
spi {
|
||||
sirf,pins = "spi0grp";
|
||||
sirf,function = "spi0";
|
||||
};
|
||||
};
|
||||
spi1_pins_a: spi1_0 {
|
||||
spi {
|
||||
sirf,pins = "spi1grp";
|
||||
sirf,function = "spi1";
|
||||
};
|
||||
};
|
||||
i2c0_pins_a: i2c0_0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c0grp";
|
||||
sirf,function = "i2c0";
|
||||
};
|
||||
};
|
||||
i2c1_pins_a: i2c1_0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c1grp";
|
||||
sirf,function = "i2c1";
|
||||
};
|
||||
};
|
||||
pwm0_pins_a: pwm0_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm0grp";
|
||||
sirf,function = "pwm0";
|
||||
};
|
||||
};
|
||||
pwm1_pins_a: pwm1_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm1grp";
|
||||
sirf,function = "pwm1";
|
||||
};
|
||||
};
|
||||
pwm2_pins_a: pwm2_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm2grp";
|
||||
sirf,function = "pwm2";
|
||||
};
|
||||
};
|
||||
pwm3_pins_a: pwm3_0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm3grp";
|
||||
sirf,function = "pwm3";
|
||||
};
|
||||
};
|
||||
gps_pins_a: gps_0 {
|
||||
gps {
|
||||
sirf,pins = "gpsgrp";
|
||||
sirf,function = "gps";
|
||||
};
|
||||
};
|
||||
vip_pins_a: vip_0 {
|
||||
vip {
|
||||
sirf,pins = "vipgrp";
|
||||
sirf,function = "vip";
|
||||
};
|
||||
};
|
||||
sdmmc0_pins_a: sdmmc0_0 {
|
||||
sdmmc0 {
|
||||
sirf,pins = "sdmmc0grp";
|
||||
sirf,function = "sdmmc0";
|
||||
};
|
||||
};
|
||||
sdmmc1_pins_a: sdmmc1_0 {
|
||||
sdmmc1 {
|
||||
sirf,pins = "sdmmc1grp";
|
||||
sirf,function = "sdmmc1";
|
||||
};
|
||||
};
|
||||
sdmmc2_pins_a: sdmmc2_0 {
|
||||
sdmmc2 {
|
||||
sirf,pins = "sdmmc2grp";
|
||||
sirf,function = "sdmmc2";
|
||||
};
|
||||
};
|
||||
sdmmc3_pins_a: sdmmc3_0 {
|
||||
sdmmc3 {
|
||||
sirf,pins = "sdmmc3grp";
|
||||
sirf,function = "sdmmc3";
|
||||
};
|
||||
};
|
||||
sdmmc4_pins_a: sdmmc4_0 {
|
||||
sdmmc4 {
|
||||
sirf,pins = "sdmmc4grp";
|
||||
sirf,function = "sdmmc4";
|
||||
};
|
||||
};
|
||||
sdmmc5_pins_a: sdmmc5_0 {
|
||||
sdmmc5 {
|
||||
sirf,pins = "sdmmc5grp";
|
||||
sirf,function = "sdmmc5";
|
||||
};
|
||||
};
|
||||
i2s_pins_a: i2s_0 {
|
||||
i2s {
|
||||
sirf,pins = "i2sgrp";
|
||||
sirf,function = "i2s";
|
||||
};
|
||||
};
|
||||
ac97_pins_a: ac97_0 {
|
||||
ac97 {
|
||||
sirf,pins = "ac97grp";
|
||||
sirf,function = "ac97";
|
||||
};
|
||||
};
|
||||
nand_pins_a: nand_0 {
|
||||
nand {
|
||||
sirf,pins = "nandgrp";
|
||||
sirf,function = "nand";
|
||||
};
|
||||
};
|
||||
usp0_pins_a: usp0_0 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0grp";
|
||||
sirf,function = "usp0";
|
||||
};
|
||||
};
|
||||
usp1_pins_a: usp1_0 {
|
||||
usp1 {
|
||||
sirf,pins = "usp1grp";
|
||||
sirf,function = "usp1";
|
||||
};
|
||||
};
|
||||
usp2_pins_a: usp2_0 {
|
||||
usp2 {
|
||||
sirf,pins = "usp2grp";
|
||||
sirf,function = "usp2";
|
||||
};
|
||||
};
|
||||
usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
|
||||
usb0_utmi_drvbus {
|
||||
sirf,pins = "usb0_utmi_drvbusgrp";
|
||||
sirf,function = "usb0_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
|
||||
usb1_utmi_drvbus {
|
||||
sirf,pins = "usb1_utmi_drvbusgrp";
|
||||
sirf,function = "usb1_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
warm_rst_pins_a: warm_rst_0 {
|
||||
warm_rst {
|
||||
sirf,pins = "warm_rstgrp";
|
||||
sirf,function = "warm_rst";
|
||||
};
|
||||
};
|
||||
pulse_count_pins_a: pulse_count_0 {
|
||||
pulse_count {
|
||||
sirf,pins = "pulse_countgrp";
|
||||
sirf,function = "pulse_count";
|
||||
};
|
||||
};
|
||||
cko0_rst_pins_a: cko0_rst_0 {
|
||||
cko0_rst {
|
||||
sirf,pins = "cko0_rstgrp";
|
||||
sirf,function = "cko0_rst";
|
||||
};
|
||||
};
|
||||
cko1_rst_pins_a: cko1_rst_0 {
|
||||
cko1_rst {
|
||||
sirf,pins = "cko1_rstgrp";
|
||||
sirf,function = "cko1_rst";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm@cc130000 {
|
||||
compatible = "sirf,marco-pwm";
|
||||
reg = <0xcc130000 0x10000>;
|
||||
};
|
||||
|
||||
efusesys@cc140000 {
|
||||
compatible = "sirf,marco-efuse";
|
||||
reg = <0xcc140000 0x10000>;
|
||||
};
|
||||
|
||||
pulsec@cc150000 {
|
||||
compatible = "sirf,marco-pulsec";
|
||||
reg = <0xcc150000 0x10000>;
|
||||
interrupts = <0 48 0>;
|
||||
};
|
||||
|
||||
pci-iobg {
|
||||
compatible = "sirf,marco-pciiobg", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xcd000000 0xcd000000 0x1000000>;
|
||||
|
||||
sd0: sdhci@cd000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd000000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd1: sdhci@cd100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd100000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd2: sdhci@cd200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd200000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd3: sdhci@cd300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd300000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd4: sdhci@cd400000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd400000 0x100000>;
|
||||
interrupts = <0 39 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd5: sdhci@cd500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,marco-sdhc";
|
||||
reg = <0xcd500000 0x100000>;
|
||||
interrupts = <0 39 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci-copy@cd900000 {
|
||||
compatible = "sirf,marco-pcicp";
|
||||
reg = <0xcd900000 0x100000>;
|
||||
interrupts = <0 40 0>;
|
||||
};
|
||||
|
||||
rom-interface@cda00000 {
|
||||
compatible = "sirf,marco-romif";
|
||||
reg = <0xcda00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc-iobg {
|
||||
compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xc1000000 0x10000>;
|
||||
|
||||
gpsrtc@1000 {
|
||||
compatible = "sirf,marco-gpsrtc";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <0 55 0>,
|
||||
<0 56 0>,
|
||||
<0 57 0>;
|
||||
};
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,marco-sysrtc";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <0 52 0>,
|
||||
<0 53 0>,
|
||||
<0 54 0>;
|
||||
};
|
||||
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,marco-pwrc";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <0 32 0>;
|
||||
};
|
||||
};
|
||||
|
||||
uus-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xce000000 0xce000000 0x1000000>;
|
||||
|
||||
usb0: usb@ce000000 {
|
||||
compatible = "chipidea,ci13611a-marco";
|
||||
reg = <0xce000000 0x10000>;
|
||||
interrupts = <0 10 0>;
|
||||
};
|
||||
|
||||
usb1: usb@ce010000 {
|
||||
compatible = "chipidea,ci13611a-marco";
|
||||
reg = <0xce010000 0x10000>;
|
||||
interrupts = <0 11 0>;
|
||||
};
|
||||
|
||||
security@ce020000 {
|
||||
compatible = "sirf,marco-security";
|
||||
reg = <0xce020000 0x10000>;
|
||||
interrupts = <0 42 0>;
|
||||
};
|
||||
};
|
||||
|
||||
can-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xd0000000 0xd0000000 0x1000000>;
|
||||
|
||||
can0: can@d0000000 {
|
||||
compatible = "sirf,marco-can";
|
||||
reg = <0xd0000000 0x10000>;
|
||||
};
|
||||
|
||||
can1: can@d0010000 {
|
||||
compatible = "sirf,marco-can";
|
||||
reg = <0xd0010000 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
lvds-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xd1000000 0xd1000000 0x1000000>;
|
||||
|
||||
lvds@d1000000 {
|
||||
compatible = "sirf,marco-lvds";
|
||||
reg = <0xd1000000 0x10000>;
|
||||
interrupts = <0 64 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue