drm/nv50/gr: add more trap names to print on error
Also avoids printing the errors bitfield if that information has already been shown. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>hifive-unleashed-5.1
Ilia Mirkin
Ben Skeggs
parent
f87cd8b695
commit
e2dd003dfa
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@ -396,6 +396,60 @@ static const struct nouveau_bitfield nv50_graph_intr_name[] = {
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{}
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};
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static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
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{ 0x00000004, "SURF_WIDTH_OVERRUN" },
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{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
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{ 0x00000010, "DST2D_FAULT" },
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{ 0x00000020, "ZETA_FAULT" },
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{ 0x00000040, "RT_FAULT" },
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{ 0x00000080, "CUDA_FAULT" },
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{ 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
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{ 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
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{ 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
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{ 0x00000800, "DST2D_LINEAR_MISMATCH" },
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{ 0x00001000, "RT_LINEAR_MISMATCH" },
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{}
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};
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static void
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nv50_priv_prop_trap(struct nv50_graph_priv *priv,
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u32 ustatus_addr, u32 ustatus, u32 tp)
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{
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u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
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u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
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u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
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u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
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u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
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u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
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u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
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/* CUDA memory: l[], g[] or stack. */
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if (ustatus & 0x00000080) {
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if (e18 & 0x80000000) {
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/* g[] read fault? */
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nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
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tp, e14, e10 | ((e18 >> 24) & 0x1f));
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e18 &= ~0x1f000000;
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} else if (e18 & 0xc) {
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/* g[] write fault? */
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nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
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tp, e14, e10 | ((e18 >> 7) & 0x1f));
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e18 &= ~0x00000f80;
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} else {
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nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
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tp, e14, e10);
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}
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ustatus &= ~0x00000080;
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}
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if (ustatus) {
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nv_error(priv, "TRAP_PROP - TP %d -", tp);
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nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
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pr_cont(" - Address %02x%08x\n", e14, e10);
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}
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nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
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tp, e0c, e18, e1c, e20, e24);
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}
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static void
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nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
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{
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@ -469,58 +523,11 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
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ustatus &= ~0x04030000;
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}
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break;
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case 8: /* TPDMA error */
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{
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u32 e0c = nv_rd32(priv, ustatus_addr + 4);
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u32 e10 = nv_rd32(priv, ustatus_addr + 8);
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u32 e14 = nv_rd32(priv, ustatus_addr + 0xc);
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u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
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u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
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u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
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u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
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/* 2d engine destination */
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if (ustatus & 0x00000010) {
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if (display) {
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nv_error(priv, "TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
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i, e14, e10);
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nv_error(priv, "TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
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i, e0c, e18, e1c, e20, e24);
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}
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ustatus &= ~0x00000010;
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}
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/* Render target */
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if (ustatus & 0x00000040) {
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if (display) {
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nv_error(priv, "TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
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i, e14, e10);
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nv_error(priv, "TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
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i, e0c, e18, e1c, e20, e24);
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}
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ustatus &= ~0x00000040;
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}
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/* CUDA memory: l[], g[] or stack. */
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if (ustatus & 0x00000080) {
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if (display) {
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if (e18 & 0x80000000) {
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/* g[] read fault? */
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nv_error(priv, "TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
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i, e14, e10 | ((e18 >> 24) & 0x1f));
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e18 &= ~0x1f000000;
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} else if (e18 & 0xc) {
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/* g[] write fault? */
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nv_error(priv, "TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
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i, e14, e10 | ((e18 >> 7) & 0x1f));
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e18 &= ~0x00000f80;
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} else {
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nv_error(priv, "TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
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i, e14, e10);
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}
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nv_error(priv, "TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
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i, e0c, e18, e1c, e20, e24);
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}
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ustatus &= ~0x00000080;
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}
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}
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case 8: /* PROP error */
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if (display)
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nv50_priv_prop_trap(
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priv, ustatus_addr, ustatus, i);
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ustatus = 0;
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break;
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}
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if (ustatus) {
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@ -727,11 +734,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
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status &= ~0x080;
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}
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/* TPDMA: Handles TP-initiated uncached memory accesses:
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/* PROP: Handles TP-initiated uncached memory accesses:
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* l[], g[], stack, 2d surfaces, render targets. */
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if (status & 0x100) {
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nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
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"TRAP_TPDMA");
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"TRAP_PROP");
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nv_wr32(priv, 0x400108, 0x100);
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status &= ~0x100;
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}
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@ -760,7 +767,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
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u32 mthd = (addr & 0x00001ffc);
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u32 data = nv_rd32(priv, 0x400708);
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u32 class = nv_rd32(priv, 0x400814);
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u32 show = stat;
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u32 show = stat, show_bitfield = stat;
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int chid;
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engctx = nouveau_engctx_get(engine, inst);
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@ -778,21 +785,26 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
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nv_error(priv, "DATA_ERROR ");
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nouveau_enum_print(nv50_data_error_names, ecode);
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pr_cont("\n");
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show_bitfield &= ~0x00100000;
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}
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if (stat & 0x00200000) {
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if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
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engctx))
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show &= ~0x00200000;
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show_bitfield &= ~0x00200000;
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}
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nv_wr32(priv, 0x400100, stat);
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nv_wr32(priv, 0x400500, 0x00010001);
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if (show) {
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nv_error(priv, "%s", "");
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nouveau_bitfield_print(nv50_graph_intr_name, show);
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pr_cont("\n");
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show &= show_bitfield;
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if (show) {
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nv_error(priv, "%s", "");
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nouveau_bitfield_print(nv50_graph_intr_name, show);
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pr_cont("\n");
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}
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nv_error(priv,
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"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
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chid, (u64)inst << 12, nouveau_client_name(engctx),
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