mfd: fsl-imx25-tsadc: Register touchscreen ADC driver
This is the core driver for imx25 touchscreen/adc driver. The module has one shared ADC and two different conversion queues which use the ADC. The two queues are identical. Both can be used for general purpose ADC but one is meant to be used for touchscreens. This driver is the core which manages the central components and registers of the TSC/ADC unit. It manages the IRQs and forwards them to the correct components. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Denis Carikli <denis@eukrea.com> [ensure correct ADC clock depending on the IPG clock] Signed-off-by: Juergen Borleis <jbe@pengutronix.de> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>hifive-unleashed-5.1
Markus Pargmann
Lee Jones
parent
ff07004f4b
commit
e2fccf5c15
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@ -271,6 +271,15 @@ config MFD_MC13XXX_I2C
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help
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Select this if your MC13xxx is connected via an I2C bus.
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config MFD_MX25_TSADC
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tristate "Freescale i.MX25 integrated Touchscreen and ADC unit"
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select REGMAP_MMIO
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depends on (SOC_IMX25 && OF) || COMPILE_TEST
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help
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Enable support for the integrated Touchscreen and ADC unit of the
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i.MX25 processors. They consist of a conversion queue for general
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purpose ADC and a queue for Touchscreens.
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config MFD_HI6421_PMIC
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tristate "HiSilicon Hi6421 PMU/Codec IC"
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depends on OF
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@ -85,6 +85,8 @@ obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o
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obj-$(CONFIG_MFD_TWL4030_AUDIO) += twl4030-audio.o
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obj-$(CONFIG_TWL6040_CORE) += twl6040.o
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obj-$(CONFIG_MFD_MX25_TSADC) += fsl-imx25-tsadc.o
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obj-$(CONFIG_MFD_MC13XXX) += mc13xxx-core.o
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obj-$(CONFIG_MFD_MC13XXX_SPI) += mc13xxx-spi.o
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obj-$(CONFIG_MFD_MC13XXX_I2C) += mc13xxx-i2c.o
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@ -0,0 +1,203 @@
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/*
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* Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdesc.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/mfd/imx25-tsadc.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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static struct regmap_config mx25_tsadc_regmap_config = {
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.fast_io = true,
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.max_register = 8,
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static void mx25_tsadc_irq_handler(struct irq_desc *desc)
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{
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struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 status;
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chained_irq_enter(chip, desc);
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regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);
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if (status & MX25_TGSR_GCQ_INT)
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generic_handle_irq(irq_find_mapping(tsadc->domain, 1));
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if (status & MX25_TGSR_TCQ_INT)
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generic_handle_irq(irq_find_mapping(tsadc->domain, 0));
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chained_irq_exit(chip, desc);
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}
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static int mx25_tsadc_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct mx25_tsadc *tsadc = d->host_data;
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irq_set_chip_data(irq, tsadc);
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irq_set_chip_and_handler(irq, &dummy_irq_chip,
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handle_level_irq);
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irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
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return 0;
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}
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static struct irq_domain_ops mx25_tsadc_domain_ops = {
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.map = mx25_tsadc_domain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int mx25_tsadc_setup_irq(struct platform_device *pdev,
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struct mx25_tsadc *tsadc)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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int irq;
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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dev_err(dev, "Failed to get irq\n");
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return irq;
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}
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tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops,
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tsadc);
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if (!tsadc->domain) {
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dev_err(dev, "Failed to add irq domain\n");
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return -ENOMEM;
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}
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irq_set_chained_handler(irq, mx25_tsadc_irq_handler);
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irq_set_handler_data(irq, tsadc);
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return 0;
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}
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static void mx25_tsadc_setup_clk(struct platform_device *pdev,
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struct mx25_tsadc *tsadc)
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{
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unsigned clk_div;
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/*
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* According to the datasheet the ADC clock should never
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* exceed 1,75 MHz. Base clock is the IPG and the ADC unit uses
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* a funny clock divider. To keep the ADC conversion time constant
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* adapt the ADC internal clock divider to the IPG clock rate.
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*/
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dev_dbg(&pdev->dev, "Found master clock at %lu Hz\n",
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clk_get_rate(tsadc->clk));
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clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000);
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dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div);
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/* adc clock = IPG clock / (2 * div + 2) */
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clk_div -= 2;
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clk_div /= 2;
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/*
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* the ADC clock divider changes its behaviour when values below 4
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* are used: it is fixed to "/ 10" in this case
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*/
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clk_div = max_t(unsigned, 4, clk_div);
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dev_dbg(&pdev->dev, "Resulting ADC conversion clock at %lu Hz\n",
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clk_get_rate(tsadc->clk) / (2 * clk_div + 2));
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regmap_update_bits(tsadc->regs, MX25_TSC_TGCR,
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MX25_TGCR_ADCCLKCFG(0x1f),
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MX25_TGCR_ADCCLKCFG(clk_div));
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}
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static int mx25_tsadc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct mx25_tsadc *tsadc;
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struct resource *res;
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int ret;
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void __iomem *iomem;
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tsadc = devm_kzalloc(dev, sizeof(*tsadc), GFP_KERNEL);
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if (!tsadc)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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iomem = devm_ioremap_resource(dev, res);
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if (IS_ERR(iomem))
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return PTR_ERR(iomem);
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tsadc->regs = devm_regmap_init_mmio(dev, iomem,
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&mx25_tsadc_regmap_config);
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if (IS_ERR(tsadc->regs)) {
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dev_err(dev, "Failed to initialize regmap\n");
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return PTR_ERR(tsadc->regs);
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}
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tsadc->clk = devm_clk_get(dev, "ipg");
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if (IS_ERR(tsadc->clk)) {
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dev_err(dev, "Failed to get ipg clock\n");
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return PTR_ERR(tsadc->clk);
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}
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/* setup clock according to the datasheet */
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mx25_tsadc_setup_clk(pdev, tsadc);
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/* Enable clock and reset the component */
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regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_CLK_EN,
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MX25_TGCR_CLK_EN);
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regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_TSC_RST,
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MX25_TGCR_TSC_RST);
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/* Setup powersaving mode, but enable internal reference voltage */
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regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_POWERMODE_MASK,
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MX25_TGCR_POWERMODE_SAVE);
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regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_INTREFEN,
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MX25_TGCR_INTREFEN);
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ret = mx25_tsadc_setup_irq(pdev, tsadc);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, tsadc);
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of_platform_populate(np, NULL, NULL, dev);
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return 0;
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}
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static const struct of_device_id mx25_tsadc_ids[] = {
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{ .compatible = "fsl,imx25-tsadc" },
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{ /* Sentinel */ }
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};
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static struct platform_driver mx25_tsadc_driver = {
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.driver = {
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.name = "mx25-tsadc",
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.of_match_table = of_match_ptr(mx25_tsadc_ids),
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},
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.probe = mx25_tsadc_probe,
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};
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module_platform_driver(mx25_tsadc_driver);
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MODULE_DESCRIPTION("MFD for ADC/TSC for Freescale mx25");
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MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:mx25-tsadc");
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@ -0,0 +1,140 @@
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#ifndef _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
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#define _LINUX_INCLUDE_MFD_IMX25_TSADC_H_
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struct regmap;
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struct clk;
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struct mx25_tsadc {
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struct regmap *regs;
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struct irq_domain *domain;
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struct clk *clk;
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};
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#define MX25_TSC_TGCR 0x00
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#define MX25_TSC_TGSR 0x04
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#define MX25_TSC_TICR 0x08
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/* The same register layout for TC and GC queue */
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#define MX25_ADCQ_FIFO 0x00
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#define MX25_ADCQ_CR 0x04
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#define MX25_ADCQ_SR 0x08
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#define MX25_ADCQ_MR 0x0c
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#define MX25_ADCQ_ITEM_7_0 0x20
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#define MX25_ADCQ_ITEM_15_8 0x24
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#define MX25_ADCQ_CFG(n) (0x40 + ((n) * 0x4))
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#define MX25_ADCQ_MR_MASK 0xffffffff
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/* TGCR */
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#define MX25_TGCR_PDBTIME(x) ((x) << 25)
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#define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25)
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#define MX25_TGCR_PDBEN BIT(24)
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#define MX25_TGCR_PDEN BIT(23)
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#define MX25_TGCR_ADCCLKCFG(x) ((x) << 16)
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#define MX25_TGCR_GET_ADCCLK(x) (((x) >> 16) & 0x1f)
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#define MX25_TGCR_INTREFEN BIT(10)
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#define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8)
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#define MX25_TGCR_POWERMODE_SAVE (1 << 8)
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#define MX25_TGCR_POWERMODE_ON (2 << 8)
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#define MX25_TGCR_STLC BIT(5)
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#define MX25_TGCR_SLPC BIT(4)
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#define MX25_TGCR_FUNC_RST BIT(2)
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#define MX25_TGCR_TSC_RST BIT(1)
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#define MX25_TGCR_CLK_EN BIT(0)
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/* TGSR */
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#define MX25_TGSR_SLP_INT BIT(2)
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#define MX25_TGSR_GCQ_INT BIT(1)
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#define MX25_TGSR_TCQ_INT BIT(0)
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/* ADCQ_ITEM_* */
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#define _MX25_ADCQ_ITEM(item, x) ((x) << ((item) * 4))
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#define MX25_ADCQ_ITEM(item, x) ((item) >= 8 ? \
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_MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x)))
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/* ADCQ_FIFO (TCQFIFO and GCQFIFO) */
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#define MX25_ADCQ_FIFO_DATA(x) (((x) >> 4) & 0xfff)
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#define MX25_ADCQ_FIFO_ID(x) ((x) & 0xf)
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/* ADCQ_CR (TCQR and GCQR) */
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#define MX25_ADCQ_CR_PDCFG_LEVEL BIT(19)
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#define MX25_ADCQ_CR_PDMSK BIT(18)
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#define MX25_ADCQ_CR_FRST BIT(17)
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#define MX25_ADCQ_CR_QRST BIT(16)
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#define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12)
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#define MX25_ADCQ_CR_RWAIT(x) ((x) << 12)
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#define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8)
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#define MX25_ADCQ_CR_WMRK(x) ((x) << 8)
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#define MX25_ADCQ_CR_LITEMID_MASK (0xf << 4)
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#define MX25_ADCQ_CR_LITEMID(x) ((x) << 4)
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#define MX25_ADCQ_CR_RPT BIT(3)
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#define MX25_ADCQ_CR_FQS BIT(2)
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#define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0)
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#define MX25_ADCQ_CR_QSM_PD 0x1
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#define MX25_ADCQ_CR_QSM_FQS 0x2
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#define MX25_ADCQ_CR_QSM_FQS_PD 0x3
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/* ADCQ_SR (TCQSR and GCQSR) */
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#define MX25_ADCQ_SR_FDRY BIT(15)
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#define MX25_ADCQ_SR_FULL BIT(14)
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#define MX25_ADCQ_SR_EMPT BIT(13)
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#define MX25_ADCQ_SR_FDN(x) (((x) >> 8) & 0x1f)
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#define MX25_ADCQ_SR_FRR BIT(6)
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#define MX25_ADCQ_SR_FUR BIT(5)
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#define MX25_ADCQ_SR_FOR BIT(4)
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#define MX25_ADCQ_SR_EOQ BIT(1)
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#define MX25_ADCQ_SR_PD BIT(0)
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/* ADCQ_MR (TCQMR and GCQMR) */
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#define MX25_ADCQ_MR_FDRY_DMA BIT(31)
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#define MX25_ADCQ_MR_FER_DMA BIT(22)
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#define MX25_ADCQ_MR_FUR_DMA BIT(21)
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#define MX25_ADCQ_MR_FOR_DMA BIT(20)
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#define MX25_ADCQ_MR_EOQ_DMA BIT(17)
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#define MX25_ADCQ_MR_PD_DMA BIT(16)
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#define MX25_ADCQ_MR_FDRY_IRQ BIT(15)
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#define MX25_ADCQ_MR_FER_IRQ BIT(6)
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#define MX25_ADCQ_MR_FUR_IRQ BIT(5)
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#define MX25_ADCQ_MR_FOR_IRQ BIT(4)
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#define MX25_ADCQ_MR_EOQ_IRQ BIT(1)
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#define MX25_ADCQ_MR_PD_IRQ BIT(0)
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/* ADCQ_CFG (TICR, TCC0-7,GCC0-7) */
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#define MX25_ADCQ_CFG_SETTLING_TIME(x) ((x) << 24)
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#define MX25_ADCQ_CFG_IGS (1 << 20)
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#define MX25_ADCQ_CFG_NOS_MASK GENMASK(19, 16)
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#define MX25_ADCQ_CFG_NOS(x) (((x) - 1) << 16)
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#define MX25_ADCQ_CFG_WIPER (1 << 15)
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#define MX25_ADCQ_CFG_YNLR (1 << 14)
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#define MX25_ADCQ_CFG_YPLL_HIGH (0 << 12)
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#define MX25_ADCQ_CFG_YPLL_OFF (1 << 12)
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#define MX25_ADCQ_CFG_YPLL_LOW (3 << 12)
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#define MX25_ADCQ_CFG_XNUR_HIGH (0 << 10)
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#define MX25_ADCQ_CFG_XNUR_OFF (1 << 10)
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#define MX25_ADCQ_CFG_XNUR_LOW (3 << 10)
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#define MX25_ADCQ_CFG_XPUL_HIGH (0 << 9)
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#define MX25_ADCQ_CFG_XPUL_OFF (1 << 9)
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#define MX25_ADCQ_CFG_REFP(sel) ((sel) << 7)
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#define MX25_ADCQ_CFG_REFP_YP MX25_ADCQ_CFG_REFP(0)
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#define MX25_ADCQ_CFG_REFP_XP MX25_ADCQ_CFG_REFP(1)
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#define MX25_ADCQ_CFG_REFP_EXT MX25_ADCQ_CFG_REFP(2)
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#define MX25_ADCQ_CFG_REFP_INT MX25_ADCQ_CFG_REFP(3)
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#define MX25_ADCQ_CFG_REFP_MASK GENMASK(8, 7)
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#define MX25_ADCQ_CFG_IN(sel) ((sel) << 4)
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#define MX25_ADCQ_CFG_IN_XP MX25_ADCQ_CFG_IN(0)
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#define MX25_ADCQ_CFG_IN_YP MX25_ADCQ_CFG_IN(1)
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#define MX25_ADCQ_CFG_IN_XN MX25_ADCQ_CFG_IN(2)
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#define MX25_ADCQ_CFG_IN_YN MX25_ADCQ_CFG_IN(3)
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#define MX25_ADCQ_CFG_IN_WIPER MX25_ADCQ_CFG_IN(4)
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#define MX25_ADCQ_CFG_IN_AUX0 MX25_ADCQ_CFG_IN(5)
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#define MX25_ADCQ_CFG_IN_AUX1 MX25_ADCQ_CFG_IN(6)
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#define MX25_ADCQ_CFG_IN_AUX2 MX25_ADCQ_CFG_IN(7)
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#define MX25_ADCQ_CFG_REFN(sel) ((sel) << 2)
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#define MX25_ADCQ_CFG_REFN_XN MX25_ADCQ_CFG_REFN(0)
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#define MX25_ADCQ_CFG_REFN_YN MX25_ADCQ_CFG_REFN(1)
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#define MX25_ADCQ_CFG_REFN_NGND MX25_ADCQ_CFG_REFN(2)
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#define MX25_ADCQ_CFG_REFN_NGND2 MX25_ADCQ_CFG_REFN(3)
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#define MX25_ADCQ_CFG_REFN_MASK GENMASK(3, 2)
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#define MX25_ADCQ_CFG_PENIACK (1 << 1)
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#endif /* _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ */
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