i.MX drivers change for 4.21:
- A series from Aisheng that improves SCU power domain bindings by
defining '#power-domain-cells' as 1, and adds i.MX8 SCU power domain
driver support on top of it.
- A series from Lucas that updates gpcv2 driver for scalability and
adds i.MX8MQ support into the driver.
- Increase gpc driver GPC_CLK_MAX definition to 7, as DISPLAY power
domain on imx6sx has 7 clocks.
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Merge tag 'imx-drivers-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
i.MX drivers change for 4.21:
- A series from Aisheng that improves SCU power domain bindings by
defining '#power-domain-cells' as 1, and adds i.MX8 SCU power domain
driver support on top of it.
- A series from Lucas that updates gpcv2 driver for scalability and
adds i.MX8MQ support into the driver.
- Increase gpc driver GPC_CLK_MAX definition to 7, as DISPLAY power
domain on imx6sx has 7 clocks.
* tag 'imx-drivers-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpc: Increase GPC_CLK_MAX to 7
soc: imx: gpcv2: add support for i.MX8MQ SoC
soc: imx: gpcv2: move register access table to domain data
soc: imx: gpcv2: prefix i.MX7 specific defines
firmware: imx: add SCU power domain driver
firmware: imx: add pm svc headfile
dt-bindings: fsl: scu: update power domain binding
firmware: imx: remove resource id enums
dt-bindings: imx: add scu resource id headfile
Signed-off-by: Olof Johansson <olof@lixom.net>
hifive-unleashed-5.1
Olof Johansson
commit
e3154317a0
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|
@ -58,19 +58,11 @@ This binding for the SCU power domain providers uses the generic power
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domain binding[2].
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Required properties:
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- compatible: Should be "fsl,scu-pd".
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- #address-cells: Should be 1.
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- #size-cells: Should be 0.
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Required properties for power domain sub nodes:
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- #power-domain-cells: Must be 0.
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Optional Properties:
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- reg: Resource ID of this power domain.
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No exist means uncontrollable by user.
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- compatible: Should be "fsl,imx8qxp-scu-pd".
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- #power-domain-cells: Must be 1. Contains the Resource ID used by
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SCU commands.
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See detailed Resource ID list from:
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include/dt-bindings/power/imx-rsrc.h
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- power-domains: phandle pointing to the parent power domain.
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include/dt-bindings/firmware/imx/rsrc.h
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Clock bindings based on SCU Message Protocol
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------------------------------------------------------------
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@ -152,22 +144,9 @@ firmware {
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...
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};
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imx8qx-pm {
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compatible = "fsl,scu-pd";
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#address-cells = <1>;
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#size-cells = <0>;
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pd_dma: dma-power-domain {
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#power-domain-cells = <0>;
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pd_dma_lpuart0: dma-lpuart0@57 {
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reg = <SC_R_UART_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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...
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};
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...
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pd: imx8qx-pd {
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compatible = "fsl,imx8qxp-scu-pd";
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#power-domain-cells = <1>;
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};
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};
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};
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@ -179,5 +158,5 @@ serial@5a060000 {
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clocks = <&clk IMX8QXP_UART0_CLK>,
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<&clk IMX8QXP_UART0_IPG_CLK>;
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clock-names = "per", "ipg";
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power-domains = <&pd_dma_lpuart0>;
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power-domains = <&pd IMX_SC_R_UART_0>;
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};
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@ -6,7 +6,9 @@ Control (PGC) for various power domains.
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Required properties:
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- compatible: Should be "fsl,imx7d-gpc"
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- compatible: Should be one of:
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- "fsl,imx7d-gpc"
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- "fsl,imx8mq-gpc"
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- reg: should be register base and length as documented in the
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datasheet
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@ -22,7 +24,8 @@ which, in turn, is expected to contain the following:
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Required properties:
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- reg: Power domain index. Valid values are defined in
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include/dt-bindings/power/imx7-power.h
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include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
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include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
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- #power-domain-cells: Should be 0
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@ -9,3 +9,9 @@ config IMX_SCU
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This driver manages the IPC interface between host CPU and the
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SCU firmware running on M4.
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config IMX_SCU_PD
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bool "IMX SCU Power Domain driver"
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depends on IMX_SCU
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help
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The System Controller Firmware (SCFW) based power domain driver.
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o
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obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o
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obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o
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@ -0,0 +1,339 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*
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* Implementation of the SCU based Power Domains
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*
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* NOTE: a better implementation suggested by Ulf Hansson is using a
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* single global power domain and implement the ->attach|detach_dev()
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* callback for the genpd and use the regular of_genpd_add_provider_simple().
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* From within the ->attach_dev(), we could get the OF node for
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* the device that is being attached and then parse the power-domain
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* cell containing the "resource id" and store that in the per device
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* struct generic_pm_domain_data (we have void pointer there for
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* storing these kind of things).
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*
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* Additionally, we need to implement the ->stop() and ->start()
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* callbacks of genpd, which is where you "power on/off" devices,
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* rather than using the above ->power_on|off() callbacks.
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*
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* However, there're two known issues:
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* 1. The ->attach_dev() of power domain infrastructure still does
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* not support multi domains case as the struct device *dev passed
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* in is a virtual PD device, it does not help for parsing the real
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* device resource id from device tree, so it's unware of which
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* real sub power domain of device should be attached.
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*
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* The framework needs some proper extension to support multi power
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* domain cases.
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*
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* 2. It also breaks most of current drivers as the driver probe sequence
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* behavior changed if removing ->power_on|off() callback and use
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* ->start() and ->stop() instead. genpd_dev_pm_attach will only power
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* up the domain and attach device, but will not call .start() which
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* relies on device runtime pm. That means the device power is still
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* not up before running driver probe function. For SCU enabled
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* platforms, all device drivers accessing registers/clock without power
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* domain enabled will trigger a HW access error. That means we need fix
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* most drivers probe sequence with proper runtime pm.
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*
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* In summary, we need fix above two issue before being able to switch to
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* the "single global power domain" way.
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*
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <linux/firmware/imx/sci.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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/* SCU Power Mode Protocol definition */
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struct imx_sc_msg_req_set_resource_power_mode {
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struct imx_sc_rpc_msg hdr;
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u16 resource;
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u8 mode;
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} __packed;
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#define IMX_SCU_PD_NAME_SIZE 20
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struct imx_sc_pm_domain {
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struct generic_pm_domain pd;
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char name[IMX_SCU_PD_NAME_SIZE];
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u32 rsrc;
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};
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struct imx_sc_pd_range {
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char *name;
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u32 rsrc;
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u8 num;
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bool postfix;
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};
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struct imx_sc_pd_soc {
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const struct imx_sc_pd_range *pd_ranges;
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u8 num_ranges;
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};
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static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
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/* LSIO SS */
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{ "lsio-pwm", IMX_SC_R_PWM_0, 8, 1 },
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{ "lsio-gpio", IMX_SC_R_GPIO_0, 8, 1 },
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{ "lsio-gpt", IMX_SC_R_GPT_0, 5, 1 },
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{ "lsio-kpp", IMX_SC_R_KPP, 1, 0 },
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{ "lsio-fspi", IMX_SC_R_FSPI_0, 2, 1 },
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{ "lsio-mu", IMX_SC_R_MU_0A, 14, 1 },
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/* CONN SS */
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{ "con-usb", IMX_SC_R_USB_0, 2, 1 },
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{ "con-usb0phy", IMX_SC_R_USB_0_PHY, 1, 0 },
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{ "con-usb2", IMX_SC_R_USB_2, 1, 0 },
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{ "con-usb2phy", IMX_SC_R_USB_2_PHY, 1, 0 },
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{ "con-sdhc", IMX_SC_R_SDHC_0, 3, 1 },
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{ "con-enet", IMX_SC_R_ENET_0, 2, 1 },
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{ "con-nand", IMX_SC_R_NAND, 1, 0 },
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{ "con-mlb", IMX_SC_R_MLB_0, 1, 1 },
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/* Audio DMA SS */
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{ "adma-audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, 0 },
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{ "adma-audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, 0 },
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{ "adma-audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, 0 },
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{ "adma-dma0-ch", IMX_SC_R_DMA_0_CH0, 16, 1 },
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{ "adma-dma1-ch", IMX_SC_R_DMA_1_CH0, 16, 1 },
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{ "adma-dma2-ch", IMX_SC_R_DMA_2_CH0, 5, 1 },
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{ "adma-asrc0", IMX_SC_R_ASRC_0, 1, 0 },
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{ "adma-asrc1", IMX_SC_R_ASRC_1, 1, 0 },
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{ "adma-esai0", IMX_SC_R_ESAI_0, 1, 0 },
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{ "adma-spdif0", IMX_SC_R_SPDIF_0, 1, 0 },
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{ "adma-sai", IMX_SC_R_SAI_0, 3, 1 },
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{ "adma-amix", IMX_SC_R_AMIX, 1, 0 },
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{ "adma-mqs0", IMX_SC_R_MQS_0, 1, 0 },
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{ "adma-dsp", IMX_SC_R_DSP, 1, 0 },
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{ "adma-dsp-ram", IMX_SC_R_DSP_RAM, 1, 0 },
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{ "adma-can", IMX_SC_R_CAN_0, 3, 1 },
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{ "adma-ftm", IMX_SC_R_FTM_0, 2, 1 },
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{ "adma-lpi2c", IMX_SC_R_I2C_0, 4, 1 },
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{ "adma-adc", IMX_SC_R_ADC_0, 1, 1 },
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{ "adma-lcd", IMX_SC_R_LCD_0, 1, 1 },
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{ "adma-lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, 1 },
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{ "adma-lpuart", IMX_SC_R_UART_0, 4, 1 },
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{ "adma-lpspi", IMX_SC_R_SPI_0, 4, 1 },
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/* VPU SS */
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{ "vpu", IMX_SC_R_VPU, 1, 0 },
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{ "vpu-pid", IMX_SC_R_VPU_PID0, 8, 1 },
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{ "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, 0 },
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{ "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, 0 },
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/* GPU SS */
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{ "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, 1 },
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/* HSIO SS */
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{ "hsio-pcie-b", IMX_SC_R_PCIE_B, 1, 0 },
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{ "hsio-serdes-1", IMX_SC_R_SERDES_1, 1, 0 },
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{ "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, 0 },
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|
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/* MIPI/LVDS SS */
|
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{ "mipi0", IMX_SC_R_MIPI_0, 1, 0 },
|
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{ "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, 0 },
|
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{ "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, 1 },
|
||||
{ "lvds0", IMX_SC_R_LVDS_0, 1, 0 },
|
||||
|
||||
/* DC SS */
|
||||
{ "dc0", IMX_SC_R_DC_0, 1, 0 },
|
||||
{ "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, 1 },
|
||||
};
|
||||
|
||||
static const struct imx_sc_pd_soc imx8qxp_scu_pd = {
|
||||
.pd_ranges = imx8qxp_scu_pd_ranges,
|
||||
.num_ranges = ARRAY_SIZE(imx8qxp_scu_pd_ranges),
|
||||
};
|
||||
|
||||
static struct imx_sc_ipc *pm_ipc_handle;
|
||||
|
||||
static inline struct imx_sc_pm_domain *
|
||||
to_imx_sc_pd(struct generic_pm_domain *genpd)
|
||||
{
|
||||
return container_of(genpd, struct imx_sc_pm_domain, pd);
|
||||
}
|
||||
|
||||
static int imx_sc_pd_power(struct generic_pm_domain *domain, bool power_on)
|
||||
{
|
||||
struct imx_sc_msg_req_set_resource_power_mode msg;
|
||||
struct imx_sc_rpc_msg *hdr = &msg.hdr;
|
||||
struct imx_sc_pm_domain *pd;
|
||||
int ret;
|
||||
|
||||
pd = to_imx_sc_pd(domain);
|
||||
|
||||
hdr->ver = IMX_SC_RPC_VERSION;
|
||||
hdr->svc = IMX_SC_RPC_SVC_PM;
|
||||
hdr->func = IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE;
|
||||
hdr->size = 2;
|
||||
|
||||
msg.resource = pd->rsrc;
|
||||
msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : IMX_SC_PM_PW_MODE_LP;
|
||||
|
||||
ret = imx_scu_call_rpc(pm_ipc_handle, &msg, true);
|
||||
if (ret)
|
||||
dev_err(&domain->dev, "failed to power %s resource %d ret %d\n",
|
||||
power_on ? "up" : "off", pd->rsrc, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int imx_sc_pd_power_on(struct generic_pm_domain *domain)
|
||||
{
|
||||
return imx_sc_pd_power(domain, true);
|
||||
}
|
||||
|
||||
static int imx_sc_pd_power_off(struct generic_pm_domain *domain)
|
||||
{
|
||||
return imx_sc_pd_power(domain, false);
|
||||
}
|
||||
|
||||
static struct generic_pm_domain *imx_scu_pd_xlate(struct of_phandle_args *spec,
|
||||
void *data)
|
||||
{
|
||||
struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
|
||||
struct genpd_onecell_data *pd_data = data;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < pd_data->num_domains; i++) {
|
||||
struct imx_sc_pm_domain *sc_pd;
|
||||
|
||||
sc_pd = to_imx_sc_pd(pd_data->domains[i]);
|
||||
if (sc_pd->rsrc == spec->args[0]) {
|
||||
domain = &sc_pd->pd;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return domain;
|
||||
}
|
||||
|
||||
static struct imx_sc_pm_domain *
|
||||
imx_scu_add_pm_domain(struct device *dev, int idx,
|
||||
const struct imx_sc_pd_range *pd_ranges)
|
||||
{
|
||||
struct imx_sc_pm_domain *sc_pd;
|
||||
int ret;
|
||||
|
||||
sc_pd = devm_kzalloc(dev, sizeof(*sc_pd), GFP_KERNEL);
|
||||
if (!sc_pd)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
sc_pd->rsrc = pd_ranges->rsrc + idx;
|
||||
sc_pd->pd.power_off = imx_sc_pd_power_off;
|
||||
sc_pd->pd.power_on = imx_sc_pd_power_on;
|
||||
|
||||
if (pd_ranges->postfix)
|
||||
snprintf(sc_pd->name, sizeof(sc_pd->name),
|
||||
"%s%i", pd_ranges->name, idx);
|
||||
else
|
||||
snprintf(sc_pd->name, sizeof(sc_pd->name),
|
||||
"%s", pd_ranges->name);
|
||||
|
||||
sc_pd->pd.name = sc_pd->name;
|
||||
|
||||
if (sc_pd->rsrc >= IMX_SC_R_LAST) {
|
||||
dev_warn(dev, "invalid pd %s rsrc id %d found",
|
||||
sc_pd->name, sc_pd->rsrc);
|
||||
|
||||
devm_kfree(dev, sc_pd);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ret = pm_genpd_init(&sc_pd->pd, NULL, true);
|
||||
if (ret) {
|
||||
dev_warn(dev, "failed to init pd %s rsrc id %d",
|
||||
sc_pd->name, sc_pd->rsrc);
|
||||
devm_kfree(dev, sc_pd);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return sc_pd;
|
||||
}
|
||||
|
||||
static int imx_scu_init_pm_domains(struct device *dev,
|
||||
const struct imx_sc_pd_soc *pd_soc)
|
||||
{
|
||||
const struct imx_sc_pd_range *pd_ranges = pd_soc->pd_ranges;
|
||||
struct generic_pm_domain **domains;
|
||||
struct genpd_onecell_data *pd_data;
|
||||
struct imx_sc_pm_domain *sc_pd;
|
||||
u32 count = 0;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < pd_soc->num_ranges; i++)
|
||||
count += pd_ranges[i].num;
|
||||
|
||||
domains = devm_kcalloc(dev, count, sizeof(*domains), GFP_KERNEL);
|
||||
if (!domains)
|
||||
return -ENOMEM;
|
||||
|
||||
pd_data = devm_kzalloc(dev, sizeof(*pd_data), GFP_KERNEL);
|
||||
if (!pd_data)
|
||||
return -ENOMEM;
|
||||
|
||||
count = 0;
|
||||
for (i = 0; i < pd_soc->num_ranges; i++) {
|
||||
for (j = 0; j < pd_ranges[i].num; j++) {
|
||||
sc_pd = imx_scu_add_pm_domain(dev, j, &pd_ranges[i]);
|
||||
if (IS_ERR_OR_NULL(sc_pd))
|
||||
continue;
|
||||
|
||||
domains[count++] = &sc_pd->pd;
|
||||
dev_dbg(dev, "added power domain %s\n", sc_pd->pd.name);
|
||||
}
|
||||
}
|
||||
|
||||
pd_data->domains = domains;
|
||||
pd_data->num_domains = count;
|
||||
pd_data->xlate = imx_scu_pd_xlate;
|
||||
|
||||
of_genpd_add_provider_onecell(dev->of_node, pd_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imx_sc_pd_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct imx_sc_pd_soc *pd_soc;
|
||||
int ret;
|
||||
|
||||
ret = imx_scu_get_handle(&pm_ipc_handle);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pd_soc = of_device_get_match_data(&pdev->dev);
|
||||
if (!pd_soc)
|
||||
return -ENODEV;
|
||||
|
||||
return imx_scu_init_pm_domains(&pdev->dev, pd_soc);
|
||||
}
|
||||
|
||||
static const struct of_device_id imx_sc_pd_match[] = {
|
||||
{ .compatible = "fsl,imx8qxp-scu-pd", &imx8qxp_scu_pd},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver imx_sc_pd_driver = {
|
||||
.driver = {
|
||||
.name = "imx-scu-pd",
|
||||
.of_match_table = imx_sc_pd_match,
|
||||
},
|
||||
.probe = imx_sc_pd_probe,
|
||||
};
|
||||
builtin_platform_driver(imx_sc_pd_driver);
|
||||
|
||||
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
|
||||
MODULE_DESCRIPTION("IMX SCU Power Domain driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
menu "i.MX SoC drivers"
|
||||
|
||||
config IMX7_PM_DOMAINS
|
||||
bool "i.MX7 PM domains"
|
||||
depends on SOC_IMX7D || (COMPILE_TEST && OF)
|
||||
config IMX_GPCV2_PM_DOMAINS
|
||||
bool "i.MX GPCv2 PM domains"
|
||||
depends on SOC_IMX7D || SOC_IMX8MQ || (COMPILE_TEST && OF)
|
||||
depends on PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
default y if SOC_IMX7D
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
|
||||
obj-$(CONFIG_IMX7_PM_DOMAINS) += gpcv2.o
|
||||
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
#define GPU_VPU_PUP_REQ BIT(1)
|
||||
#define GPU_VPU_PDN_REQ BIT(0)
|
||||
|
||||
#define GPC_CLK_MAX 6
|
||||
#define GPC_CLK_MAX 7
|
||||
|
||||
#define PGC_DOMAIN_FLAG_NO_PD BIT(0)
|
||||
|
||||
|
|
|
|||
|
|
@ -14,23 +14,54 @@
|
|||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <dt-bindings/power/imx7-power.h>
|
||||
#include <dt-bindings/power/imx8mq-power.h>
|
||||
|
||||
#define GPC_LPCR_A_CORE_BSC 0x000
|
||||
|
||||
#define GPC_PGC_CPU_MAPPING 0x0ec
|
||||
#define USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
|
||||
#define USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
|
||||
#define USB_OTG1_PHY_A_CORE_DOMAIN BIT(4)
|
||||
#define PCIE_PHY_A_CORE_DOMAIN BIT(3)
|
||||
#define MIPI_PHY_A_CORE_DOMAIN BIT(2)
|
||||
|
||||
#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
|
||||
#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
|
||||
#define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4)
|
||||
#define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3)
|
||||
#define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2)
|
||||
|
||||
#define IMX8M_PCIE2_A53_DOMAIN BIT(15)
|
||||
#define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14)
|
||||
#define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13)
|
||||
#define IMX8M_DISP_A53_DOMAIN BIT(12)
|
||||
#define IMX8M_HDMI_A53_DOMAIN BIT(11)
|
||||
#define IMX8M_VPU_A53_DOMAIN BIT(10)
|
||||
#define IMX8M_GPU_A53_DOMAIN BIT(9)
|
||||
#define IMX8M_DDR2_A53_DOMAIN BIT(8)
|
||||
#define IMX8M_DDR1_A53_DOMAIN BIT(7)
|
||||
#define IMX8M_OTG2_A53_DOMAIN BIT(5)
|
||||
#define IMX8M_OTG1_A53_DOMAIN BIT(4)
|
||||
#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
|
||||
#define IMX8M_MIPI_A53_DOMAIN BIT(2)
|
||||
|
||||
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
|
||||
#define GPC_PU_PGC_SW_PDN_REQ 0x104
|
||||
#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
|
||||
#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
|
||||
#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
|
||||
#define PCIE_PHY_SW_Pxx_REQ BIT(1)
|
||||
#define MIPI_PHY_SW_Pxx_REQ BIT(0)
|
||||
|
||||
#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
|
||||
#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
|
||||
#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
|
||||
#define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
|
||||
#define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
|
||||
|
||||
#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
|
||||
#define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12)
|
||||
#define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11)
|
||||
#define IMX8M_DISP_SW_Pxx_REQ BIT(10)
|
||||
#define IMX8M_HDMI_SW_Pxx_REQ BIT(9)
|
||||
#define IMX8M_VPU_SW_Pxx_REQ BIT(8)
|
||||
#define IMX8M_GPU_SW_Pxx_REQ BIT(7)
|
||||
#define IMX8M_DDR2_SW_Pxx_REQ BIT(6)
|
||||
#define IMX8M_DDR1_SW_Pxx_REQ BIT(5)
|
||||
#define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
|
||||
#define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
|
||||
#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
|
||||
#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
|
||||
|
||||
#define GPC_M4_PU_PDN_FLG 0x1bc
|
||||
|
||||
|
|
@ -40,9 +71,22 @@
|
|||
* GPC_PGC memory map are incorrect, below offset
|
||||
* values are from design RTL.
|
||||
*/
|
||||
#define PGC_MIPI 16
|
||||
#define PGC_PCIE 17
|
||||
#define PGC_USB_HSIC 20
|
||||
#define IMX7_PGC_MIPI 16
|
||||
#define IMX7_PGC_PCIE 17
|
||||
#define IMX7_PGC_USB_HSIC 20
|
||||
|
||||
#define IMX8M_PGC_MIPI 16
|
||||
#define IMX8M_PGC_PCIE1 17
|
||||
#define IMX8M_PGC_OTG1 18
|
||||
#define IMX8M_PGC_OTG2 19
|
||||
#define IMX8M_PGC_DDR1 21
|
||||
#define IMX8M_PGC_GPU 23
|
||||
#define IMX8M_PGC_VPU 24
|
||||
#define IMX8M_PGC_DISP 26
|
||||
#define IMX8M_PGC_MIPI_CSI1 27
|
||||
#define IMX8M_PGC_MIPI_CSI2 28
|
||||
#define IMX8M_PGC_PCIE2 29
|
||||
|
||||
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
|
||||
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
|
||||
|
||||
|
|
@ -67,6 +111,7 @@ struct imx_pgc_domain {
|
|||
struct imx_pgc_domain_data {
|
||||
const struct imx_pgc_domain *domains;
|
||||
size_t domains_num;
|
||||
const struct regmap_access_table *reg_access_table;
|
||||
};
|
||||
|
||||
static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
|
||||
|
|
@ -166,11 +211,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
|
|||
.name = "mipi-phy",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = MIPI_PHY_SW_Pxx_REQ,
|
||||
.map = MIPI_PHY_A_CORE_DOMAIN,
|
||||
.pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
|
||||
.map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
|
||||
},
|
||||
.voltage = 1000000,
|
||||
.pgc = PGC_MIPI,
|
||||
.pgc = IMX7_PGC_MIPI,
|
||||
},
|
||||
|
||||
[IMX7_POWER_DOMAIN_PCIE_PHY] = {
|
||||
|
|
@ -178,11 +223,11 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
|
|||
.name = "pcie-phy",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = PCIE_PHY_SW_Pxx_REQ,
|
||||
.map = PCIE_PHY_A_CORE_DOMAIN,
|
||||
.pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
|
||||
.map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
|
||||
},
|
||||
.voltage = 1000000,
|
||||
.pgc = PGC_PCIE,
|
||||
.pgc = IMX7_PGC_PCIE,
|
||||
},
|
||||
|
||||
[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
|
||||
|
|
@ -190,17 +235,195 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = {
|
|||
.name = "usb-hsic-phy",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = USB_HSIC_PHY_SW_Pxx_REQ,
|
||||
.map = USB_HSIC_PHY_A_CORE_DOMAIN,
|
||||
.pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
|
||||
.map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
|
||||
},
|
||||
.voltage = 1200000,
|
||||
.pgc = PGC_USB_HSIC,
|
||||
.pgc = IMX7_PGC_USB_HSIC,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct regmap_range imx7_yes_ranges[] = {
|
||||
regmap_reg_range(GPC_LPCR_A_CORE_BSC,
|
||||
GPC_M4_PU_PDN_FLG),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
|
||||
GPC_PGC_SR(IMX7_PGC_MIPI)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
|
||||
GPC_PGC_SR(IMX7_PGC_PCIE)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
|
||||
GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table imx7_access_table = {
|
||||
.yes_ranges = imx7_yes_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
|
||||
};
|
||||
|
||||
static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
|
||||
.domains = imx7_pgc_domains,
|
||||
.domains_num = ARRAY_SIZE(imx7_pgc_domains),
|
||||
.reg_access_table = &imx7_access_table,
|
||||
};
|
||||
|
||||
static const struct imx_pgc_domain imx8m_pgc_domains[] = {
|
||||
[IMX8M_POWER_DOMAIN_MIPI] = {
|
||||
.genpd = {
|
||||
.name = "mipi",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_MIPI_SW_Pxx_REQ,
|
||||
.map = IMX8M_MIPI_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_MIPI,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_PCIE1] = {
|
||||
.genpd = {
|
||||
.name = "pcie1",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_PCIE1_SW_Pxx_REQ,
|
||||
.map = IMX8M_PCIE1_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_PCIE1,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_USB_OTG1] = {
|
||||
.genpd = {
|
||||
.name = "usb-otg1",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_OTG1_SW_Pxx_REQ,
|
||||
.map = IMX8M_OTG1_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_OTG1,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_USB_OTG2] = {
|
||||
.genpd = {
|
||||
.name = "usb-otg2",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_OTG2_SW_Pxx_REQ,
|
||||
.map = IMX8M_OTG2_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_OTG2,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_DDR1] = {
|
||||
.genpd = {
|
||||
.name = "ddr1",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_DDR1_SW_Pxx_REQ,
|
||||
.map = IMX8M_DDR2_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_DDR1,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_GPU] = {
|
||||
.genpd = {
|
||||
.name = "gpu",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_GPU_SW_Pxx_REQ,
|
||||
.map = IMX8M_GPU_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_GPU,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_VPU] = {
|
||||
.genpd = {
|
||||
.name = "vpu",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_VPU_SW_Pxx_REQ,
|
||||
.map = IMX8M_VPU_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_VPU,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_DISP] = {
|
||||
.genpd = {
|
||||
.name = "disp",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_DISP_SW_Pxx_REQ,
|
||||
.map = IMX8M_DISP_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_DISP,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
|
||||
.genpd = {
|
||||
.name = "mipi-csi1",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
|
||||
.map = IMX8M_MIPI_CSI1_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_MIPI_CSI1,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
|
||||
.genpd = {
|
||||
.name = "mipi-csi2",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
|
||||
.map = IMX8M_MIPI_CSI2_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_MIPI_CSI2,
|
||||
},
|
||||
|
||||
[IMX8M_POWER_DOMAIN_PCIE2] = {
|
||||
.genpd = {
|
||||
.name = "pcie2",
|
||||
},
|
||||
.bits = {
|
||||
.pxx = IMX8M_PCIE2_SW_Pxx_REQ,
|
||||
.map = IMX8M_PCIE2_A53_DOMAIN,
|
||||
},
|
||||
.pgc = IMX8M_PGC_PCIE2,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct regmap_range imx8m_yes_ranges[] = {
|
||||
regmap_reg_range(GPC_LPCR_A_CORE_BSC,
|
||||
GPC_M4_PU_PDN_FLG),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
|
||||
GPC_PGC_SR(IMX8M_PGC_MIPI)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
|
||||
GPC_PGC_SR(IMX8M_PGC_PCIE1)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
|
||||
GPC_PGC_SR(IMX8M_PGC_OTG1)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
|
||||
GPC_PGC_SR(IMX8M_PGC_OTG2)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
|
||||
GPC_PGC_SR(IMX8M_PGC_DDR1)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
|
||||
GPC_PGC_SR(IMX8M_PGC_GPU)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
|
||||
GPC_PGC_SR(IMX8M_PGC_VPU)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
|
||||
GPC_PGC_SR(IMX8M_PGC_DISP)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
|
||||
GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
|
||||
GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
|
||||
GPC_PGC_SR(IMX8M_PGC_PCIE2)),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table imx8m_access_table = {
|
||||
.yes_ranges = imx8m_yes_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges),
|
||||
};
|
||||
|
||||
static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
|
||||
.domains = imx8m_pgc_domains,
|
||||
.domains_num = ARRAY_SIZE(imx8m_pgc_domains),
|
||||
.reg_access_table = &imx8m_access_table,
|
||||
};
|
||||
|
||||
static int imx_pgc_domain_probe(struct platform_device *pdev)
|
||||
|
|
@ -217,7 +440,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
|
|||
dev_err(domain->dev, "Failed to get domain's regulator\n");
|
||||
return PTR_ERR(domain->regulator);
|
||||
}
|
||||
} else {
|
||||
} else if (domain->voltage) {
|
||||
regulator_set_voltage(domain->regulator,
|
||||
domain->voltage, domain->voltage);
|
||||
}
|
||||
|
|
@ -265,27 +488,15 @@ builtin_platform_driver(imx_pgc_domain_driver)
|
|||
|
||||
static int imx_gpcv2_probe(struct platform_device *pdev)
|
||||
{
|
||||
static const struct imx_pgc_domain_data *domain_data;
|
||||
static const struct regmap_range yes_ranges[] = {
|
||||
regmap_reg_range(GPC_LPCR_A_CORE_BSC,
|
||||
GPC_M4_PU_PDN_FLG),
|
||||
regmap_reg_range(GPC_PGC_CTRL(PGC_MIPI),
|
||||
GPC_PGC_SR(PGC_MIPI)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(PGC_PCIE),
|
||||
GPC_PGC_SR(PGC_PCIE)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(PGC_USB_HSIC),
|
||||
GPC_PGC_SR(PGC_USB_HSIC)),
|
||||
};
|
||||
static const struct regmap_access_table access_table = {
|
||||
.yes_ranges = yes_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(yes_ranges),
|
||||
};
|
||||
static const struct regmap_config regmap_config = {
|
||||
const struct imx_pgc_domain_data *domain_data =
|
||||
of_device_get_match_data(&pdev->dev);
|
||||
|
||||
struct regmap_config regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.rd_table = &access_table,
|
||||
.wr_table = &access_table,
|
||||
.rd_table = domain_data->reg_access_table,
|
||||
.wr_table = domain_data->reg_access_table,
|
||||
.max_register = SZ_4K,
|
||||
};
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -313,8 +524,6 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
domain_data = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
for_each_child_of_node(pgc_np, np) {
|
||||
struct platform_device *pd_pdev;
|
||||
struct imx_pgc_domain *domain;
|
||||
|
|
@ -372,6 +581,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
|
|||
|
||||
static const struct of_device_id imx_gpcv2_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
|
||||
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,559 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_RSCRC_IMX_H
|
||||
#define __DT_BINDINGS_RSCRC_IMX_H
|
||||
|
||||
/*
|
||||
* These defines are used to indicate a resource. Resources include peripherals
|
||||
* and bus masters (but not memory regions). Note items from list should
|
||||
* never be changed or removed (only added to at the end of the list).
|
||||
*/
|
||||
|
||||
#define IMX_SC_R_A53 0
|
||||
#define IMX_SC_R_A53_0 1
|
||||
#define IMX_SC_R_A53_1 2
|
||||
#define IMX_SC_R_A53_2 3
|
||||
#define IMX_SC_R_A53_3 4
|
||||
#define IMX_SC_R_A72 5
|
||||
#define IMX_SC_R_A72_0 6
|
||||
#define IMX_SC_R_A72_1 7
|
||||
#define IMX_SC_R_A72_2 8
|
||||
#define IMX_SC_R_A72_3 9
|
||||
#define IMX_SC_R_CCI 10
|
||||
#define IMX_SC_R_DB 11
|
||||
#define IMX_SC_R_DRC_0 12
|
||||
#define IMX_SC_R_DRC_1 13
|
||||
#define IMX_SC_R_GIC_SMMU 14
|
||||
#define IMX_SC_R_IRQSTR_M4_0 15
|
||||
#define IMX_SC_R_IRQSTR_M4_1 16
|
||||
#define IMX_SC_R_SMMU 17
|
||||
#define IMX_SC_R_GIC 18
|
||||
#define IMX_SC_R_DC_0_BLIT0 19
|
||||
#define IMX_SC_R_DC_0_BLIT1 20
|
||||
#define IMX_SC_R_DC_0_BLIT2 21
|
||||
#define IMX_SC_R_DC_0_BLIT_OUT 22
|
||||
#define IMX_SC_R_DC_0_CAPTURE0 23
|
||||
#define IMX_SC_R_DC_0_CAPTURE1 24
|
||||
#define IMX_SC_R_DC_0_WARP 25
|
||||
#define IMX_SC_R_DC_0_INTEGRAL0 26
|
||||
#define IMX_SC_R_DC_0_INTEGRAL1 27
|
||||
#define IMX_SC_R_DC_0_VIDEO0 28
|
||||
#define IMX_SC_R_DC_0_VIDEO1 29
|
||||
#define IMX_SC_R_DC_0_FRAC0 30
|
||||
#define IMX_SC_R_DC_0_FRAC1 31
|
||||
#define IMX_SC_R_DC_0 32
|
||||
#define IMX_SC_R_GPU_2_PID0 33
|
||||
#define IMX_SC_R_DC_0_PLL_0 34
|
||||
#define IMX_SC_R_DC_0_PLL_1 35
|
||||
#define IMX_SC_R_DC_1_BLIT0 36
|
||||
#define IMX_SC_R_DC_1_BLIT1 37
|
||||
#define IMX_SC_R_DC_1_BLIT2 38
|
||||
#define IMX_SC_R_DC_1_BLIT_OUT 39
|
||||
#define IMX_SC_R_DC_1_CAPTURE0 40
|
||||
#define IMX_SC_R_DC_1_CAPTURE1 41
|
||||
#define IMX_SC_R_DC_1_WARP 42
|
||||
#define IMX_SC_R_DC_1_INTEGRAL0 43
|
||||
#define IMX_SC_R_DC_1_INTEGRAL1 44
|
||||
#define IMX_SC_R_DC_1_VIDEO0 45
|
||||
#define IMX_SC_R_DC_1_VIDEO1 46
|
||||
#define IMX_SC_R_DC_1_FRAC0 47
|
||||
#define IMX_SC_R_DC_1_FRAC1 48
|
||||
#define IMX_SC_R_DC_1 49
|
||||
#define IMX_SC_R_GPU_3_PID0 50
|
||||
#define IMX_SC_R_DC_1_PLL_0 51
|
||||
#define IMX_SC_R_DC_1_PLL_1 52
|
||||
#define IMX_SC_R_SPI_0 53
|
||||
#define IMX_SC_R_SPI_1 54
|
||||
#define IMX_SC_R_SPI_2 55
|
||||
#define IMX_SC_R_SPI_3 56
|
||||
#define IMX_SC_R_UART_0 57
|
||||
#define IMX_SC_R_UART_1 58
|
||||
#define IMX_SC_R_UART_2 59
|
||||
#define IMX_SC_R_UART_3 60
|
||||
#define IMX_SC_R_UART_4 61
|
||||
#define IMX_SC_R_EMVSIM_0 62
|
||||
#define IMX_SC_R_EMVSIM_1 63
|
||||
#define IMX_SC_R_DMA_0_CH0 64
|
||||
#define IMX_SC_R_DMA_0_CH1 65
|
||||
#define IMX_SC_R_DMA_0_CH2 66
|
||||
#define IMX_SC_R_DMA_0_CH3 67
|
||||
#define IMX_SC_R_DMA_0_CH4 68
|
||||
#define IMX_SC_R_DMA_0_CH5 69
|
||||
#define IMX_SC_R_DMA_0_CH6 70
|
||||
#define IMX_SC_R_DMA_0_CH7 71
|
||||
#define IMX_SC_R_DMA_0_CH8 72
|
||||
#define IMX_SC_R_DMA_0_CH9 73
|
||||
#define IMX_SC_R_DMA_0_CH10 74
|
||||
#define IMX_SC_R_DMA_0_CH11 75
|
||||
#define IMX_SC_R_DMA_0_CH12 76
|
||||
#define IMX_SC_R_DMA_0_CH13 77
|
||||
#define IMX_SC_R_DMA_0_CH14 78
|
||||
#define IMX_SC_R_DMA_0_CH15 79
|
||||
#define IMX_SC_R_DMA_0_CH16 80
|
||||
#define IMX_SC_R_DMA_0_CH17 81
|
||||
#define IMX_SC_R_DMA_0_CH18 82
|
||||
#define IMX_SC_R_DMA_0_CH19 83
|
||||
#define IMX_SC_R_DMA_0_CH20 84
|
||||
#define IMX_SC_R_DMA_0_CH21 85
|
||||
#define IMX_SC_R_DMA_0_CH22 86
|
||||
#define IMX_SC_R_DMA_0_CH23 87
|
||||
#define IMX_SC_R_DMA_0_CH24 88
|
||||
#define IMX_SC_R_DMA_0_CH25 89
|
||||
#define IMX_SC_R_DMA_0_CH26 90
|
||||
#define IMX_SC_R_DMA_0_CH27 91
|
||||
#define IMX_SC_R_DMA_0_CH28 92
|
||||
#define IMX_SC_R_DMA_0_CH29 93
|
||||
#define IMX_SC_R_DMA_0_CH30 94
|
||||
#define IMX_SC_R_DMA_0_CH31 95
|
||||
#define IMX_SC_R_I2C_0 96
|
||||
#define IMX_SC_R_I2C_1 97
|
||||
#define IMX_SC_R_I2C_2 98
|
||||
#define IMX_SC_R_I2C_3 99
|
||||
#define IMX_SC_R_I2C_4 100
|
||||
#define IMX_SC_R_ADC_0 101
|
||||
#define IMX_SC_R_ADC_1 102
|
||||
#define IMX_SC_R_FTM_0 103
|
||||
#define IMX_SC_R_FTM_1 104
|
||||
#define IMX_SC_R_CAN_0 105
|
||||
#define IMX_SC_R_CAN_1 106
|
||||
#define IMX_SC_R_CAN_2 107
|
||||
#define IMX_SC_R_DMA_1_CH0 108
|
||||
#define IMX_SC_R_DMA_1_CH1 109
|
||||
#define IMX_SC_R_DMA_1_CH2 110
|
||||
#define IMX_SC_R_DMA_1_CH3 111
|
||||
#define IMX_SC_R_DMA_1_CH4 112
|
||||
#define IMX_SC_R_DMA_1_CH5 113
|
||||
#define IMX_SC_R_DMA_1_CH6 114
|
||||
#define IMX_SC_R_DMA_1_CH7 115
|
||||
#define IMX_SC_R_DMA_1_CH8 116
|
||||
#define IMX_SC_R_DMA_1_CH9 117
|
||||
#define IMX_SC_R_DMA_1_CH10 118
|
||||
#define IMX_SC_R_DMA_1_CH11 119
|
||||
#define IMX_SC_R_DMA_1_CH12 120
|
||||
#define IMX_SC_R_DMA_1_CH13 121
|
||||
#define IMX_SC_R_DMA_1_CH14 122
|
||||
#define IMX_SC_R_DMA_1_CH15 123
|
||||
#define IMX_SC_R_DMA_1_CH16 124
|
||||
#define IMX_SC_R_DMA_1_CH17 125
|
||||
#define IMX_SC_R_DMA_1_CH18 126
|
||||
#define IMX_SC_R_DMA_1_CH19 127
|
||||
#define IMX_SC_R_DMA_1_CH20 128
|
||||
#define IMX_SC_R_DMA_1_CH21 129
|
||||
#define IMX_SC_R_DMA_1_CH22 130
|
||||
#define IMX_SC_R_DMA_1_CH23 131
|
||||
#define IMX_SC_R_DMA_1_CH24 132
|
||||
#define IMX_SC_R_DMA_1_CH25 133
|
||||
#define IMX_SC_R_DMA_1_CH26 134
|
||||
#define IMX_SC_R_DMA_1_CH27 135
|
||||
#define IMX_SC_R_DMA_1_CH28 136
|
||||
#define IMX_SC_R_DMA_1_CH29 137
|
||||
#define IMX_SC_R_DMA_1_CH30 138
|
||||
#define IMX_SC_R_DMA_1_CH31 139
|
||||
#define IMX_SC_R_UNUSED1 140
|
||||
#define IMX_SC_R_UNUSED2 141
|
||||
#define IMX_SC_R_UNUSED3 142
|
||||
#define IMX_SC_R_UNUSED4 143
|
||||
#define IMX_SC_R_GPU_0_PID0 144
|
||||
#define IMX_SC_R_GPU_0_PID1 145
|
||||
#define IMX_SC_R_GPU_0_PID2 146
|
||||
#define IMX_SC_R_GPU_0_PID3 147
|
||||
#define IMX_SC_R_GPU_1_PID0 148
|
||||
#define IMX_SC_R_GPU_1_PID1 149
|
||||
#define IMX_SC_R_GPU_1_PID2 150
|
||||
#define IMX_SC_R_GPU_1_PID3 151
|
||||
#define IMX_SC_R_PCIE_A 152
|
||||
#define IMX_SC_R_SERDES_0 153
|
||||
#define IMX_SC_R_MATCH_0 154
|
||||
#define IMX_SC_R_MATCH_1 155
|
||||
#define IMX_SC_R_MATCH_2 156
|
||||
#define IMX_SC_R_MATCH_3 157
|
||||
#define IMX_SC_R_MATCH_4 158
|
||||
#define IMX_SC_R_MATCH_5 159
|
||||
#define IMX_SC_R_MATCH_6 160
|
||||
#define IMX_SC_R_MATCH_7 161
|
||||
#define IMX_SC_R_MATCH_8 162
|
||||
#define IMX_SC_R_MATCH_9 163
|
||||
#define IMX_SC_R_MATCH_10 164
|
||||
#define IMX_SC_R_MATCH_11 165
|
||||
#define IMX_SC_R_MATCH_12 166
|
||||
#define IMX_SC_R_MATCH_13 167
|
||||
#define IMX_SC_R_MATCH_14 168
|
||||
#define IMX_SC_R_PCIE_B 169
|
||||
#define IMX_SC_R_SATA_0 170
|
||||
#define IMX_SC_R_SERDES_1 171
|
||||
#define IMX_SC_R_HSIO_GPIO 172
|
||||
#define IMX_SC_R_MATCH_15 173
|
||||
#define IMX_SC_R_MATCH_16 174
|
||||
#define IMX_SC_R_MATCH_17 175
|
||||
#define IMX_SC_R_MATCH_18 176
|
||||
#define IMX_SC_R_MATCH_19 177
|
||||
#define IMX_SC_R_MATCH_20 178
|
||||
#define IMX_SC_R_MATCH_21 179
|
||||
#define IMX_SC_R_MATCH_22 180
|
||||
#define IMX_SC_R_MATCH_23 181
|
||||
#define IMX_SC_R_MATCH_24 182
|
||||
#define IMX_SC_R_MATCH_25 183
|
||||
#define IMX_SC_R_MATCH_26 184
|
||||
#define IMX_SC_R_MATCH_27 185
|
||||
#define IMX_SC_R_MATCH_28 186
|
||||
#define IMX_SC_R_LCD_0 187
|
||||
#define IMX_SC_R_LCD_0_PWM_0 188
|
||||
#define IMX_SC_R_LCD_0_I2C_0 189
|
||||
#define IMX_SC_R_LCD_0_I2C_1 190
|
||||
#define IMX_SC_R_PWM_0 191
|
||||
#define IMX_SC_R_PWM_1 192
|
||||
#define IMX_SC_R_PWM_2 193
|
||||
#define IMX_SC_R_PWM_3 194
|
||||
#define IMX_SC_R_PWM_4 195
|
||||
#define IMX_SC_R_PWM_5 196
|
||||
#define IMX_SC_R_PWM_6 197
|
||||
#define IMX_SC_R_PWM_7 198
|
||||
#define IMX_SC_R_GPIO_0 199
|
||||
#define IMX_SC_R_GPIO_1 200
|
||||
#define IMX_SC_R_GPIO_2 201
|
||||
#define IMX_SC_R_GPIO_3 202
|
||||
#define IMX_SC_R_GPIO_4 203
|
||||
#define IMX_SC_R_GPIO_5 204
|
||||
#define IMX_SC_R_GPIO_6 205
|
||||
#define IMX_SC_R_GPIO_7 206
|
||||
#define IMX_SC_R_GPT_0 207
|
||||
#define IMX_SC_R_GPT_1 208
|
||||
#define IMX_SC_R_GPT_2 209
|
||||
#define IMX_SC_R_GPT_3 210
|
||||
#define IMX_SC_R_GPT_4 211
|
||||
#define IMX_SC_R_KPP 212
|
||||
#define IMX_SC_R_MU_0A 213
|
||||
#define IMX_SC_R_MU_1A 214
|
||||
#define IMX_SC_R_MU_2A 215
|
||||
#define IMX_SC_R_MU_3A 216
|
||||
#define IMX_SC_R_MU_4A 217
|
||||
#define IMX_SC_R_MU_5A 218
|
||||
#define IMX_SC_R_MU_6A 219
|
||||
#define IMX_SC_R_MU_7A 220
|
||||
#define IMX_SC_R_MU_8A 221
|
||||
#define IMX_SC_R_MU_9A 222
|
||||
#define IMX_SC_R_MU_10A 223
|
||||
#define IMX_SC_R_MU_11A 224
|
||||
#define IMX_SC_R_MU_12A 225
|
||||
#define IMX_SC_R_MU_13A 226
|
||||
#define IMX_SC_R_MU_5B 227
|
||||
#define IMX_SC_R_MU_6B 228
|
||||
#define IMX_SC_R_MU_7B 229
|
||||
#define IMX_SC_R_MU_8B 230
|
||||
#define IMX_SC_R_MU_9B 231
|
||||
#define IMX_SC_R_MU_10B 232
|
||||
#define IMX_SC_R_MU_11B 233
|
||||
#define IMX_SC_R_MU_12B 234
|
||||
#define IMX_SC_R_MU_13B 235
|
||||
#define IMX_SC_R_ROM_0 236
|
||||
#define IMX_SC_R_FSPI_0 237
|
||||
#define IMX_SC_R_FSPI_1 238
|
||||
#define IMX_SC_R_IEE 239
|
||||
#define IMX_SC_R_IEE_R0 240
|
||||
#define IMX_SC_R_IEE_R1 241
|
||||
#define IMX_SC_R_IEE_R2 242
|
||||
#define IMX_SC_R_IEE_R3 243
|
||||
#define IMX_SC_R_IEE_R4 244
|
||||
#define IMX_SC_R_IEE_R5 245
|
||||
#define IMX_SC_R_IEE_R6 246
|
||||
#define IMX_SC_R_IEE_R7 247
|
||||
#define IMX_SC_R_SDHC_0 248
|
||||
#define IMX_SC_R_SDHC_1 249
|
||||
#define IMX_SC_R_SDHC_2 250
|
||||
#define IMX_SC_R_ENET_0 251
|
||||
#define IMX_SC_R_ENET_1 252
|
||||
#define IMX_SC_R_MLB_0 253
|
||||
#define IMX_SC_R_DMA_2_CH0 254
|
||||
#define IMX_SC_R_DMA_2_CH1 255
|
||||
#define IMX_SC_R_DMA_2_CH2 256
|
||||
#define IMX_SC_R_DMA_2_CH3 257
|
||||
#define IMX_SC_R_DMA_2_CH4 258
|
||||
#define IMX_SC_R_USB_0 259
|
||||
#define IMX_SC_R_USB_1 260
|
||||
#define IMX_SC_R_USB_0_PHY 261
|
||||
#define IMX_SC_R_USB_2 262
|
||||
#define IMX_SC_R_USB_2_PHY 263
|
||||
#define IMX_SC_R_DTCP 264
|
||||
#define IMX_SC_R_NAND 265
|
||||
#define IMX_SC_R_LVDS_0 266
|
||||
#define IMX_SC_R_LVDS_0_PWM_0 267
|
||||
#define IMX_SC_R_LVDS_0_I2C_0 268
|
||||
#define IMX_SC_R_LVDS_0_I2C_1 269
|
||||
#define IMX_SC_R_LVDS_1 270
|
||||
#define IMX_SC_R_LVDS_1_PWM_0 271
|
||||
#define IMX_SC_R_LVDS_1_I2C_0 272
|
||||
#define IMX_SC_R_LVDS_1_I2C_1 273
|
||||
#define IMX_SC_R_LVDS_2 274
|
||||
#define IMX_SC_R_LVDS_2_PWM_0 275
|
||||
#define IMX_SC_R_LVDS_2_I2C_0 276
|
||||
#define IMX_SC_R_LVDS_2_I2C_1 277
|
||||
#define IMX_SC_R_M4_0_PID0 278
|
||||
#define IMX_SC_R_M4_0_PID1 279
|
||||
#define IMX_SC_R_M4_0_PID2 280
|
||||
#define IMX_SC_R_M4_0_PID3 281
|
||||
#define IMX_SC_R_M4_0_PID4 282
|
||||
#define IMX_SC_R_M4_0_RGPIO 283
|
||||
#define IMX_SC_R_M4_0_SEMA42 284
|
||||
#define IMX_SC_R_M4_0_TPM 285
|
||||
#define IMX_SC_R_M4_0_PIT 286
|
||||
#define IMX_SC_R_M4_0_UART 287
|
||||
#define IMX_SC_R_M4_0_I2C 288
|
||||
#define IMX_SC_R_M4_0_INTMUX 289
|
||||
#define IMX_SC_R_M4_0_SIM 290
|
||||
#define IMX_SC_R_M4_0_WDOG 291
|
||||
#define IMX_SC_R_M4_0_MU_0B 292
|
||||
#define IMX_SC_R_M4_0_MU_0A0 293
|
||||
#define IMX_SC_R_M4_0_MU_0A1 294
|
||||
#define IMX_SC_R_M4_0_MU_0A2 295
|
||||
#define IMX_SC_R_M4_0_MU_0A3 296
|
||||
#define IMX_SC_R_M4_0_MU_1A 297
|
||||
#define IMX_SC_R_M4_1_PID0 298
|
||||
#define IMX_SC_R_M4_1_PID1 299
|
||||
#define IMX_SC_R_M4_1_PID2 300
|
||||
#define IMX_SC_R_M4_1_PID3 301
|
||||
#define IMX_SC_R_M4_1_PID4 302
|
||||
#define IMX_SC_R_M4_1_RGPIO 303
|
||||
#define IMX_SC_R_M4_1_SEMA42 304
|
||||
#define IMX_SC_R_M4_1_TPM 305
|
||||
#define IMX_SC_R_M4_1_PIT 306
|
||||
#define IMX_SC_R_M4_1_UART 307
|
||||
#define IMX_SC_R_M4_1_I2C 308
|
||||
#define IMX_SC_R_M4_1_INTMUX 309
|
||||
#define IMX_SC_R_M4_1_SIM 310
|
||||
#define IMX_SC_R_M4_1_WDOG 311
|
||||
#define IMX_SC_R_M4_1_MU_0B 312
|
||||
#define IMX_SC_R_M4_1_MU_0A0 313
|
||||
#define IMX_SC_R_M4_1_MU_0A1 314
|
||||
#define IMX_SC_R_M4_1_MU_0A2 315
|
||||
#define IMX_SC_R_M4_1_MU_0A3 316
|
||||
#define IMX_SC_R_M4_1_MU_1A 317
|
||||
#define IMX_SC_R_SAI_0 318
|
||||
#define IMX_SC_R_SAI_1 319
|
||||
#define IMX_SC_R_SAI_2 320
|
||||
#define IMX_SC_R_IRQSTR_SCU2 321
|
||||
#define IMX_SC_R_IRQSTR_DSP 322
|
||||
#define IMX_SC_R_ELCDIF_PLL 323
|
||||
#define IMX_SC_R_UNUSED6 324
|
||||
#define IMX_SC_R_AUDIO_PLL_0 325
|
||||
#define IMX_SC_R_PI_0 326
|
||||
#define IMX_SC_R_PI_0_PWM_0 327
|
||||
#define IMX_SC_R_PI_0_PWM_1 328
|
||||
#define IMX_SC_R_PI_0_I2C_0 329
|
||||
#define IMX_SC_R_PI_0_PLL 330
|
||||
#define IMX_SC_R_PI_1 331
|
||||
#define IMX_SC_R_PI_1_PWM_0 332
|
||||
#define IMX_SC_R_PI_1_PWM_1 333
|
||||
#define IMX_SC_R_PI_1_I2C_0 334
|
||||
#define IMX_SC_R_PI_1_PLL 335
|
||||
#define IMX_SC_R_SC_PID0 336
|
||||
#define IMX_SC_R_SC_PID1 337
|
||||
#define IMX_SC_R_SC_PID2 338
|
||||
#define IMX_SC_R_SC_PID3 339
|
||||
#define IMX_SC_R_SC_PID4 340
|
||||
#define IMX_SC_R_SC_SEMA42 341
|
||||
#define IMX_SC_R_SC_TPM 342
|
||||
#define IMX_SC_R_SC_PIT 343
|
||||
#define IMX_SC_R_SC_UART 344
|
||||
#define IMX_SC_R_SC_I2C 345
|
||||
#define IMX_SC_R_SC_MU_0B 346
|
||||
#define IMX_SC_R_SC_MU_0A0 347
|
||||
#define IMX_SC_R_SC_MU_0A1 348
|
||||
#define IMX_SC_R_SC_MU_0A2 349
|
||||
#define IMX_SC_R_SC_MU_0A3 350
|
||||
#define IMX_SC_R_SC_MU_1A 351
|
||||
#define IMX_SC_R_SYSCNT_RD 352
|
||||
#define IMX_SC_R_SYSCNT_CMP 353
|
||||
#define IMX_SC_R_DEBUG 354
|
||||
#define IMX_SC_R_SYSTEM 355
|
||||
#define IMX_SC_R_SNVS 356
|
||||
#define IMX_SC_R_OTP 357
|
||||
#define IMX_SC_R_VPU_PID0 358
|
||||
#define IMX_SC_R_VPU_PID1 359
|
||||
#define IMX_SC_R_VPU_PID2 360
|
||||
#define IMX_SC_R_VPU_PID3 361
|
||||
#define IMX_SC_R_VPU_PID4 362
|
||||
#define IMX_SC_R_VPU_PID5 363
|
||||
#define IMX_SC_R_VPU_PID6 364
|
||||
#define IMX_SC_R_VPU_PID7 365
|
||||
#define IMX_SC_R_VPU_UART 366
|
||||
#define IMX_SC_R_VPUCORE 367
|
||||
#define IMX_SC_R_VPUCORE_0 368
|
||||
#define IMX_SC_R_VPUCORE_1 369
|
||||
#define IMX_SC_R_VPUCORE_2 370
|
||||
#define IMX_SC_R_VPUCORE_3 371
|
||||
#define IMX_SC_R_DMA_4_CH0 372
|
||||
#define IMX_SC_R_DMA_4_CH1 373
|
||||
#define IMX_SC_R_DMA_4_CH2 374
|
||||
#define IMX_SC_R_DMA_4_CH3 375
|
||||
#define IMX_SC_R_DMA_4_CH4 376
|
||||
#define IMX_SC_R_ISI_CH0 377
|
||||
#define IMX_SC_R_ISI_CH1 378
|
||||
#define IMX_SC_R_ISI_CH2 379
|
||||
#define IMX_SC_R_ISI_CH3 380
|
||||
#define IMX_SC_R_ISI_CH4 381
|
||||
#define IMX_SC_R_ISI_CH5 382
|
||||
#define IMX_SC_R_ISI_CH6 383
|
||||
#define IMX_SC_R_ISI_CH7 384
|
||||
#define IMX_SC_R_MJPEG_DEC_S0 385
|
||||
#define IMX_SC_R_MJPEG_DEC_S1 386
|
||||
#define IMX_SC_R_MJPEG_DEC_S2 387
|
||||
#define IMX_SC_R_MJPEG_DEC_S3 388
|
||||
#define IMX_SC_R_MJPEG_ENC_S0 389
|
||||
#define IMX_SC_R_MJPEG_ENC_S1 390
|
||||
#define IMX_SC_R_MJPEG_ENC_S2 391
|
||||
#define IMX_SC_R_MJPEG_ENC_S3 392
|
||||
#define IMX_SC_R_MIPI_0 393
|
||||
#define IMX_SC_R_MIPI_0_PWM_0 394
|
||||
#define IMX_SC_R_MIPI_0_I2C_0 395
|
||||
#define IMX_SC_R_MIPI_0_I2C_1 396
|
||||
#define IMX_SC_R_MIPI_1 397
|
||||
#define IMX_SC_R_MIPI_1_PWM_0 398
|
||||
#define IMX_SC_R_MIPI_1_I2C_0 399
|
||||
#define IMX_SC_R_MIPI_1_I2C_1 400
|
||||
#define IMX_SC_R_CSI_0 401
|
||||
#define IMX_SC_R_CSI_0_PWM_0 402
|
||||
#define IMX_SC_R_CSI_0_I2C_0 403
|
||||
#define IMX_SC_R_CSI_1 404
|
||||
#define IMX_SC_R_CSI_1_PWM_0 405
|
||||
#define IMX_SC_R_CSI_1_I2C_0 406
|
||||
#define IMX_SC_R_HDMI 407
|
||||
#define IMX_SC_R_HDMI_I2S 408
|
||||
#define IMX_SC_R_HDMI_I2C_0 409
|
||||
#define IMX_SC_R_HDMI_PLL_0 410
|
||||
#define IMX_SC_R_HDMI_RX 411
|
||||
#define IMX_SC_R_HDMI_RX_BYPASS 412
|
||||
#define IMX_SC_R_HDMI_RX_I2C_0 413
|
||||
#define IMX_SC_R_ASRC_0 414
|
||||
#define IMX_SC_R_ESAI_0 415
|
||||
#define IMX_SC_R_SPDIF_0 416
|
||||
#define IMX_SC_R_SPDIF_1 417
|
||||
#define IMX_SC_R_SAI_3 418
|
||||
#define IMX_SC_R_SAI_4 419
|
||||
#define IMX_SC_R_SAI_5 420
|
||||
#define IMX_SC_R_GPT_5 421
|
||||
#define IMX_SC_R_GPT_6 422
|
||||
#define IMX_SC_R_GPT_7 423
|
||||
#define IMX_SC_R_GPT_8 424
|
||||
#define IMX_SC_R_GPT_9 425
|
||||
#define IMX_SC_R_GPT_10 426
|
||||
#define IMX_SC_R_DMA_2_CH5 427
|
||||
#define IMX_SC_R_DMA_2_CH6 428
|
||||
#define IMX_SC_R_DMA_2_CH7 429
|
||||
#define IMX_SC_R_DMA_2_CH8 430
|
||||
#define IMX_SC_R_DMA_2_CH9 431
|
||||
#define IMX_SC_R_DMA_2_CH10 432
|
||||
#define IMX_SC_R_DMA_2_CH11 433
|
||||
#define IMX_SC_R_DMA_2_CH12 434
|
||||
#define IMX_SC_R_DMA_2_CH13 435
|
||||
#define IMX_SC_R_DMA_2_CH14 436
|
||||
#define IMX_SC_R_DMA_2_CH15 437
|
||||
#define IMX_SC_R_DMA_2_CH16 438
|
||||
#define IMX_SC_R_DMA_2_CH17 439
|
||||
#define IMX_SC_R_DMA_2_CH18 440
|
||||
#define IMX_SC_R_DMA_2_CH19 441
|
||||
#define IMX_SC_R_DMA_2_CH20 442
|
||||
#define IMX_SC_R_DMA_2_CH21 443
|
||||
#define IMX_SC_R_DMA_2_CH22 444
|
||||
#define IMX_SC_R_DMA_2_CH23 445
|
||||
#define IMX_SC_R_DMA_2_CH24 446
|
||||
#define IMX_SC_R_DMA_2_CH25 447
|
||||
#define IMX_SC_R_DMA_2_CH26 448
|
||||
#define IMX_SC_R_DMA_2_CH27 449
|
||||
#define IMX_SC_R_DMA_2_CH28 450
|
||||
#define IMX_SC_R_DMA_2_CH29 451
|
||||
#define IMX_SC_R_DMA_2_CH30 452
|
||||
#define IMX_SC_R_DMA_2_CH31 453
|
||||
#define IMX_SC_R_ASRC_1 454
|
||||
#define IMX_SC_R_ESAI_1 455
|
||||
#define IMX_SC_R_SAI_6 456
|
||||
#define IMX_SC_R_SAI_7 457
|
||||
#define IMX_SC_R_AMIX 458
|
||||
#define IMX_SC_R_MQS_0 459
|
||||
#define IMX_SC_R_DMA_3_CH0 460
|
||||
#define IMX_SC_R_DMA_3_CH1 461
|
||||
#define IMX_SC_R_DMA_3_CH2 462
|
||||
#define IMX_SC_R_DMA_3_CH3 463
|
||||
#define IMX_SC_R_DMA_3_CH4 464
|
||||
#define IMX_SC_R_DMA_3_CH5 465
|
||||
#define IMX_SC_R_DMA_3_CH6 466
|
||||
#define IMX_SC_R_DMA_3_CH7 467
|
||||
#define IMX_SC_R_DMA_3_CH8 468
|
||||
#define IMX_SC_R_DMA_3_CH9 469
|
||||
#define IMX_SC_R_DMA_3_CH10 470
|
||||
#define IMX_SC_R_DMA_3_CH11 471
|
||||
#define IMX_SC_R_DMA_3_CH12 472
|
||||
#define IMX_SC_R_DMA_3_CH13 473
|
||||
#define IMX_SC_R_DMA_3_CH14 474
|
||||
#define IMX_SC_R_DMA_3_CH15 475
|
||||
#define IMX_SC_R_DMA_3_CH16 476
|
||||
#define IMX_SC_R_DMA_3_CH17 477
|
||||
#define IMX_SC_R_DMA_3_CH18 478
|
||||
#define IMX_SC_R_DMA_3_CH19 479
|
||||
#define IMX_SC_R_DMA_3_CH20 480
|
||||
#define IMX_SC_R_DMA_3_CH21 481
|
||||
#define IMX_SC_R_DMA_3_CH22 482
|
||||
#define IMX_SC_R_DMA_3_CH23 483
|
||||
#define IMX_SC_R_DMA_3_CH24 484
|
||||
#define IMX_SC_R_DMA_3_CH25 485
|
||||
#define IMX_SC_R_DMA_3_CH26 486
|
||||
#define IMX_SC_R_DMA_3_CH27 487
|
||||
#define IMX_SC_R_DMA_3_CH28 488
|
||||
#define IMX_SC_R_DMA_3_CH29 489
|
||||
#define IMX_SC_R_DMA_3_CH30 490
|
||||
#define IMX_SC_R_DMA_3_CH31 491
|
||||
#define IMX_SC_R_AUDIO_PLL_1 492
|
||||
#define IMX_SC_R_AUDIO_CLK_0 493
|
||||
#define IMX_SC_R_AUDIO_CLK_1 494
|
||||
#define IMX_SC_R_MCLK_OUT_0 495
|
||||
#define IMX_SC_R_MCLK_OUT_1 496
|
||||
#define IMX_SC_R_PMIC_0 497
|
||||
#define IMX_SC_R_PMIC_1 498
|
||||
#define IMX_SC_R_SECO 499
|
||||
#define IMX_SC_R_CAAM_JR1 500
|
||||
#define IMX_SC_R_CAAM_JR2 501
|
||||
#define IMX_SC_R_CAAM_JR3 502
|
||||
#define IMX_SC_R_SECO_MU_2 503
|
||||
#define IMX_SC_R_SECO_MU_3 504
|
||||
#define IMX_SC_R_SECO_MU_4 505
|
||||
#define IMX_SC_R_HDMI_RX_PWM_0 506
|
||||
#define IMX_SC_R_A35 507
|
||||
#define IMX_SC_R_A35_0 508
|
||||
#define IMX_SC_R_A35_1 509
|
||||
#define IMX_SC_R_A35_2 510
|
||||
#define IMX_SC_R_A35_3 511
|
||||
#define IMX_SC_R_DSP 512
|
||||
#define IMX_SC_R_DSP_RAM 513
|
||||
#define IMX_SC_R_CAAM_JR1_OUT 514
|
||||
#define IMX_SC_R_CAAM_JR2_OUT 515
|
||||
#define IMX_SC_R_CAAM_JR3_OUT 516
|
||||
#define IMX_SC_R_VPU_DEC_0 517
|
||||
#define IMX_SC_R_VPU_ENC_0 518
|
||||
#define IMX_SC_R_CAAM_JR0 519
|
||||
#define IMX_SC_R_CAAM_JR0_OUT 520
|
||||
#define IMX_SC_R_PMIC_2 521
|
||||
#define IMX_SC_R_DBLOGIC 522
|
||||
#define IMX_SC_R_HDMI_PLL_1 523
|
||||
#define IMX_SC_R_BOARD_R0 524
|
||||
#define IMX_SC_R_BOARD_R1 525
|
||||
#define IMX_SC_R_BOARD_R2 526
|
||||
#define IMX_SC_R_BOARD_R3 527
|
||||
#define IMX_SC_R_BOARD_R4 528
|
||||
#define IMX_SC_R_BOARD_R5 529
|
||||
#define IMX_SC_R_BOARD_R6 530
|
||||
#define IMX_SC_R_BOARD_R7 531
|
||||
#define IMX_SC_R_MJPEG_DEC_MP 532
|
||||
#define IMX_SC_R_MJPEG_ENC_MP 533
|
||||
#define IMX_SC_R_VPU_TS_0 534
|
||||
#define IMX_SC_R_VPU_MU_0 535
|
||||
#define IMX_SC_R_VPU_MU_1 536
|
||||
#define IMX_SC_R_VPU_MU_2 537
|
||||
#define IMX_SC_R_VPU_MU_3 538
|
||||
#define IMX_SC_R_VPU_ENC_1 539
|
||||
#define IMX_SC_R_VPU 540
|
||||
#define IMX_SC_R_LAST 541
|
||||
|
||||
#endif /* __DT_BINDINGS_RSCRC_IMX_H */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__
|
||||
#define __DT_BINDINGS_IMX8MQ_POWER_H__
|
||||
|
||||
#define IMX8M_POWER_DOMAIN_MIPI 0
|
||||
#define IMX8M_POWER_DOMAIN_PCIE1 1
|
||||
#define IMX8M_POWER_DOMAIN_USB_OTG1 2
|
||||
#define IMX8M_POWER_DOMAIN_USB_OTG2 3
|
||||
#define IMX8M_POWER_DOMAIN_DDR1 4
|
||||
#define IMX8M_POWER_DOMAIN_GPU 5
|
||||
#define IMX8M_POWER_DOMAIN_VPU 6
|
||||
#define IMX8M_POWER_DOMAIN_DISP 7
|
||||
#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8
|
||||
#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
|
||||
#define IMX8M_POWER_DOMAIN_PCIE2 10
|
||||
|
||||
#endif
|
||||
|
|
@ -14,4 +14,5 @@
|
|||
#include <linux/firmware/imx/types.h>
|
||||
|
||||
#include <linux/firmware/imx/svc/misc.h>
|
||||
#include <linux/firmware/imx/svc/pm.h>
|
||||
#endif /* _SC_SCI_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,85 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2018 NXP
|
||||
*
|
||||
* Header file containing the public API for the System Controller (SC)
|
||||
* Power Management (PM) function. This includes functions for power state
|
||||
* control, clock control, reset control, and wake-up event control.
|
||||
*
|
||||
* PM_SVC (SVC) Power Management Service
|
||||
*
|
||||
* Module for the Power Management (PM) service.
|
||||
*/
|
||||
|
||||
#ifndef _SC_PM_API_H
|
||||
#define _SC_PM_API_H
|
||||
|
||||
#include <linux/firmware/imx/sci.h>
|
||||
|
||||
/*
|
||||
* This type is used to indicate RPC PM function calls.
|
||||
*/
|
||||
enum imx_sc_pm_func {
|
||||
IMX_SC_PM_FUNC_UNKNOWN = 0,
|
||||
IMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19,
|
||||
IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1,
|
||||
IMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2,
|
||||
IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3,
|
||||
IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4,
|
||||
IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16,
|
||||
IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17,
|
||||
IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18,
|
||||
IMX_SC_PM_FUNC_SET_CLOCK_RATE = 5,
|
||||
IMX_SC_PM_FUNC_GET_CLOCK_RATE = 6,
|
||||
IMX_SC_PM_FUNC_CLOCK_ENABLE = 7,
|
||||
IMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14,
|
||||
IMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15,
|
||||
IMX_SC_PM_FUNC_RESET = 13,
|
||||
IMX_SC_PM_FUNC_RESET_REASON = 10,
|
||||
IMX_SC_PM_FUNC_BOOT = 8,
|
||||
IMX_SC_PM_FUNC_REBOOT = 9,
|
||||
IMX_SC_PM_FUNC_REBOOT_PARTITION = 12,
|
||||
IMX_SC_PM_FUNC_CPU_START = 11,
|
||||
};
|
||||
|
||||
/*
|
||||
* Defines for ALL parameters
|
||||
*/
|
||||
#define IMX_SC_PM_CLK_ALL UINT8_MAX /* All clocks */
|
||||
|
||||
/*
|
||||
* Defines for SC PM Power Mode
|
||||
*/
|
||||
#define IMX_SC_PM_PW_MODE_OFF 0 /* Power off */
|
||||
#define IMX_SC_PM_PW_MODE_STBY 1 /* Power in standby */
|
||||
#define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */
|
||||
#define IMX_SC_PM_PW_MODE_ON 3 /* Power on */
|
||||
|
||||
/*
|
||||
* Defines for SC PM CLK
|
||||
*/
|
||||
#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */
|
||||
#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */
|
||||
#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */
|
||||
#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
|
||||
#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */
|
||||
#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */
|
||||
#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */
|
||||
#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */
|
||||
#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */
|
||||
#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */
|
||||
#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */
|
||||
#define IMX_SC_PM_CLK_PLL 4 /* PLL */
|
||||
#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */
|
||||
|
||||
/*
|
||||
* Defines for SC PM CLK Parent
|
||||
*/
|
||||
#define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */
|
||||
#define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
|
||||
#define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
|
||||
#define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
|
||||
#define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */
|
||||
|
||||
#endif /* _SC_PM_API_H */
|
||||
|
|
@ -9,558 +9,6 @@
|
|||
#ifndef _SC_TYPES_H
|
||||
#define _SC_TYPES_H
|
||||
|
||||
/*
|
||||
* This type is used to indicate a resource. Resources include peripherals
|
||||
* and bus masters (but not memory regions). Note items from list should
|
||||
* never be changed or removed (only added to at the end of the list).
|
||||
*/
|
||||
enum imx_sc_rsrc {
|
||||
IMX_SC_R_A53 = 0,
|
||||
IMX_SC_R_A53_0 = 1,
|
||||
IMX_SC_R_A53_1 = 2,
|
||||
IMX_SC_R_A53_2 = 3,
|
||||
IMX_SC_R_A53_3 = 4,
|
||||
IMX_SC_R_A72 = 5,
|
||||
IMX_SC_R_A72_0 = 6,
|
||||
IMX_SC_R_A72_1 = 7,
|
||||
IMX_SC_R_A72_2 = 8,
|
||||
IMX_SC_R_A72_3 = 9,
|
||||
IMX_SC_R_CCI = 10,
|
||||
IMX_SC_R_DB = 11,
|
||||
IMX_SC_R_DRC_0 = 12,
|
||||
IMX_SC_R_DRC_1 = 13,
|
||||
IMX_SC_R_GIC_SMMU = 14,
|
||||
IMX_SC_R_IRQSTR_M4_0 = 15,
|
||||
IMX_SC_R_IRQSTR_M4_1 = 16,
|
||||
IMX_SC_R_SMMU = 17,
|
||||
IMX_SC_R_GIC = 18,
|
||||
IMX_SC_R_DC_0_BLIT0 = 19,
|
||||
IMX_SC_R_DC_0_BLIT1 = 20,
|
||||
IMX_SC_R_DC_0_BLIT2 = 21,
|
||||
IMX_SC_R_DC_0_BLIT_OUT = 22,
|
||||
IMX_SC_R_DC_0_CAPTURE0 = 23,
|
||||
IMX_SC_R_DC_0_CAPTURE1 = 24,
|
||||
IMX_SC_R_DC_0_WARP = 25,
|
||||
IMX_SC_R_DC_0_INTEGRAL0 = 26,
|
||||
IMX_SC_R_DC_0_INTEGRAL1 = 27,
|
||||
IMX_SC_R_DC_0_VIDEO0 = 28,
|
||||
IMX_SC_R_DC_0_VIDEO1 = 29,
|
||||
IMX_SC_R_DC_0_FRAC0 = 30,
|
||||
IMX_SC_R_DC_0_FRAC1 = 31,
|
||||
IMX_SC_R_DC_0 = 32,
|
||||
IMX_SC_R_GPU_2_PID0 = 33,
|
||||
IMX_SC_R_DC_0_PLL_0 = 34,
|
||||
IMX_SC_R_DC_0_PLL_1 = 35,
|
||||
IMX_SC_R_DC_1_BLIT0 = 36,
|
||||
IMX_SC_R_DC_1_BLIT1 = 37,
|
||||
IMX_SC_R_DC_1_BLIT2 = 38,
|
||||
IMX_SC_R_DC_1_BLIT_OUT = 39,
|
||||
IMX_SC_R_DC_1_CAPTURE0 = 40,
|
||||
IMX_SC_R_DC_1_CAPTURE1 = 41,
|
||||
IMX_SC_R_DC_1_WARP = 42,
|
||||
IMX_SC_R_DC_1_INTEGRAL0 = 43,
|
||||
IMX_SC_R_DC_1_INTEGRAL1 = 44,
|
||||
IMX_SC_R_DC_1_VIDEO0 = 45,
|
||||
IMX_SC_R_DC_1_VIDEO1 = 46,
|
||||
IMX_SC_R_DC_1_FRAC0 = 47,
|
||||
IMX_SC_R_DC_1_FRAC1 = 48,
|
||||
IMX_SC_R_DC_1 = 49,
|
||||
IMX_SC_R_GPU_3_PID0 = 50,
|
||||
IMX_SC_R_DC_1_PLL_0 = 51,
|
||||
IMX_SC_R_DC_1_PLL_1 = 52,
|
||||
IMX_SC_R_SPI_0 = 53,
|
||||
IMX_SC_R_SPI_1 = 54,
|
||||
IMX_SC_R_SPI_2 = 55,
|
||||
IMX_SC_R_SPI_3 = 56,
|
||||
IMX_SC_R_UART_0 = 57,
|
||||
IMX_SC_R_UART_1 = 58,
|
||||
IMX_SC_R_UART_2 = 59,
|
||||
IMX_SC_R_UART_3 = 60,
|
||||
IMX_SC_R_UART_4 = 61,
|
||||
IMX_SC_R_EMVSIM_0 = 62,
|
||||
IMX_SC_R_EMVSIM_1 = 63,
|
||||
IMX_SC_R_DMA_0_CH0 = 64,
|
||||
IMX_SC_R_DMA_0_CH1 = 65,
|
||||
IMX_SC_R_DMA_0_CH2 = 66,
|
||||
IMX_SC_R_DMA_0_CH3 = 67,
|
||||
IMX_SC_R_DMA_0_CH4 = 68,
|
||||
IMX_SC_R_DMA_0_CH5 = 69,
|
||||
IMX_SC_R_DMA_0_CH6 = 70,
|
||||
IMX_SC_R_DMA_0_CH7 = 71,
|
||||
IMX_SC_R_DMA_0_CH8 = 72,
|
||||
IMX_SC_R_DMA_0_CH9 = 73,
|
||||
IMX_SC_R_DMA_0_CH10 = 74,
|
||||
IMX_SC_R_DMA_0_CH11 = 75,
|
||||
IMX_SC_R_DMA_0_CH12 = 76,
|
||||
IMX_SC_R_DMA_0_CH13 = 77,
|
||||
IMX_SC_R_DMA_0_CH14 = 78,
|
||||
IMX_SC_R_DMA_0_CH15 = 79,
|
||||
IMX_SC_R_DMA_0_CH16 = 80,
|
||||
IMX_SC_R_DMA_0_CH17 = 81,
|
||||
IMX_SC_R_DMA_0_CH18 = 82,
|
||||
IMX_SC_R_DMA_0_CH19 = 83,
|
||||
IMX_SC_R_DMA_0_CH20 = 84,
|
||||
IMX_SC_R_DMA_0_CH21 = 85,
|
||||
IMX_SC_R_DMA_0_CH22 = 86,
|
||||
IMX_SC_R_DMA_0_CH23 = 87,
|
||||
IMX_SC_R_DMA_0_CH24 = 88,
|
||||
IMX_SC_R_DMA_0_CH25 = 89,
|
||||
IMX_SC_R_DMA_0_CH26 = 90,
|
||||
IMX_SC_R_DMA_0_CH27 = 91,
|
||||
IMX_SC_R_DMA_0_CH28 = 92,
|
||||
IMX_SC_R_DMA_0_CH29 = 93,
|
||||
IMX_SC_R_DMA_0_CH30 = 94,
|
||||
IMX_SC_R_DMA_0_CH31 = 95,
|
||||
IMX_SC_R_I2C_0 = 96,
|
||||
IMX_SC_R_I2C_1 = 97,
|
||||
IMX_SC_R_I2C_2 = 98,
|
||||
IMX_SC_R_I2C_3 = 99,
|
||||
IMX_SC_R_I2C_4 = 100,
|
||||
IMX_SC_R_ADC_0 = 101,
|
||||
IMX_SC_R_ADC_1 = 102,
|
||||
IMX_SC_R_FTM_0 = 103,
|
||||
IMX_SC_R_FTM_1 = 104,
|
||||
IMX_SC_R_CAN_0 = 105,
|
||||
IMX_SC_R_CAN_1 = 106,
|
||||
IMX_SC_R_CAN_2 = 107,
|
||||
IMX_SC_R_DMA_1_CH0 = 108,
|
||||
IMX_SC_R_DMA_1_CH1 = 109,
|
||||
IMX_SC_R_DMA_1_CH2 = 110,
|
||||
IMX_SC_R_DMA_1_CH3 = 111,
|
||||
IMX_SC_R_DMA_1_CH4 = 112,
|
||||
IMX_SC_R_DMA_1_CH5 = 113,
|
||||
IMX_SC_R_DMA_1_CH6 = 114,
|
||||
IMX_SC_R_DMA_1_CH7 = 115,
|
||||
IMX_SC_R_DMA_1_CH8 = 116,
|
||||
IMX_SC_R_DMA_1_CH9 = 117,
|
||||
IMX_SC_R_DMA_1_CH10 = 118,
|
||||
IMX_SC_R_DMA_1_CH11 = 119,
|
||||
IMX_SC_R_DMA_1_CH12 = 120,
|
||||
IMX_SC_R_DMA_1_CH13 = 121,
|
||||
IMX_SC_R_DMA_1_CH14 = 122,
|
||||
IMX_SC_R_DMA_1_CH15 = 123,
|
||||
IMX_SC_R_DMA_1_CH16 = 124,
|
||||
IMX_SC_R_DMA_1_CH17 = 125,
|
||||
IMX_SC_R_DMA_1_CH18 = 126,
|
||||
IMX_SC_R_DMA_1_CH19 = 127,
|
||||
IMX_SC_R_DMA_1_CH20 = 128,
|
||||
IMX_SC_R_DMA_1_CH21 = 129,
|
||||
IMX_SC_R_DMA_1_CH22 = 130,
|
||||
IMX_SC_R_DMA_1_CH23 = 131,
|
||||
IMX_SC_R_DMA_1_CH24 = 132,
|
||||
IMX_SC_R_DMA_1_CH25 = 133,
|
||||
IMX_SC_R_DMA_1_CH26 = 134,
|
||||
IMX_SC_R_DMA_1_CH27 = 135,
|
||||
IMX_SC_R_DMA_1_CH28 = 136,
|
||||
IMX_SC_R_DMA_1_CH29 = 137,
|
||||
IMX_SC_R_DMA_1_CH30 = 138,
|
||||
IMX_SC_R_DMA_1_CH31 = 139,
|
||||
IMX_SC_R_UNUSED1 = 140,
|
||||
IMX_SC_R_UNUSED2 = 141,
|
||||
IMX_SC_R_UNUSED3 = 142,
|
||||
IMX_SC_R_UNUSED4 = 143,
|
||||
IMX_SC_R_GPU_0_PID0 = 144,
|
||||
IMX_SC_R_GPU_0_PID1 = 145,
|
||||
IMX_SC_R_GPU_0_PID2 = 146,
|
||||
IMX_SC_R_GPU_0_PID3 = 147,
|
||||
IMX_SC_R_GPU_1_PID0 = 148,
|
||||
IMX_SC_R_GPU_1_PID1 = 149,
|
||||
IMX_SC_R_GPU_1_PID2 = 150,
|
||||
IMX_SC_R_GPU_1_PID3 = 151,
|
||||
IMX_SC_R_PCIE_A = 152,
|
||||
IMX_SC_R_SERDES_0 = 153,
|
||||
IMX_SC_R_MATCH_0 = 154,
|
||||
IMX_SC_R_MATCH_1 = 155,
|
||||
IMX_SC_R_MATCH_2 = 156,
|
||||
IMX_SC_R_MATCH_3 = 157,
|
||||
IMX_SC_R_MATCH_4 = 158,
|
||||
IMX_SC_R_MATCH_5 = 159,
|
||||
IMX_SC_R_MATCH_6 = 160,
|
||||
IMX_SC_R_MATCH_7 = 161,
|
||||
IMX_SC_R_MATCH_8 = 162,
|
||||
IMX_SC_R_MATCH_9 = 163,
|
||||
IMX_SC_R_MATCH_10 = 164,
|
||||
IMX_SC_R_MATCH_11 = 165,
|
||||
IMX_SC_R_MATCH_12 = 166,
|
||||
IMX_SC_R_MATCH_13 = 167,
|
||||
IMX_SC_R_MATCH_14 = 168,
|
||||
IMX_SC_R_PCIE_B = 169,
|
||||
IMX_SC_R_SATA_0 = 170,
|
||||
IMX_SC_R_SERDES_1 = 171,
|
||||
IMX_SC_R_HSIO_GPIO = 172,
|
||||
IMX_SC_R_MATCH_15 = 173,
|
||||
IMX_SC_R_MATCH_16 = 174,
|
||||
IMX_SC_R_MATCH_17 = 175,
|
||||
IMX_SC_R_MATCH_18 = 176,
|
||||
IMX_SC_R_MATCH_19 = 177,
|
||||
IMX_SC_R_MATCH_20 = 178,
|
||||
IMX_SC_R_MATCH_21 = 179,
|
||||
IMX_SC_R_MATCH_22 = 180,
|
||||
IMX_SC_R_MATCH_23 = 181,
|
||||
IMX_SC_R_MATCH_24 = 182,
|
||||
IMX_SC_R_MATCH_25 = 183,
|
||||
IMX_SC_R_MATCH_26 = 184,
|
||||
IMX_SC_R_MATCH_27 = 185,
|
||||
IMX_SC_R_MATCH_28 = 186,
|
||||
IMX_SC_R_LCD_0 = 187,
|
||||
IMX_SC_R_LCD_0_PWM_0 = 188,
|
||||
IMX_SC_R_LCD_0_I2C_0 = 189,
|
||||
IMX_SC_R_LCD_0_I2C_1 = 190,
|
||||
IMX_SC_R_PWM_0 = 191,
|
||||
IMX_SC_R_PWM_1 = 192,
|
||||
IMX_SC_R_PWM_2 = 193,
|
||||
IMX_SC_R_PWM_3 = 194,
|
||||
IMX_SC_R_PWM_4 = 195,
|
||||
IMX_SC_R_PWM_5 = 196,
|
||||
IMX_SC_R_PWM_6 = 197,
|
||||
IMX_SC_R_PWM_7 = 198,
|
||||
IMX_SC_R_GPIO_0 = 199,
|
||||
IMX_SC_R_GPIO_1 = 200,
|
||||
IMX_SC_R_GPIO_2 = 201,
|
||||
IMX_SC_R_GPIO_3 = 202,
|
||||
IMX_SC_R_GPIO_4 = 203,
|
||||
IMX_SC_R_GPIO_5 = 204,
|
||||
IMX_SC_R_GPIO_6 = 205,
|
||||
IMX_SC_R_GPIO_7 = 206,
|
||||
IMX_SC_R_GPT_0 = 207,
|
||||
IMX_SC_R_GPT_1 = 208,
|
||||
IMX_SC_R_GPT_2 = 209,
|
||||
IMX_SC_R_GPT_3 = 210,
|
||||
IMX_SC_R_GPT_4 = 211,
|
||||
IMX_SC_R_KPP = 212,
|
||||
IMX_SC_R_MU_0A = 213,
|
||||
IMX_SC_R_MU_1A = 214,
|
||||
IMX_SC_R_MU_2A = 215,
|
||||
IMX_SC_R_MU_3A = 216,
|
||||
IMX_SC_R_MU_4A = 217,
|
||||
IMX_SC_R_MU_5A = 218,
|
||||
IMX_SC_R_MU_6A = 219,
|
||||
IMX_SC_R_MU_7A = 220,
|
||||
IMX_SC_R_MU_8A = 221,
|
||||
IMX_SC_R_MU_9A = 222,
|
||||
IMX_SC_R_MU_10A = 223,
|
||||
IMX_SC_R_MU_11A = 224,
|
||||
IMX_SC_R_MU_12A = 225,
|
||||
IMX_SC_R_MU_13A = 226,
|
||||
IMX_SC_R_MU_5B = 227,
|
||||
IMX_SC_R_MU_6B = 228,
|
||||
IMX_SC_R_MU_7B = 229,
|
||||
IMX_SC_R_MU_8B = 230,
|
||||
IMX_SC_R_MU_9B = 231,
|
||||
IMX_SC_R_MU_10B = 232,
|
||||
IMX_SC_R_MU_11B = 233,
|
||||
IMX_SC_R_MU_12B = 234,
|
||||
IMX_SC_R_MU_13B = 235,
|
||||
IMX_SC_R_ROM_0 = 236,
|
||||
IMX_SC_R_FSPI_0 = 237,
|
||||
IMX_SC_R_FSPI_1 = 238,
|
||||
IMX_SC_R_IEE = 239,
|
||||
IMX_SC_R_IEE_R0 = 240,
|
||||
IMX_SC_R_IEE_R1 = 241,
|
||||
IMX_SC_R_IEE_R2 = 242,
|
||||
IMX_SC_R_IEE_R3 = 243,
|
||||
IMX_SC_R_IEE_R4 = 244,
|
||||
IMX_SC_R_IEE_R5 = 245,
|
||||
IMX_SC_R_IEE_R6 = 246,
|
||||
IMX_SC_R_IEE_R7 = 247,
|
||||
IMX_SC_R_SDHC_0 = 248,
|
||||
IMX_SC_R_SDHC_1 = 249,
|
||||
IMX_SC_R_SDHC_2 = 250,
|
||||
IMX_SC_R_ENET_0 = 251,
|
||||
IMX_SC_R_ENET_1 = 252,
|
||||
IMX_SC_R_MLB_0 = 253,
|
||||
IMX_SC_R_DMA_2_CH0 = 254,
|
||||
IMX_SC_R_DMA_2_CH1 = 255,
|
||||
IMX_SC_R_DMA_2_CH2 = 256,
|
||||
IMX_SC_R_DMA_2_CH3 = 257,
|
||||
IMX_SC_R_DMA_2_CH4 = 258,
|
||||
IMX_SC_R_USB_0 = 259,
|
||||
IMX_SC_R_USB_1 = 260,
|
||||
IMX_SC_R_USB_0_PHY = 261,
|
||||
IMX_SC_R_USB_2 = 262,
|
||||
IMX_SC_R_USB_2_PHY = 263,
|
||||
IMX_SC_R_DTCP = 264,
|
||||
IMX_SC_R_NAND = 265,
|
||||
IMX_SC_R_LVDS_0 = 266,
|
||||
IMX_SC_R_LVDS_0_PWM_0 = 267,
|
||||
IMX_SC_R_LVDS_0_I2C_0 = 268,
|
||||
IMX_SC_R_LVDS_0_I2C_1 = 269,
|
||||
IMX_SC_R_LVDS_1 = 270,
|
||||
IMX_SC_R_LVDS_1_PWM_0 = 271,
|
||||
IMX_SC_R_LVDS_1_I2C_0 = 272,
|
||||
IMX_SC_R_LVDS_1_I2C_1 = 273,
|
||||
IMX_SC_R_LVDS_2 = 274,
|
||||
IMX_SC_R_LVDS_2_PWM_0 = 275,
|
||||
IMX_SC_R_LVDS_2_I2C_0 = 276,
|
||||
IMX_SC_R_LVDS_2_I2C_1 = 277,
|
||||
IMX_SC_R_M4_0_PID0 = 278,
|
||||
IMX_SC_R_M4_0_PID1 = 279,
|
||||
IMX_SC_R_M4_0_PID2 = 280,
|
||||
IMX_SC_R_M4_0_PID3 = 281,
|
||||
IMX_SC_R_M4_0_PID4 = 282,
|
||||
IMX_SC_R_M4_0_RGPIO = 283,
|
||||
IMX_SC_R_M4_0_SEMA42 = 284,
|
||||
IMX_SC_R_M4_0_TPM = 285,
|
||||
IMX_SC_R_M4_0_PIT = 286,
|
||||
IMX_SC_R_M4_0_UART = 287,
|
||||
IMX_SC_R_M4_0_I2C = 288,
|
||||
IMX_SC_R_M4_0_INTMUX = 289,
|
||||
IMX_SC_R_M4_0_SIM = 290,
|
||||
IMX_SC_R_M4_0_WDOG = 291,
|
||||
IMX_SC_R_M4_0_MU_0B = 292,
|
||||
IMX_SC_R_M4_0_MU_0A0 = 293,
|
||||
IMX_SC_R_M4_0_MU_0A1 = 294,
|
||||
IMX_SC_R_M4_0_MU_0A2 = 295,
|
||||
IMX_SC_R_M4_0_MU_0A3 = 296,
|
||||
IMX_SC_R_M4_0_MU_1A = 297,
|
||||
IMX_SC_R_M4_1_PID0 = 298,
|
||||
IMX_SC_R_M4_1_PID1 = 299,
|
||||
IMX_SC_R_M4_1_PID2 = 300,
|
||||
IMX_SC_R_M4_1_PID3 = 301,
|
||||
IMX_SC_R_M4_1_PID4 = 302,
|
||||
IMX_SC_R_M4_1_RGPIO = 303,
|
||||
IMX_SC_R_M4_1_SEMA42 = 304,
|
||||
IMX_SC_R_M4_1_TPM = 305,
|
||||
IMX_SC_R_M4_1_PIT = 306,
|
||||
IMX_SC_R_M4_1_UART = 307,
|
||||
IMX_SC_R_M4_1_I2C = 308,
|
||||
IMX_SC_R_M4_1_INTMUX = 309,
|
||||
IMX_SC_R_M4_1_SIM = 310,
|
||||
IMX_SC_R_M4_1_WDOG = 311,
|
||||
IMX_SC_R_M4_1_MU_0B = 312,
|
||||
IMX_SC_R_M4_1_MU_0A0 = 313,
|
||||
IMX_SC_R_M4_1_MU_0A1 = 314,
|
||||
IMX_SC_R_M4_1_MU_0A2 = 315,
|
||||
IMX_SC_R_M4_1_MU_0A3 = 316,
|
||||
IMX_SC_R_M4_1_MU_1A = 317,
|
||||
IMX_SC_R_SAI_0 = 318,
|
||||
IMX_SC_R_SAI_1 = 319,
|
||||
IMX_SC_R_SAI_2 = 320,
|
||||
IMX_SC_R_IRQSTR_SCU2 = 321,
|
||||
IMX_SC_R_IRQSTR_DSP = 322,
|
||||
IMX_SC_R_UNUSED5 = 323,
|
||||
IMX_SC_R_UNUSED6 = 324,
|
||||
IMX_SC_R_AUDIO_PLL_0 = 325,
|
||||
IMX_SC_R_PI_0 = 326,
|
||||
IMX_SC_R_PI_0_PWM_0 = 327,
|
||||
IMX_SC_R_PI_0_PWM_1 = 328,
|
||||
IMX_SC_R_PI_0_I2C_0 = 329,
|
||||
IMX_SC_R_PI_0_PLL = 330,
|
||||
IMX_SC_R_PI_1 = 331,
|
||||
IMX_SC_R_PI_1_PWM_0 = 332,
|
||||
IMX_SC_R_PI_1_PWM_1 = 333,
|
||||
IMX_SC_R_PI_1_I2C_0 = 334,
|
||||
IMX_SC_R_PI_1_PLL = 335,
|
||||
IMX_SC_R_SC_PID0 = 336,
|
||||
IMX_SC_R_SC_PID1 = 337,
|
||||
IMX_SC_R_SC_PID2 = 338,
|
||||
IMX_SC_R_SC_PID3 = 339,
|
||||
IMX_SC_R_SC_PID4 = 340,
|
||||
IMX_SC_R_SC_SEMA42 = 341,
|
||||
IMX_SC_R_SC_TPM = 342,
|
||||
IMX_SC_R_SC_PIT = 343,
|
||||
IMX_SC_R_SC_UART = 344,
|
||||
IMX_SC_R_SC_I2C = 345,
|
||||
IMX_SC_R_SC_MU_0B = 346,
|
||||
IMX_SC_R_SC_MU_0A0 = 347,
|
||||
IMX_SC_R_SC_MU_0A1 = 348,
|
||||
IMX_SC_R_SC_MU_0A2 = 349,
|
||||
IMX_SC_R_SC_MU_0A3 = 350,
|
||||
IMX_SC_R_SC_MU_1A = 351,
|
||||
IMX_SC_R_SYSCNT_RD = 352,
|
||||
IMX_SC_R_SYSCNT_CMP = 353,
|
||||
IMX_SC_R_DEBUG = 354,
|
||||
IMX_SC_R_SYSTEM = 355,
|
||||
IMX_SC_R_SNVS = 356,
|
||||
IMX_SC_R_OTP = 357,
|
||||
IMX_SC_R_VPU_PID0 = 358,
|
||||
IMX_SC_R_VPU_PID1 = 359,
|
||||
IMX_SC_R_VPU_PID2 = 360,
|
||||
IMX_SC_R_VPU_PID3 = 361,
|
||||
IMX_SC_R_VPU_PID4 = 362,
|
||||
IMX_SC_R_VPU_PID5 = 363,
|
||||
IMX_SC_R_VPU_PID6 = 364,
|
||||
IMX_SC_R_VPU_PID7 = 365,
|
||||
IMX_SC_R_VPU_UART = 366,
|
||||
IMX_SC_R_VPUCORE = 367,
|
||||
IMX_SC_R_VPUCORE_0 = 368,
|
||||
IMX_SC_R_VPUCORE_1 = 369,
|
||||
IMX_SC_R_VPUCORE_2 = 370,
|
||||
IMX_SC_R_VPUCORE_3 = 371,
|
||||
IMX_SC_R_DMA_4_CH0 = 372,
|
||||
IMX_SC_R_DMA_4_CH1 = 373,
|
||||
IMX_SC_R_DMA_4_CH2 = 374,
|
||||
IMX_SC_R_DMA_4_CH3 = 375,
|
||||
IMX_SC_R_DMA_4_CH4 = 376,
|
||||
IMX_SC_R_ISI_CH0 = 377,
|
||||
IMX_SC_R_ISI_CH1 = 378,
|
||||
IMX_SC_R_ISI_CH2 = 379,
|
||||
IMX_SC_R_ISI_CH3 = 380,
|
||||
IMX_SC_R_ISI_CH4 = 381,
|
||||
IMX_SC_R_ISI_CH5 = 382,
|
||||
IMX_SC_R_ISI_CH6 = 383,
|
||||
IMX_SC_R_ISI_CH7 = 384,
|
||||
IMX_SC_R_MJPEG_DEC_S0 = 385,
|
||||
IMX_SC_R_MJPEG_DEC_S1 = 386,
|
||||
IMX_SC_R_MJPEG_DEC_S2 = 387,
|
||||
IMX_SC_R_MJPEG_DEC_S3 = 388,
|
||||
IMX_SC_R_MJPEG_ENC_S0 = 389,
|
||||
IMX_SC_R_MJPEG_ENC_S1 = 390,
|
||||
IMX_SC_R_MJPEG_ENC_S2 = 391,
|
||||
IMX_SC_R_MJPEG_ENC_S3 = 392,
|
||||
IMX_SC_R_MIPI_0 = 393,
|
||||
IMX_SC_R_MIPI_0_PWM_0 = 394,
|
||||
IMX_SC_R_MIPI_0_I2C_0 = 395,
|
||||
IMX_SC_R_MIPI_0_I2C_1 = 396,
|
||||
IMX_SC_R_MIPI_1 = 397,
|
||||
IMX_SC_R_MIPI_1_PWM_0 = 398,
|
||||
IMX_SC_R_MIPI_1_I2C_0 = 399,
|
||||
IMX_SC_R_MIPI_1_I2C_1 = 400,
|
||||
IMX_SC_R_CSI_0 = 401,
|
||||
IMX_SC_R_CSI_0_PWM_0 = 402,
|
||||
IMX_SC_R_CSI_0_I2C_0 = 403,
|
||||
IMX_SC_R_CSI_1 = 404,
|
||||
IMX_SC_R_CSI_1_PWM_0 = 405,
|
||||
IMX_SC_R_CSI_1_I2C_0 = 406,
|
||||
IMX_SC_R_HDMI = 407,
|
||||
IMX_SC_R_HDMI_I2S = 408,
|
||||
IMX_SC_R_HDMI_I2C_0 = 409,
|
||||
IMX_SC_R_HDMI_PLL_0 = 410,
|
||||
IMX_SC_R_HDMI_RX = 411,
|
||||
IMX_SC_R_HDMI_RX_BYPASS = 412,
|
||||
IMX_SC_R_HDMI_RX_I2C_0 = 413,
|
||||
IMX_SC_R_ASRC_0 = 414,
|
||||
IMX_SC_R_ESAI_0 = 415,
|
||||
IMX_SC_R_SPDIF_0 = 416,
|
||||
IMX_SC_R_SPDIF_1 = 417,
|
||||
IMX_SC_R_SAI_3 = 418,
|
||||
IMX_SC_R_SAI_4 = 419,
|
||||
IMX_SC_R_SAI_5 = 420,
|
||||
IMX_SC_R_GPT_5 = 421,
|
||||
IMX_SC_R_GPT_6 = 422,
|
||||
IMX_SC_R_GPT_7 = 423,
|
||||
IMX_SC_R_GPT_8 = 424,
|
||||
IMX_SC_R_GPT_9 = 425,
|
||||
IMX_SC_R_GPT_10 = 426,
|
||||
IMX_SC_R_DMA_2_CH5 = 427,
|
||||
IMX_SC_R_DMA_2_CH6 = 428,
|
||||
IMX_SC_R_DMA_2_CH7 = 429,
|
||||
IMX_SC_R_DMA_2_CH8 = 430,
|
||||
IMX_SC_R_DMA_2_CH9 = 431,
|
||||
IMX_SC_R_DMA_2_CH10 = 432,
|
||||
IMX_SC_R_DMA_2_CH11 = 433,
|
||||
IMX_SC_R_DMA_2_CH12 = 434,
|
||||
IMX_SC_R_DMA_2_CH13 = 435,
|
||||
IMX_SC_R_DMA_2_CH14 = 436,
|
||||
IMX_SC_R_DMA_2_CH15 = 437,
|
||||
IMX_SC_R_DMA_2_CH16 = 438,
|
||||
IMX_SC_R_DMA_2_CH17 = 439,
|
||||
IMX_SC_R_DMA_2_CH18 = 440,
|
||||
IMX_SC_R_DMA_2_CH19 = 441,
|
||||
IMX_SC_R_DMA_2_CH20 = 442,
|
||||
IMX_SC_R_DMA_2_CH21 = 443,
|
||||
IMX_SC_R_DMA_2_CH22 = 444,
|
||||
IMX_SC_R_DMA_2_CH23 = 445,
|
||||
IMX_SC_R_DMA_2_CH24 = 446,
|
||||
IMX_SC_R_DMA_2_CH25 = 447,
|
||||
IMX_SC_R_DMA_2_CH26 = 448,
|
||||
IMX_SC_R_DMA_2_CH27 = 449,
|
||||
IMX_SC_R_DMA_2_CH28 = 450,
|
||||
IMX_SC_R_DMA_2_CH29 = 451,
|
||||
IMX_SC_R_DMA_2_CH30 = 452,
|
||||
IMX_SC_R_DMA_2_CH31 = 453,
|
||||
IMX_SC_R_ASRC_1 = 454,
|
||||
IMX_SC_R_ESAI_1 = 455,
|
||||
IMX_SC_R_SAI_6 = 456,
|
||||
IMX_SC_R_SAI_7 = 457,
|
||||
IMX_SC_R_AMIX = 458,
|
||||
IMX_SC_R_MQS_0 = 459,
|
||||
IMX_SC_R_DMA_3_CH0 = 460,
|
||||
IMX_SC_R_DMA_3_CH1 = 461,
|
||||
IMX_SC_R_DMA_3_CH2 = 462,
|
||||
IMX_SC_R_DMA_3_CH3 = 463,
|
||||
IMX_SC_R_DMA_3_CH4 = 464,
|
||||
IMX_SC_R_DMA_3_CH5 = 465,
|
||||
IMX_SC_R_DMA_3_CH6 = 466,
|
||||
IMX_SC_R_DMA_3_CH7 = 467,
|
||||
IMX_SC_R_DMA_3_CH8 = 468,
|
||||
IMX_SC_R_DMA_3_CH9 = 469,
|
||||
IMX_SC_R_DMA_3_CH10 = 470,
|
||||
IMX_SC_R_DMA_3_CH11 = 471,
|
||||
IMX_SC_R_DMA_3_CH12 = 472,
|
||||
IMX_SC_R_DMA_3_CH13 = 473,
|
||||
IMX_SC_R_DMA_3_CH14 = 474,
|
||||
IMX_SC_R_DMA_3_CH15 = 475,
|
||||
IMX_SC_R_DMA_3_CH16 = 476,
|
||||
IMX_SC_R_DMA_3_CH17 = 477,
|
||||
IMX_SC_R_DMA_3_CH18 = 478,
|
||||
IMX_SC_R_DMA_3_CH19 = 479,
|
||||
IMX_SC_R_DMA_3_CH20 = 480,
|
||||
IMX_SC_R_DMA_3_CH21 = 481,
|
||||
IMX_SC_R_DMA_3_CH22 = 482,
|
||||
IMX_SC_R_DMA_3_CH23 = 483,
|
||||
IMX_SC_R_DMA_3_CH24 = 484,
|
||||
IMX_SC_R_DMA_3_CH25 = 485,
|
||||
IMX_SC_R_DMA_3_CH26 = 486,
|
||||
IMX_SC_R_DMA_3_CH27 = 487,
|
||||
IMX_SC_R_DMA_3_CH28 = 488,
|
||||
IMX_SC_R_DMA_3_CH29 = 489,
|
||||
IMX_SC_R_DMA_3_CH30 = 490,
|
||||
IMX_SC_R_DMA_3_CH31 = 491,
|
||||
IMX_SC_R_AUDIO_PLL_1 = 492,
|
||||
IMX_SC_R_AUDIO_CLK_0 = 493,
|
||||
IMX_SC_R_AUDIO_CLK_1 = 494,
|
||||
IMX_SC_R_MCLK_OUT_0 = 495,
|
||||
IMX_SC_R_MCLK_OUT_1 = 496,
|
||||
IMX_SC_R_PMIC_0 = 497,
|
||||
IMX_SC_R_PMIC_1 = 498,
|
||||
IMX_SC_R_SECO = 499,
|
||||
IMX_SC_R_CAAM_JR1 = 500,
|
||||
IMX_SC_R_CAAM_JR2 = 501,
|
||||
IMX_SC_R_CAAM_JR3 = 502,
|
||||
IMX_SC_R_SECO_MU_2 = 503,
|
||||
IMX_SC_R_SECO_MU_3 = 504,
|
||||
IMX_SC_R_SECO_MU_4 = 505,
|
||||
IMX_SC_R_HDMI_RX_PWM_0 = 506,
|
||||
IMX_SC_R_A35 = 507,
|
||||
IMX_SC_R_A35_0 = 508,
|
||||
IMX_SC_R_A35_1 = 509,
|
||||
IMX_SC_R_A35_2 = 510,
|
||||
IMX_SC_R_A35_3 = 511,
|
||||
IMX_SC_R_DSP = 512,
|
||||
IMX_SC_R_DSP_RAM = 513,
|
||||
IMX_SC_R_CAAM_JR1_OUT = 514,
|
||||
IMX_SC_R_CAAM_JR2_OUT = 515,
|
||||
IMX_SC_R_CAAM_JR3_OUT = 516,
|
||||
IMX_SC_R_VPU_DEC_0 = 517,
|
||||
IMX_SC_R_VPU_ENC_0 = 518,
|
||||
IMX_SC_R_CAAM_JR0 = 519,
|
||||
IMX_SC_R_CAAM_JR0_OUT = 520,
|
||||
IMX_SC_R_PMIC_2 = 521,
|
||||
IMX_SC_R_DBLOGIC = 522,
|
||||
IMX_SC_R_HDMI_PLL_1 = 523,
|
||||
IMX_SC_R_BOARD_R0 = 524,
|
||||
IMX_SC_R_BOARD_R1 = 525,
|
||||
IMX_SC_R_BOARD_R2 = 526,
|
||||
IMX_SC_R_BOARD_R3 = 527,
|
||||
IMX_SC_R_BOARD_R4 = 528,
|
||||
IMX_SC_R_BOARD_R5 = 529,
|
||||
IMX_SC_R_BOARD_R6 = 530,
|
||||
IMX_SC_R_BOARD_R7 = 531,
|
||||
IMX_SC_R_MJPEG_DEC_MP = 532,
|
||||
IMX_SC_R_MJPEG_ENC_MP = 533,
|
||||
IMX_SC_R_VPU_TS_0 = 534,
|
||||
IMX_SC_R_VPU_MU_0 = 535,
|
||||
IMX_SC_R_VPU_MU_1 = 536,
|
||||
IMX_SC_R_VPU_MU_2 = 537,
|
||||
IMX_SC_R_VPU_MU_3 = 538,
|
||||
IMX_SC_R_VPU_ENC_1 = 539,
|
||||
IMX_SC_R_VPU = 540,
|
||||
IMX_SC_R_LAST
|
||||
};
|
||||
|
||||
/* NOTE - please add by replacing some of the UNUSED from above! */
|
||||
|
||||
/*
|
||||
* This type is used to indicate a control.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue