drm/radeon/dpm: fix UVD clock setting on SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -5883,7 +5883,7 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
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}
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if (eg_pi->pcie_performance_request)
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si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
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rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
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ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
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ret = si_enable_power_containment(rdev, new_ps, false);
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if (ret) {
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DRM_ERROR("si_enable_power_containment failed\n");
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@ -5948,7 +5948,7 @@ int si_dpm_set_power_state(struct radeon_device *rdev)
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DRM_ERROR("si_set_sw_state failed\n");
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return ret;
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}
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rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
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ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
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if (eg_pi->pcie_performance_request)
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si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
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ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
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