spi: bcm2835: move to the transfer_one driver model
This also allows for GPIO-CS to get used removing the limitation of
2/3 SPI devises on the SPI bus.
Fixes: spi-cs-high with native CS with multiple devices on the spi-bus
resetting the chip selects to "normal" polarity after a finished
transfer.
No other functionality/improvements added.
Tested with the following 4 devices on the spi-bus:
* mcp2515 with native CS
* mcp2515 with gpio CS
* fb_st7735r with native CS
(plus spi-cs-high via transistor inverting polarity)
* enc28j60 with gpio-CS
Tested-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
hifive-unleashed-5.1
Martin Sperl
Mark Brown
parent
1be38e041f
commit
e34ff011c7
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2012 Chris Boot
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* Copyright (C) 2013 Stephen Warren
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* Copyright (C) 2015 Martin Sperl
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*
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* This driver is inspired by:
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* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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@ -29,6 +30,7 @@
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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@ -76,10 +78,10 @@ struct bcm2835_spi {
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void __iomem *regs;
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struct clk *clk;
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int irq;
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struct completion done;
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const u8 *tx_buf;
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u8 *rx_buf;
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int len;
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int tx_len;
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int rx_len;
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};
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static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
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@ -96,10 +98,12 @@ static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
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{
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u8 byte;
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while (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD) {
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while ((bs->rx_len) &&
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
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byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
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if (bs->rx_buf)
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*bs->rx_buf++ = byte;
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bs->rx_len--;
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}
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}
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@ -107,47 +111,60 @@ static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
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{
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u8 byte;
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while ((bs->len) &&
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while ((bs->tx_len) &&
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
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byte = bs->tx_buf ? *bs->tx_buf++ : 0;
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bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
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bs->len--;
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bs->tx_len--;
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}
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}
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static void bcm2835_spi_reset_hw(struct spi_master *master)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/* Disable SPI interrupts and transfer */
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cs &= ~(BCM2835_SPI_CS_INTR |
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BCM2835_SPI_CS_INTD |
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BCM2835_SPI_CS_TA);
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/* and reset RX/TX FIFOS */
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cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
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/* and reset the SPI_HW */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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}
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static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/* Read as many bytes as possible from FIFO */
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bcm2835_rd_fifo(bs);
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/* Write as many bytes as possible to FIFO */
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bcm2835_wr_fifo(bs);
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if (bs->len) { /* there is more data to transmit */
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bcm2835_wr_fifo(bs);
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} else { /* Transfer complete */
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/* Disable SPI interrupts */
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cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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/*
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* Wake up bcm2835_spi_transfer_one(), which will call
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* bcm2835_spi_finish_transfer(), to drain the RX FIFO.
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*/
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complete(&bs->done);
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/* based on flags decide if we can finish the transfer */
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if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
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/* Transfer complete - reset SPI HW */
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bcm2835_spi_reset_hw(master);
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/* wake up the framework */
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complete(&master->xfer_completion);
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}
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return IRQ_HANDLED;
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}
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static int bcm2835_spi_start_transfer(struct spi_device *spi,
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struct spi_transfer *tfr)
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static int bcm2835_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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unsigned long spi_hz, clk_hz, cdiv;
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u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/* set clock */
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spi_hz = tfr->speed_hz;
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clk_hz = clk_get_rate(bs->clk);
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@ -163,100 +180,118 @@ static int bcm2835_spi_start_transfer(struct spi_device *spi,
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} else {
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cdiv = 0; /* 0 is the slowest we can go */
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}
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bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
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/* handle all the modes */
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if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
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cs |= BCM2835_SPI_CS_REN;
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if (spi->mode & SPI_CPOL)
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cs |= BCM2835_SPI_CS_CPOL;
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if (spi->mode & SPI_CPHA)
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cs |= BCM2835_SPI_CS_CPHA;
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if (!(spi->mode & SPI_NO_CS)) {
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if (spi->mode & SPI_CS_HIGH) {
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cs |= BCM2835_SPI_CS_CSPOL;
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cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
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}
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/* for gpio_cs set dummy CS so that no HW-CS get changed
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* we can not run this in bcm2835_spi_set_cs, as it does
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* not get called for cs_gpio cases, so we need to do it here
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*/
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if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
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cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
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cs |= spi->chip_select;
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}
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reinit_completion(&bs->done);
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/* set transmit buffers and length */
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bs->tx_buf = tfr->tx_buf;
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bs->rx_buf = tfr->rx_buf;
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bs->len = tfr->len;
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bs->tx_len = tfr->len;
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bs->rx_len = tfr->len;
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bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
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/*
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* Enable the HW block. This will immediately trigger a DONE (TX
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* empty) interrupt, upon which we will fill the TX FIFO with the
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* first TX bytes. Pre-filling the TX FIFO here to avoid the
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* interrupt doesn't work:-(
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*/
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cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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return 0;
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/* signal that we need to wait for completion */
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return 1;
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}
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static int bcm2835_spi_finish_transfer(struct spi_device *spi,
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struct spi_transfer *tfr,
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bool cs_change)
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static void bcm2835_spi_handle_err(struct spi_master *master,
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struct spi_message *msg)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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if (tfr->delay_usecs)
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udelay(tfr->delay_usecs);
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if (cs_change)
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/* Clear TA flag */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
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return 0;
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bcm2835_spi_reset_hw(master);
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}
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static int bcm2835_spi_transfer_one(struct spi_master *master,
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struct spi_message *mesg)
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static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
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{
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/*
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* we can assume that we are "native" as per spi_set_cs
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* calling us ONLY when cs_gpio is not set
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* we can also assume that we are CS < 3 as per bcm2835_spi_setup
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* we would not get called because of error handling there.
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* the level passed is the electrical level not enabled/disabled
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* so it has to get translated back to enable/disable
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* see spi_set_cs in spi.c for the implementation
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*/
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struct spi_master *master = spi->master;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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struct spi_transfer *tfr;
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struct spi_device *spi = mesg->spi;
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int err = 0;
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unsigned int timeout;
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bool cs_change;
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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bool enable;
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list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
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err = bcm2835_spi_start_transfer(spi, tfr);
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if (err)
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goto out;
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/* calculate the enable flag from the passed gpio_level */
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enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
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timeout = wait_for_completion_timeout(
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&bs->done,
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msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS)
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);
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if (!timeout) {
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err = -ETIMEDOUT;
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goto out;
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}
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cs_change = tfr->cs_change ||
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list_is_last(&tfr->transfer_list, &mesg->transfers);
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err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
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if (err)
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goto out;
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mesg->actual_length += (tfr->len - bs->len);
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/* set flags for "reverse" polarity in the registers */
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if (spi->mode & SPI_CS_HIGH) {
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/* set the correct CS-bits */
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cs |= BCM2835_SPI_CS_CSPOL;
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cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
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} else {
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/* clean the CS-bits */
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cs &= ~BCM2835_SPI_CS_CSPOL;
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cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
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}
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out:
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/* Clear FIFOs, and disable the HW block */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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mesg->status = err;
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spi_finalize_current_message(master);
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/* select the correct chip_select depending on disabled/enabled */
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if (enable) {
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/* set cs correctly */
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if (spi->mode & SPI_NO_CS) {
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/* use the "undefined" chip-select */
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cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
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} else {
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/* set the chip select */
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cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
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cs |= spi->chip_select;
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}
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} else {
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/* disable CSPOL which puts HW-CS into deselected state */
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cs &= ~BCM2835_SPI_CS_CSPOL;
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/* use the "undefined" chip-select as precaution */
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cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
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}
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return 0;
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/* finally set the calculated flags in SPI_CS */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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}
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static int bcm2835_spi_setup(struct spi_device *spi)
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{
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/*
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* sanity checking the native-chipselects
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*/
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if (spi->mode & SPI_NO_CS)
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return 0;
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if (gpio_is_valid(spi->cs_gpio))
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return 0;
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if (spi->chip_select < 3)
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return 0;
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/* error in the case of native CS requested with CS-id > 2 */
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dev_err(&spi->dev,
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"setup: only three native chip-selects are supported\n"
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);
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return -EINVAL;
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}
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static int bcm2835_spi_probe(struct platform_device *pdev)
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@ -277,13 +312,14 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
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master->mode_bits = BCM2835_SPI_MODE_BITS;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->num_chipselect = 3;
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master->transfer_one_message = bcm2835_spi_transfer_one;
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master->setup = bcm2835_spi_setup;
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master->set_cs = bcm2835_spi_set_cs;
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master->transfer_one = bcm2835_spi_transfer_one;
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master->handle_err = bcm2835_spi_handle_err;
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master->dev.of_node = pdev->dev.of_node;
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bs = spi_master_get_devdata(master);
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init_completion(&bs->done);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bs->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(bs->regs)) {
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@ -314,7 +350,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
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goto out_clk_disable;
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}
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/* initialise the hardware */
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/* initialise the hardware with the default polarities */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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