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ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices 

Although RESET state of LIMITEDADDRESS bit in GPMC_CONFIG register
is 0 (i.e. A26-A11 enabled), faulty bootloaders might accidentally
set this bit. e.g. u-boot 2014.07 with CONFIG_NOR disabled.

Explicity disable LIMITEDADDRESS bit for non NAND devices so that
they can always work.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
hifive-unleashed-5.1
Roger Quadros 2014-08-29 19:11:52 +03:00
parent 7604baf365
commit e378d22b9c
1 changed files with 8 additions and 0 deletions
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8
arch/arm/mach-omap2/gpmc.c
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@ -85,6 +85,8 @@
#define GPMC_ECC_CTRL_ECCREG8 0x008
#define GPMC_ECC_CTRL_ECCREG9 0x009
#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
@ -1501,6 +1503,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
struct resource res;
unsigned long base;
int ret, cs;
u32 val;
if (of_property_read_u32(child, "reg", &cs) < 0) {
dev_err(&pdev->dev, "%s has no 'reg' property\n",
@ -1569,6 +1572,11 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
goto err;
}
/* Clear limited address i.e. enable A26-A11 */
val = gpmc_read_reg(GPMC_CONFIG);
val &= ~GPMC_CONFIG_LIMITEDADDRESS;
gpmc_write_reg(GPMC_CONFIG, val);
no_timings:
if (of_platform_device_create(child, NULL, &pdev->dev))
return 0;