pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs
[ Upstream commit 02aeb2f215
]
pinmux_func_gpios[] contains a hole due to the missing function GPIO
definition for the "CTX0&CTX1" signal, which is the logical "AND" of the
first two CAN outputs.
A closer look reveals other issues:
- Some functionality is available on alternative pins, but the
PINMUX_DATA() entries is using the wrong marks,
- Several configurations are missing.
Fix this by:
- Renaming CTX0CTX1CTX2_MARK, CRX0CRX1_PJ22_MARK, and
CRX0CRX1CRX2_PJ20_MARK to CTX0_CTX1_CTX2_MARK, CRX0_CRX1_PJ22_MARK,
resp. CRX0_CRX1_CRX2_PJ20_MARK for consistency with the
corresponding enum IDs,
- Adding all missing enum IDs and marks,
- Use the right (*_PJ2x) variants for alternative pins,
- Adding all missing configurations to pinmux_data[],
- Adding all missing function GPIO definitions to pinmux_func_gpios[].
See SH7268 Group, SH7269 Group User’s Manual: Hardware, Rev. 2.00:
[1] Table 1.4 List of Pins
[2] Figure 23.29 Connection Example when Using Channels 0 and 1 as One
Channel (64 Mailboxes × 1 Channel) and Channel 2 as One Channel
(32 Mailboxes × 1 Channel),
[3] Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as
One Channel (96 Mailboxes × 1 Channel),
[4] Table 48.3 Multiplexed Pins (Port B),
[5] Table 48.4 Multiplexed Pins (Port C),
[6] Table 48.10 Multiplexed Pins (Port J),
[7] Section 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-5-geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>
5.4-rM2-2.2.x-imx-squashed
parent
9ed7329798
commit
e39aac0e65
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@ -78,8 +78,15 @@ enum {
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GPIO_FN_WDTOVF,
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/* CAN */
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GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
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GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
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GPIO_FN_CTX2, GPIO_FN_CRX2,
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GPIO_FN_CTX1, GPIO_FN_CRX1,
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GPIO_FN_CTX0, GPIO_FN_CRX0,
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GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1,
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GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2,
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GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20,
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GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22,
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GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22,
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GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20,
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/* DMAC */
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GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
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@ -737,13 +737,12 @@ enum {
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CRX0_MARK, CTX0_MARK,
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CRX1_MARK, CTX1_MARK,
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CRX2_MARK, CTX2_MARK,
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CRX0_CRX1_MARK,
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CRX0_CRX1_CRX2_MARK,
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CTX0CTX1CTX2_MARK,
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CRX0_CRX1_MARK, CTX0_CTX1_MARK,
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CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK,
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CRX1_PJ22_MARK, CTX1_PJ23_MARK,
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CRX2_PJ20_MARK, CTX2_PJ21_MARK,
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CRX0CRX1_PJ22_MARK,
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CRX0CRX1CRX2_PJ20_MARK,
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CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK,
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CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK,
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/* VDC */
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DV_CLK_MARK,
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@ -821,6 +820,7 @@ static const u16 pinmux_data[] = {
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PINMUX_DATA(CS3_MARK, PC8MD_001),
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PINMUX_DATA(TXD7_MARK, PC8MD_010),
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PINMUX_DATA(CTX1_MARK, PC8MD_011),
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PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100),
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PINMUX_DATA(PC7_DATA, PC7MD_000),
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PINMUX_DATA(CKE_MARK, PC7MD_001),
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@ -833,11 +833,12 @@ static const u16 pinmux_data[] = {
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PINMUX_DATA(CAS_MARK, PC6MD_001),
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PINMUX_DATA(SCK7_MARK, PC6MD_010),
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PINMUX_DATA(CTX0_MARK, PC6MD_011),
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PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100),
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PINMUX_DATA(PC5_DATA, PC5MD_000),
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PINMUX_DATA(RAS_MARK, PC5MD_001),
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PINMUX_DATA(CRX0_MARK, PC5MD_011),
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PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100),
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PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100),
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PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),
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PINMUX_DATA(PC4_DATA, PC4MD_00),
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@ -1289,30 +1290,32 @@ static const u16 pinmux_data[] = {
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PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),
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PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
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PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
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PINMUX_DATA(CTX1_MARK, PJ23MD_101),
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PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101),
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PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110),
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PINMUX_DATA(PJ22_DATA, PJ22MD_000),
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PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
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PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),
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PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
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PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
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PINMUX_DATA(CRX1_MARK, PJ22MD_101),
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PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110),
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PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101),
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PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110),
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PINMUX_DATA(PJ21_DATA, PJ21MD_000),
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PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
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PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),
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PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
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PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
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PINMUX_DATA(CTX2_MARK, PJ21MD_101),
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PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101),
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PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110),
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PINMUX_DATA(PJ20_DATA, PJ20MD_000),
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PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
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PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),
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PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
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PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
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PINMUX_DATA(CRX2_MARK, PJ20MD_101),
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PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110),
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PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101),
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PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110),
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PINMUX_DATA(PJ19_DATA, PJ19MD_000),
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PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
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@ -1663,12 +1666,24 @@ static const struct pinmux_func pinmux_func_gpios[] = {
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GPIO_FN(WDTOVF),
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/* CAN */
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GPIO_FN(CTX2),
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GPIO_FN(CRX2),
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GPIO_FN(CTX1),
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GPIO_FN(CRX1),
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GPIO_FN(CTX0),
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GPIO_FN(CRX0),
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GPIO_FN(CTX0_CTX1),
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GPIO_FN(CRX0_CRX1),
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GPIO_FN(CTX0_CTX1_CTX2),
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GPIO_FN(CRX0_CRX1_CRX2),
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GPIO_FN(CTX2_PJ21),
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GPIO_FN(CRX2_PJ20),
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GPIO_FN(CTX1_PJ23),
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GPIO_FN(CRX1_PJ22),
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GPIO_FN(CTX0_CTX1_PJ23),
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GPIO_FN(CRX0_CRX1_PJ22),
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GPIO_FN(CTX0_CTX1_CTX2_PJ21),
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GPIO_FN(CRX0_CRX1_CRX2_PJ20),
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/* DMAC */
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GPIO_FN(TEND0),
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