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Devicetree updates for v5.4: 

- A bunch of DT binding conversions to DT schema format
 
 - Clean-ups of the Arm idle-states binding
 
 - Support a default number of cells in of_for_each_phandle() when the
   cells name is missing
 
 - Expose dtbs_check and dt_binding_check in the make help
 
 - Convert writting-schema.md to ReST
 
 - HiSilicon reset controller binding updates
 
 - Add documentation for MT8516 RNG
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Merge tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull Devicetree updates from Rob Herring:

 - a bunch of DT binding conversions to DT schema format

 - clean-ups of the Arm idle-states binding

 - support a default number of cells in of_for_each_phandle() when the
   cells name is missing

 - expose dtbs_check and dt_binding_check in the make help

 - convert writting-schema.md to ReST

 - HiSilicon reset controller binding updates

 - add documentation for MT8516 RNG

* tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
  of: restore old handling of cells_name=NULL in of_*_phandle_with_args()
  bus: qcom: fix spelling mistake "ambigous" -> "ambiguous"
  of: Let of_for_each_phandle fallback to non-negative cell_count
  iommu: pass cell_count = -1 to of_for_each_phandle with cells_name
  dt-bindings: arm: Convert Realtek board/soc bindings to json-schema
  dt-bindings: arm: Convert Actions Semi bindings to jsonschema
  dt-bindings: Correct spelling in example schema
  dt-bindings: cpu: Add a support cpu type for cortex-a55
  dt-bindings: gpu: mali-midgard: Add samsung exynos5250 compatible
  dt-bindings: arm: idle-states: Move exit-latency-us explanation
  dt-bindings: arm: idle-states: Add punctuation to improve readability
  dt-bindings: arm: idle-states: Correct "constraint guarantees"
  dt-bindings: arm: idle-states: Correct references to wake-up delay
  dt-bindings: arm: idle-states: Use "e.g." and "i.e." consistently
  pinctrl-mcp23s08: Fix property-name in dt-example
  dt-bindings: Clarify interrupts-extended usage
  dt-bindings: Convert Arm Mali Utgard GPU to DT schema
  dt-bindings: Convert Arm Mali Bifrost GPU to DT schema
  dt-bindings: Convert Arm Mali Midgard GPU to DT schema
  dt-bindings: irq: Convert Allwinner NMI Controller to a schema
  ...
alistair/sunxi64-5.4-dsi
Linus Torvalds 2019-09-19 13:48:37 -07:00
parent 671df18953 59e9fcf877
commit e3a008ac12
60 changed files with 1522 additions and 892 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
Documentation/devicetree/bindings/arm/actions.txt
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@ -1,56 +0,0 @@
Actions Semi platforms device tree bindings
-------------------------------------------
S500 SoC
========
Required root node properties:
- compatible : must contain "actions,s500"
Modules:
Root node property compatible must contain, depending on module:
- LeMaker Guitar: "lemaker,guitar"
Boards:
Root node property compatible must contain, depending on board:
- Allo.com Sparky: "allo,sparky"
- Cubietech CubieBoard6: "cubietech,cubieboard6"
- LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
S700 SoC
========
Required root node properties:
- compatible : must contain "actions,s700"
Boards:
Root node property compatible must contain, depending on board:
- Cubietech CubieBoard7: "cubietech,cubieboard7"
S900 SoC
========
Required root node properties:
- compatible : must contain "actions,s900"
Boards:
Root node property compatible must contain, depending on board:
- uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96"

38
Documentation/devicetree/bindings/arm/actions.yaml 100644
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@ -0,0 +1,38 @@
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/actions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi platforms device tree bindings
maintainers:
- Andreas Färber <afaerber@suse.de>
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
compatible:
oneOf:
# The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
- items:
- enum:
- allo,sparky # Allo.com Sparky
- cubietech,cubieboard6 # Cubietech CubieBoard6
- const: actions,s500
- items:
- enum:
- lemaker,guitar-bb-rev-b # LeMaker Guitar Base Board rev. B
- const: lemaker,guitar
- const: actions,s500
# The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC.
- items:
- enum:
- cubietech,cubieboard7 # Cubietech CubieBoard7
- const: actions,s700
# The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
- items:
- enum:
- ucrobotics,bubblegum-96 # uCRobotics Bubblegum-96
- const: actions,s900

28
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
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@ -1,28 +0,0 @@
Amlogic Meson Firmware registers Interface
------------------------------------------
The Meson SoCs have a register bank with status and data shared with the
secure firmware.
Required properties:
- compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
Properties should indentify components of this register interface :
Meson GX SoC Information
------------------------
A firmware register encodes the SoC type, package and revision information on
the Meson GX SoCs.
If present, the following property should be added :
Optional properties:
- amlogic,has-chip-id: If present, the interface gives the current SoC version.
Example
-------
ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x0 0x140 0x0 0x140>;
amlogic,has-chip-id;
};

52
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml 100644
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson Firmware registers Interface
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
description: |
The Meson SoCs have a register bank with status and data shared with the
secure firmware.
# We need a select here so we don't match all nodes with 'syscon'
select:
properties:
compatible:
contains:
const: amlogic,meson-gx-ao-secure
required:
- compatible
properties:
compatible:
items:
- const: amlogic,meson-gx-ao-secure
- const: syscon
reg:
maxItems: 1
amlogic,has-chip-id:
description: |
A firmware register encodes the SoC type, package and revision
information on the Meson GX SoCs. If present, the interface gives
the current SoC version.
type: boolean
required:
- compatible
- reg
examples:
- |
ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x140 0x140>;
amlogic,has-chip-id;
};

2
Documentation/devicetree/bindings/arm/arm-boards
View File

@ -199,7 +199,7 @@ The description for the board must include:
A detailed description of the bindings used for "psci" nodes is present
in the psci.yaml file.
- a "cpus" node describing the available cores and their associated
"enable-method"s. For more details see cpus.txt file.
"enable-method"s. For more details see cpus.yaml file.
Example:

2
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -124,6 +124,7 @@ properties:
- arm,cortex-a15
- arm,cortex-a17
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
- arm,cortex-a72
- arm,cortex-a73
@ -155,6 +156,7 @@ properties:
- qcom,krait
- qcom,kryo
- qcom,kryo385
- qcom,kryo485
- qcom,scorpion
enable-method:

32
Documentation/devicetree/bindings/arm/idle-states.txt
View File

@ -28,7 +28,7 @@ PM implementation to put the processor in different idle states (which include
states listed above; "off" state is not an idle state since it does not have
wake-up capabilities, hence it is not considered in this document).
Idle state parameters (eg entry latency) are platform specific and need to be
Idle state parameters (e.g. entry latency) are platform specific and need to be
characterized with bindings that provide the required information to OS PM
code so that it can build the required tables and use them at runtime.
@ -90,24 +90,24 @@ These timing parameters can be used by an OS in different circumstances.
An idle CPU requires the expected min-residency time to select the most
appropriate idle state based on the expected expiry time of the next IRQ
(ie wake-up) that causes the CPU to return to the EXEC phase.
(i.e. wake-up) that causes the CPU to return to the EXEC phase.
An operating system scheduler may need to compute the shortest wake-up delay
for CPUs in the system by detecting how long will it take to get a CPU out
of an idle state, eg:
of an idle state, e.g.:
wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
In other words, the scheduler can make its scheduling decision by selecting
(eg waking-up) the CPU with the shortest wake-up latency.
The wake-up latency must take into account the entry latency if that period
(e.g. waking-up) the CPU with the shortest wake-up delay.
The wake-up delay must take into account the entry latency if that period
has not expired. The abortable nature of the PREP period can be ignored
if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
the worst case since it depends on the CPU operating conditions, ie caches
the worst case since it depends on the CPU operating conditions, i.e. caches
state).
An OS has to reliably probe the wakeup-latency since some devices can enforce
latency constraints guarantees to work properly, so the OS has to detect the
latency constraint guarantees to work properly, so the OS has to detect the
worst case wake-up latency it can incur if a CPU is allowed to enter an
idle state, and possibly to prevent that to guarantee reliable device
functioning.
@ -183,15 +183,15 @@ and IDLE2:
Graph 2: idle states min-residency example
In graph 2 above, that takes into account idle states entry/exit energy
costs, it is clear that if the idle state residency time (ie time till next
costs, it is clear that if the idle state residency time (i.e. time till next
wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
choice energywise.
This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
than IDLE2.
However, the lower power consumption (ie shallower energy curve slope) of idle
state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
However, the lower power consumption (i.e. shallower energy curve slope) of
idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
efficient.
The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
@ -214,8 +214,8 @@ processor idle states, defined as device tree nodes, are listed.
Usage: Optional - On ARM systems, it is a container of processor idle
states nodes. If the system does not provide CPU
power management capabilities or the processor just
supports idle_standby an idle-states node is not
power management capabilities, or the processor just
supports idle_standby, an idle-states node is not
required.
Description: idle-states node is a container node, where its
@ -287,14 +287,14 @@ follows:
Value type: <prop-encoded-array>
Definition: u32 value representing worst case latency in
microseconds required to enter the idle state.
The exit-latency-us duration may be guaranteed
only after entry-latency-us has passed.
- exit-latency-us
Usage: Required
Value type: <prop-encoded-array>
Definition: u32 value representing worst case latency
in microseconds required to exit the idle state.
The exit-latency-us duration may be guaranteed
only after entry-latency-us has passed.
- min-residency-us
Usage: Required
@ -342,8 +342,8 @@ follows:
state.
In addition to the properties listed above, a state node may require
additional properties specifics to the entry-method defined in the
idle-states node, please refer to the entry-method bindings
additional properties specific to the entry-method defined in the
idle-states node. Please refer to the entry-method bindings
documentation for properties definitions.
===========================================

22
Documentation/devicetree/bindings/arm/realtek.txt
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@ -1,22 +0,0 @@
Realtek platforms device tree bindings
--------------------------------------
RTD1295 SoC
===========
Required root node properties:
- compatible : must contain "realtek,rtd1295"
Root node property compatible must contain, depending on board:
- MeLE V9: "mele,v9"
- ProBox2 AVA: "probox2,ava"
- Zidoo X9S: "zidoo,x9s"
Example:
compatible = "zidoo,x9s", "realtek,rtd1295";

23
Documentation/devicetree/bindings/arm/realtek.yaml 100644
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@ -0,0 +1,23 @@
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/realtek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek platforms device tree bindings
maintainers:
- Andreas Färber <afaerber@suse.de>
properties:
$nodename:
const: '/'
compatible:
# RTD1295 SoC based boards
items:
- enum:
- mele,v9
- probox2,ava
- zidoo,x9s
- const: realtek,rtd1295
...

2
Documentation/devicetree/bindings/ata/ahci-platform.txt
View File

@ -45,7 +45,7 @@ Required properties when using sub-nodes:
- #address-cells : number of cells to encode an address
- #size-cells : number of cells representing the size of an address
For allwinner,sun8i-r40-ahci, the reset propertie must be present.
For allwinner,sun8i-r40-ahci, the reset property must be present.
Sub-nodes required properties:
- reg : the port number

85
Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml 100644
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@ -0,0 +1,85 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A64 Display Engine Bus Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
$nodename:
pattern: "^bus(@[0-9a-f]+)?$"
"#address-cells":
const: 1
"#size-cells":
const: 1
compatible:
oneOf:
- const: allwinner,sun50i-a64-de2
- items:
- const: allwinner,sun50i-h6-de3
- const: allwinner,sun50i-a64-de2
reg:
maxItems: 1
allwinner,sram:
allOf:
- $ref: /schemas/types.yaml#definitions/phandle-array
- maxItems: 1
description:
The SRAM that needs to be claimed to access the display engine
bus.
ranges: true
patternProperties:
# All other properties should be child nodes with unit-address and 'reg'
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
type: object
properties:
reg:
maxItems: 1
required:
- reg
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
- allwinner,sram
additionalProperties: false
examples:
- |
bus@1000000 {
compatible = "allwinner,sun50i-a64-de2";
reg = <0x1000000 0x400000>;
allwinner,sram = <&de2_sram 1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000000 0x400000>;
display_clocks: clock@0 {
compatible = "allwinner,sun50i-a64-de2-clk";
reg = <0x0 0x100000>;
clocks = <&ccu 52>, <&ccu 99>;
clock-names = "bus", "mod";
resets = <&ccu 30>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
...

2
Documentation/devicetree/bindings/bus/qcom,ebi2.txt
View File

@ -71,7 +71,7 @@ Optional subnodes:
The following optional properties are properties that can be tagged onto
any device subnode. We are assuming that there can be only ONE device per
chipselect subnode, else the properties will become ambigous.
chipselect subnode, else the properties will become ambiguous.
Optional properties arrays for SLOW chip selects:
- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to

40
Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
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@ -1,40 +0,0 @@
Device tree bindings for Allwinner DE2/3 bus
The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
to be claimed for enabling the access. The DE3 on Allwinner H6 is at the same
situation, and the binding also applies.
Required properties:
- compatible: Should be one of:
- "allwinner,sun50i-a64-de2"
- "allwinner,sun50i-h6-de3", "allwinner,sun50i-a64-de2"
- reg: A resource specifier for the register space
- #address-cells: Must be set to 1
- #size-cells: Must be set to 1
- ranges: Must be set up to map the address space inside the
DE2, for the sub-blocks of DE2.
- allwinner,sram: the SRAM that needs to be claimed
Example:
de2@1000000 {
compatible = "allwinner,sun50i-a64-de2";
reg = <0x1000000 0x400000>;
allwinner,sram = <&de2_sram 1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000000 0x400000>;
display_clocks: clock@0 {
compatible = "allwinner,sun50i-a64-de2-clk";
reg = <0x0 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

79
Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml 100644
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@ -0,0 +1,79 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/allwinner,sun4i-a10-crypto.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Security System Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
compatible:
oneOf:
- const: allwinner,sun4i-a10-crypto
- items:
- const: allwinner,sun5i-a13-crypto
- const: allwinner,sun4i-a10-crypto
- items:
- const: allwinner,sun6i-a31-crypto
- const: allwinner,sun4i-a10-crypto
- items:
- const: allwinner,sun7i-a20-crypto
- const: allwinner,sun4i-a10-crypto
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: ahb
- const: mod
resets:
maxItems: 1
reset-names:
const: ahb
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
if:
properties:
compatible:
contains:
const: allwinner,sun6i-a31-crypto
then:
required:
- resets
- reset-names
additionalProperties: false
examples:
- |
crypto: crypto-engine@1c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <86>;
clocks = <&ahb_gates 5>, <&ss_clk>;
clock-names = "ahb", "mod";
};
...

23
Documentation/devicetree/bindings/crypto/sun4i-ss.txt
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@ -1,23 +0,0 @@
* Allwinner Security System found on A20 SoC
Required properties:
- compatible : Should be "allwinner,sun4i-a10-crypto".
- reg: Should contain the Security System register location and length.
- interrupts: Should contain the IRQ line for the Security System.
- clocks : List of clock specifiers, corresponding to ahb and ss.
- clock-names : Name of the functional clock, should be
* "ahb" : AHB gating clock
* "mod" : SS controller clock
Optional properties:
- resets : phandle + reset specifier pair
- reset-names : must contain "ahb"
Example:
crypto: crypto-engine@1c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 5>, <&ss_clk>;
clock-names = "ahb", "mod";
};

2
Documentation/devicetree/bindings/example-schema.yaml
View File

@ -5,7 +5,7 @@
# All the top-level keys are standard json-schema keywords except for
# 'maintainers' and 'select'
# $id is a unique idenifier based on the filename. There may or may not be a
# $id is a unique identifier based on the filename. There may or may not be a
# file present at the URL.
$id: "http://devicetree.org/schemas/example-schema.yaml#"
# $schema is the meta-schema this schema should be validated with.

92
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
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@ -1,92 +0,0 @@
ARM Mali Bifrost GPU
====================
Required properties:
- compatible :
* Since Mali Bifrost GPU model/revision is fully discoverable by reading
some determined registers, must contain the following:
+ "arm,mali-bifrost"
* which must be preceded by one of the following vendor specifics:
+ "amlogic,meson-g12a-mali"
- reg : Physical base address of the device and length of the register area.
- interrupts : Contains the three IRQ lines required by Mali Bifrost devices,
in the following defined order.
- interrupt-names : Contains the names of IRQ resources in this exact defined
order: "job", "mmu", "gpu".
Optional properties:
- clocks : Phandle to clock for the Mali Bifrost device.
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.
- resets : Phandle of the GPU reset line.
Vendor-specific bindings
------------------------
The Mali GPU is integrated very differently from one SoC to
another. In order to accommodate those differences, you have the option
to specify one more vendor-specific compatible, among:
- "amlogic,meson-g12a-mali"
Required properties:
- resets : Should contain phandles of :
+ GPU reset line
+ GPU APB glue reset line
Example for a Mali-G31:
gpu@ffa30000 {
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
reg = <0xffe40000 0x10000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&clk CLKID_MALI>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp@533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp@450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp@266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Bifrost GPU
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
items:
- enum:
- amlogic,meson-g12a-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
reg:
maxItems: 1
interrupts:
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
interrupt-names:
items:
- const: job
- const: mmu
- const: gpu
clocks:
maxItems: 1
mali-supply:
maxItems: 1
operating-points-v2: true
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
allOf:
- if:
properties:
compatible:
contains:
const: amlogic,meson-g12a-mali
then:
properties:
resets:
minItems: 2
required:
- resets
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@ffe40000 {
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
reg = <0xffe40000 0x10000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&clk 1>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
resets = <&reset 0>, <&reset 1>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp@533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp@450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp@266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
...

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ARM Mali Midgard GPU
====================
Required properties:
- compatible :
* Must contain one of the following:
+ "arm,mali-t604"
+ "arm,mali-t624"
+ "arm,mali-t628"
+ "arm,mali-t720"
+ "arm,mali-t760"
+ "arm,mali-t820"
+ "arm,mali-t830"
+ "arm,mali-t860"
+ "arm,mali-t880"
* which must be preceded by one of the following vendor specifics:
+ "allwinner,sun50i-h6-mali"
+ "amlogic,meson-gxm-mali"
+ "samsung,exynos5433-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
- reg : Physical base address of the device and length of the register area.
- interrupts : Contains the three IRQ lines required by Mali Midgard devices.
- interrupt-names : Contains the names of IRQ resources in the order they were
provided in the interrupts property. Must contain: "job", "mmu", "gpu".
Optional properties:
- clocks : Phandle to clock for the Mali Midgard device.
- clock-names : Specify the names of the clocks specified in clocks
when multiple clocks are present.
* core: clock driving the GPU itself (When only one clock is present,
assume it's this clock.)
* bus: bus clock for the GPU
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.
- #cooling-cells: Refer to Documentation/devicetree/bindings/thermal/thermal.txt
for details.
- resets : Phandle of the GPU reset line.
Vendor-specific bindings
------------------------
The Mali GPU is integrated very differently from one SoC to
another. In order to accommodate those differences, you have the option
to specify one more vendor-specific compatible, among:
- "allwinner,sun50i-h6-mali"
Required properties:
- clocks : phandles to core and bus clocks
- clock-names : must contain "core" and "bus"
- resets: phandle to GPU reset line
- "amlogic,meson-gxm-mali"
Required properties:
- resets : Should contain phandles of :
+ GPU reset line
+ GPU APB glue reset line
Example for a Mali-T760:
gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru ACLK_GPU>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3288_PD_GPU>;
#cooling-cells = <2>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp@533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp@450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp@266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Midgard GPU
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- enum:
- allwinner,sun50i-h6-mali
- const: arm,mali-t720
- items:
- enum:
- amlogic,meson-gxm-mali
- const: arm,mali-t820
- items:
- enum:
- rockchip,rk3288-mali
- const: arm,mali-t760
- items:
- enum:
- rockchip,rk3399-mali
- const: arm,mali-t860
- items:
- enum:
- samsung,exynos5250-mali
- const: arm,mali-t604
- items:
- enum:
- samsung,exynos5433-mali
- const: arm,mali-t760
# "arm,mali-t624"
# "arm,mali-t628"
# "arm,mali-t830"
# "arm,mali-t880"
reg:
maxItems: 1
interrupts:
items:
- description: Job interrupt
- description: MMU interrupt
- description: GPU interrupt
interrupt-names:
items:
- const: job
- const: mmu
- const: gpu
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: bus
mali-supply:
maxItems: 1
resets:
minItems: 1
maxItems: 2
operating-points-v2: true
"#cooling-cells":
const: 2
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
allOf:
- if:
properties:
compatible:
contains:
const: allwinner,sun50i-h6-mali
then:
properties:
clocks:
minItems: 2
required:
- clock-names
- resets
- if:
properties:
compatible:
contains:
const: amlogic,meson-gxm-mali
then:
properties:
resets:
minItems: 2
required:
- resets
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@ffa30000 {
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
reg = <0xffa30000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru 0>;
mali-supply = <&vdd_gpu>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power 0>;
#cooling-cells = <2>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp@533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp@450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp@266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
...

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ARM Mali Utgard GPU
===================
Required properties:
- compatible
* Must be one of the following:
+ "arm,mali-300"
+ "arm,mali-400"
+ "arm,mali-450"
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ allwinner,sun8i-h3-mali
+ allwinner,sun50i-a64-mali
+ allwinner,sun50i-h5-mali
+ amlogic,meson8-mali
+ amlogic,meson8b-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
+ samsung,exynos4210-mali
+ rockchip,rk3036-mali
+ rockchip,rk3066-mali
+ rockchip,rk3188-mali
+ rockchip,rk3228-mali
+ rockchip,rk3328-mali
+ stericsson,db8500-mali
- reg: Physical base address and length of the GPU registers
- interrupts: an entry for each entry in interrupt-names.
See ../interrupt-controller/interrupts.txt for details.
- interrupt-names:
* ppX: Pixel Processor X interrupt (X from 0 to 7)
* ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
* pp: Pixel Processor broadcast interrupt (mali-450 only)
* gp: Geometry Processor interrupt
* gpmmu: Geometry Processor MMU interrupt
- clocks: an entry for each entry in clock-names
- clock-names:
* bus: bus clock for the GPU
* core: clock driving the GPU itself
Optional properties:
- interrupt-names and interrupts:
* pmu: Power Management Unit interrupt, if implemented in hardware
- memory-region:
Memory region to allocate from, as defined in
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
- mali-supply:
Phandle to regulator for the Mali device, as defined in
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- operating-points-v2:
Operating Points for the GPU, as defined in
Documentation/devicetree/bindings/opp/opp.txt
- power-domains:
A power domain consumer specifier as defined in
Documentation/devicetree/bindings/power/power_domain.txt
Vendor-specific bindings
------------------------
The Mali GPU is integrated very differently from one SoC to
another. In order to accomodate those differences, you have the option
to specify one more vendor-specific compatible, among:
- allwinner,sun4i-a10-mali
Required properties:
* resets: phandle to the reset line for the GPU
- allwinner,sun7i-a20-mali
Required properties:
* resets: phandle to the reset line for the GPU
- allwinner,sun50i-a64-mali
Required properties:
* resets: phandle to the reset line for the GPU
- allwinner,sun50i-h5-mali
Required properties:
* resets: phandle to the reset line for the GPU
- amlogic,meson8-mali and amlogic,meson8b-mali
Required properties:
* resets: phandle to the reset line for the GPU
- Rockchip variants:
Required properties:
* resets: phandle to the reset line for the GPU
- stericsson,db8500-mali
Required properties:
* interrupt-names and interrupts:
+ combined: combined interrupt of all of the above lines
Example:
mali: gpu@1c40000 {
compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pmu";
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_BUS_GPU>;
};

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali Utgard GPU
maintainers:
- Rob Herring <robh@kernel.org>
- Maxime Ripard <maxime.ripard@free-electrons.com>
- Heiko Stuebner <heiko@sntech.de>
properties:
$nodename:
pattern: '^gpu@[a-f0-9]+$'
compatible:
oneOf:
- items:
- const: allwinner,sun8i-a23-mali
- const: allwinner,sun7i-a20-mali
- const: arm,mali-400
- items:
- enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-h3-mali
- allwinner,sun50i-a64-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- samsung,exynos4210-mali
- stericsson,db8500-mali
- const: arm,mali-400
- items:
- enum:
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali
- amlogic,meson8b-mali
- amlogic,meson-gxbb-mali
- amlogic,meson-gxl-mali
- hisilicon,hi6220-mali
- rockchip,rk3328-mali
- const: arm,mali-450
# "arm,mali-300"
reg:
maxItems: 1
interrupts:
minItems: 4
maxItems: 20
interrupt-names:
allOf:
- additionalItems: true
minItems: 4
maxItems: 20
items:
# At least enforce the first 2 interrupts
- const: gp
- const: gpmmu
- items:
# Not ideal as any order and combination are allowed
enum:
- gp # Geometry Processor interrupt
- gpmmu # Geometry Processor MMU interrupt
- pp # Pixel Processor broadcast interrupt (mali-450 only)
- pp0 # Pixel Processor X interrupt (X from 0 to 7)
- ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
- pp1
- ppmmu1
- pp2
- ppmmu2
- pp3
- ppmmu3
- pp4
- ppmmu4
- pp5
- ppmmu5
- pp6
- ppmmu6
- pp7
- ppmmu7
- pmu # Power Management Unit interrupt (optional)
- combined # stericsson,db8500-mali only
clocks:
maxItems: 2
clock-names:
items:
- const: bus
- const: core
memory-region: true
mali-supply:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
operating-points-v2: true
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun50i-a64-mali
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali
- amlogic,meson8b-mali
- hisilicon,hi6220-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- rockchip,rk3328-mali
then:
required:
- resets
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mali: gpu@1c40000 {
compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pmu";
clocks = <&ccu 1>, <&ccu 2>;
clock-names = "bus", "core";
resets = <&ccu 1>;
};
...

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/allwinner,sun4i-a10-lradc-keys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 LRADC Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
compatible:
oneOf:
- const: allwinner,sun4i-a10-lradc-keys
- const: allwinner,sun8i-a83t-r-lradc
- items:
- const: allwinner,sun50i-a64-lradc
- const: allwinner,sun8i-a83t-r-lradc
reg:
maxItems: 1
interrupts:
maxItems: 1
vref-supply:
description:
Regulator for the LRADC reference voltage
patternProperties:
"^button-[0-9]+$":
type: object
properties:
label:
$ref: /schemas/types.yaml#/definitions/string
description: Descriptive name of the key
linux,code:
$ref: /schemas/types.yaml#/definitions/uint32
description: Keycode to emit
channel:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1]
description: ADC Channel this key is attached to
voltage:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Voltage in microvolts at LRADC input when this key is
pressed
required:
- label
- linux,code
- channel
- voltage
additionalProperties: false
required:
- compatible
- reg
- interrupts
- vref-supply
additionalProperties: false
examples:
- |
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
vref-supply = <&reg_vcc3v0>;
button-191 {
label = "Volume Up";
linux,code = <115>;
channel = <0>;
voltage = <191274>;
};
button-392 {
label = "Volume Down";
linux,code = <114>;
channel = <0>;
voltage = <392644>;
};
};
...

65
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Allwinner sun4i low res adc attached tablet keys
------------------------------------------------
Required properties:
- compatible: should be one of the following string:
"allwinner,sun4i-a10-lradc-keys"
"allwinner,sun8i-a83t-r-lradc"
"allwinner,sun50i-a64-lradc", "allwinner,sun8i-a83t-r-lradc"
- reg: mmio address range of the chip
- interrupts: interrupt to which the chip is connected
- vref-supply: powersupply for the lradc reference voltage
Each key is represented as a sub-node of the compatible mentioned above:
Required subnode-properties:
- label: Descriptive name of the key.
- linux,code: Keycode to emit.
- channel: Channel this key is attached to, must be 0 or 1.
- voltage: Voltage in µV at lradc input when this key is pressed.
Example:
#include <dt-bindings/input/input.h>
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
vref-supply = <&reg_vcc3v0>;
button@191 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <191274>;
};
button@392 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <392644>;
};
button@601 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <601151>;
};
button@795 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
voltage = <795090>;
};
button@987 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <987387>;
};
};

47
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@ -0,0 +1,47 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun4i-a10-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Interrupt Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
"#interrupt-cells":
const: 1
compatible:
enum:
- allwinner,sun4i-a10-ic
- allwinner,suniv-f1c100s-ic
reg:
maxItems: 1
interrupt-controller: true
required:
- "#interrupt-cells"
- compatible
- reg
- interrupt-controller
additionalProperties: false
examples:
- |
intc: interrupt-controller@1c20400 {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
...

20
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@ -1,20 +0,0 @@
Allwinner Sunxi Interrupt Controller
Required properties:
- compatible : should be one of the following:
"allwinner,sun4i-a10-ic"
"allwinner,suniv-f1c100s-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
intc: interrupt-controller {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};

70
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@ -0,0 +1,70 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A20 Non-Maskable Interrupt Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
"#interrupt-cells":
const: 2
description:
The first cell is the IRQ number, the second cell the trigger
type as defined in interrupt.txt in this directory.
compatible:
oneOf:
- const: allwinner,sun6i-a31-r-intc
- const: allwinner,sun6i-a31-sc-nmi
deprecated: true
- const: allwinner,sun7i-a20-sc-nmi
- items:
- const: allwinner,sun8i-a83t-r-intc
- const: allwinner,sun6i-a31-r-intc
- const: allwinner,sun9i-a80-sc-nmi
- items:
- const: allwinner,sun50i-a64-r-intc
- const: allwinner,sun6i-a31-r-intc
- items:
- const: allwinner,sun50i-h6-r-intc
- const: allwinner,sun6i-a31-r-intc
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
required:
- "#interrupt-cells"
- compatible
- reg
- interrupts
- interrupt-controller
# FIXME: We should set it, but it would report all the generic
# properties as additional properties.
# additionalProperties: false
examples:
- |
interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x01c00030 0x0c>;
interrupt-parent = <&gic>;
interrupts = <0 0 4>;
};
...

29
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@ -1,29 +0,0 @@
Allwinner Sunxi NMI Controller
==============================
Required properties:
- compatible : should be one of the following:
- "allwinner,sun7i-a20-sc-nmi"
- "allwinner,sun6i-a31-sc-nmi" (deprecated)
- "allwinner,sun6i-a31-r-intc"
- "allwinner,sun9i-a80-nmi"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 2. The first cell is the IRQ number, the
second cell the trigger type as defined in interrupt.txt in this directory.
- interrupts: Specifies the interrupt line (NMI) which is handled by
the interrupt controller in the parent controller's notation. This value
shall be the NMI.
Example:
sc-nmi-intc@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x01c00030 0x0c>;
interrupt-parent = <&gic>;
interrupts = <0 0 4>;
};

8
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@ -22,10 +22,10 @@ controller node. This property is inherited, so it may be specified in an
interrupt client node or in any of its parent nodes. Interrupts listed in the
"interrupts" property are always in reference to the node's interrupt parent.
The "interrupts-extended" property is a special form for use when a node needs
to reference multiple interrupt parents. Each entry in this property contains
both the parent phandle and the interrupt specifier. "interrupts-extended"
should only be used when a device has multiple interrupt parents.
The "interrupts-extended" property is a special form; useful when a node needs
to reference multiple interrupt parents or a different interrupt parent than
the inherited one. Each entry in this property contains both the parent phandle
and the interrupt specifier.
Example:
interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;

52
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson Message-Handling-Unit Controller
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
description: |
The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
that has 3 independent channels/links to communicate with remote processor(s).
MHU links are hardwired on a platform. A link raises interrupt for any
received data. However, there is no specified way of knowing if the sent
data has been read by the remote. This driver assumes the sender polls
STAT register and the remote clears it after having read the data.
properties:
compatible:
enum:
- amlogic,meson-gxbb-mhu
reg:
maxItems: 1
interrupts:
minItems: 3
description:
Contains the interrupt information corresponding to each of the 3 links
of MHU.
"#mbox-cells":
const: 1
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
examples:
- |
mailbox@c883c404 {
compatible = "amlogic,meson-gxbb-mhu";
reg = <0xc883c404 0x4c>;
interrupts = <208>, <209>, <210>;
#mbox-cells = <1>;
};

34
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@ -1,34 +0,0 @@
Amlogic Meson MHU Mailbox Driver
================================
The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
that has 3 independent channels/links to communicate with remote processor(s).
MHU links are hardwired on a platform. A link raises interrupt for any
received data. However, there is no specified way of knowing if the sent
data has been read by the remote. This driver assumes the sender polls
STAT register and the remote clears it after having read the data.
Mailbox Device Node:
====================
Required properties:
--------------------
- compatible: Shall be "amlogic,meson-gxbb-mhu"
- reg: Contains the mailbox register address range (base
address and length)
- #mbox-cells Shall be 1 - the index of the channel needed.
- interrupts: Contains the interrupt information corresponding to
each of the 2 links of MHU.
Example:
--------
mailbox: mailbox@c883c404 {
#mbox-cells = <1>;
compatible = "amlogic,meson-gxbb-mhu";
reg = <0 0xc883c404 0 0x4c>;
interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
<0 209 IRQ_TYPE_EDGE_RISING>,
<0 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};

10
Documentation/devicetree/bindings/media/i2c/nokia,smia.txt
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@ -7,6 +7,9 @@ of that. These definitions are valid for both types of sensors.
More detailed documentation can be found in
Documentation/devicetree/bindings/media/video-interfaces.txt .
The device node should contain a "port" node which may contain one or more
endpoint nodes, in accordance with video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt .
Mandatory properties
--------------------
@ -37,9 +40,7 @@ Optional properties
Endpoint node mandatory properties
----------------------------------
- clock-lanes: <0>
- data-lanes: <1..n>
- remote-endpoint: A phandle to the bus receiver's endpoint node.
Example
@ -48,7 +49,7 @@ Example
&i2c2 {
clock-frequency = <400000>;
smiapp_1: camera@10 {
camera-sensor@10 {
compatible = "nokia,smia";
reg = <0x10>;
reset-gpios = <&gpio3 20 0>;
@ -58,8 +59,7 @@ Example
nokia,nvm-size = <512>; /* 8 * 64 */
link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
port {
smiapp_1_1: endpoint {
clock-lanes = <0>;
smiapp_ep: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&csi2a_ep>;
};

2
Documentation/devicetree/bindings/pci/pci-msi.txt
View File

@ -201,7 +201,7 @@ Example (5)
#msi-cells = <1>;
};
pci: pci@c {
pci: pci@f {
reg = <0xf 0x1>;
compatible = "vendor,pcie-root-complex";
device_type = "pci";

63
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic G12A USB2 PHY
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
properties:
compatible:
enum:
- amlogic,meson-g12a-usb2-phy
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: xtal
resets:
maxItems: 1
reset-names:
items:
- const: phy
"#phy-cells":
const: 0
phy-supply:
maxItems: 1
description:
Phandle to a regulator that provides power to the PHY. This
regulator will be managed during the PHY power on/off sequence.
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- "#phy-cells"
examples:
- |
phy@36000 {
compatible = "amlogic,meson-g12a-usb2-phy";
reg = <0x36000 0x2000>;
clocks = <&xtal>;
clock-names = "xtal";
resets = <&phy_reset>;
reset-names = "phy";
#phy-cells = <0>;
};

57
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@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic G12A USB3 + PCIE Combo PHY
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
properties:
compatible:
enum:
- amlogic,meson-g12a-usb3-pcie-phy
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: ref_clk
resets:
maxItems: 1
reset-names:
items:
- const: phy
"#phy-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- "#phy-cells"
examples:
- |
phy@46000 {
compatible = "amlogic,meson-g12a-usb3-pcie-phy";
reg = <0x46000 0x2000>;
clocks = <&ref_clk>;
clock-names = "ref_clk";
resets = <&phy_reset>;
reset-names = "phy";
#phy-cells = <1>;
};

22
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@ -1,22 +0,0 @@
* Amlogic G12A USB2 PHY binding
Required properties:
- compatible: Should be "amlogic,meson-g12a-usb2-phy"
- reg: The base address and length of the registers
- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
- clocks: a phandle to the clock of this PHY
- clock-names: must be "xtal"
- resets: a phandle to the reset line of this PHY
- reset-names: must be "phy"
- phy-supply: see phy-bindings.txt in this directory
Example:
usb2_phy0: phy@36000 {
compatible = "amlogic,g12a-usb2-phy";
reg = <0x0 0x36000 0x0 0x2000>;
clocks = <&xtal>;
clock-names = "xtal";
resets = <&reset RESET_USB_PHY21>;
reset-names = "phy";
#phy-cells = <0>;
};

22
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@ -1,22 +0,0 @@
* Amlogic G12A USB3 + PCIE Combo PHY binding
Required properties:
- compatible: Should be "amlogic,meson-g12a-usb3-pcie-phy"
- #phys-cells: must be 1. The cell number is used to select the phy mode
as defined in <dt-bindings/phy/phy.h> between PHY_TYPE_USB3 and PHY_TYPE_PCIE
- reg: The base address and length of the registers
- clocks: a phandle to the 100MHz reference clock of this PHY
- clock-names: must be "ref_clk"
- resets: phandle to the reset lines for the PHY control
- reset-names: must be "phy"
Example:
usb3_pcie_phy: phy@46000 {
compatible = "amlogic,g12a-usb3-pcie-phy";
reg = <0x0 0x46000 0x0 0x2000>;
clocks = <&clkc CLKID_PCIE_PLL>;
clock-names = "ref_clk";
resets = <&reset RESET_PCIE_PHY>;
reset-names = "phy";
#phy-cells = <1>;
};

2
Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
View File

@ -82,7 +82,7 @@ gpiom1: gpio@0 {
compatible = "microchip,mcp23s17";
gpio-controller;
#gpio-cells = <2>;
spi-present-mask = <0x01>;
microchip,spi-present-mask = <0x01>;
reg = <0>;
spi-max-frequency = <1000000>;
};

19
Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
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@ -1,19 +0,0 @@
Amlogic Meson SoC Reset Controller
=======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or
"amlogic,meson-axg-reset".
- reg: should contain the register address base
- #reset-cells: 1, see below
example:
reset: reset-controller {
compatible = "amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
#reset-cells = <1>;
};

37
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@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson SoC Reset Controller
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
properties:
compatible:
enum:
- amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
- amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
reg:
maxItems: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#reset-cells"
examples:
- |
reset-controller@c884404 {
compatible = "amlogic,meson-gxbb-reset";
reg = <0xc884404 0x20>;
#reset-cells = <1>;
};

1
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
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@ -11,6 +11,7 @@ Required properties:
- compatible: should be one of the following:
- "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
- "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
- "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below

21
Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
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@ -1,21 +0,0 @@
Amlogic Meson Random number generator
=====================================
Required properties:
- compatible : should be "amlogic,meson-rng"
- reg : Specifies base physical address and size of the registers.
Optional properties:
- clocks : phandle to the following named clocks
- clock-names: Name of core clock, must be "core"
Example:
rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0xc8834000 0x0 0x4>;
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};

37
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@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/rng/amlogic,meson-rng.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson Random number generator
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
properties:
compatible:
enum:
- amlogic,meson-rng
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: core
required:
- compatible
- reg
examples:
- |
rng@c8834000 {
compatible = "amlogic,meson-rng";
reg = <0xc8834000 0x4>;
};

1
Documentation/devicetree/bindings/rng/mtk-rng.txt
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@ -6,6 +6,7 @@ Required properties:
"mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622
"mediatek,mt7629-rng", "mediatek,mt7623-rng" : for MT7629
"mediatek,mt7623-rng" : for MT7623
"mediatek,mt8516-rng", "mediatek,mt7623-rng" : for MT8516
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : Should contain "rng" entries;

38
Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
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@ -1,38 +0,0 @@
Amlogic Meson SoC UART Serial Interface
=======================================
The Amlogic Meson SoC UART Serial Interface is present on a large range
of SoCs, and can be present either in the "Always-On" power domain or the
"Everything-Else" power domain.
The particularity of the "Always-On" Serial Interface is that the hardware
is active since power-on and does not need any clock gating and is usable
as very early serial console.
Required properties:
- compatible : compatible: value should be different for each SoC family as :
- Meson6 : "amlogic,meson6-uart"
- Meson8 : "amlogic,meson8-uart"
- Meson8b : "amlogic,meson8b-uart"
- GX (GXBB, GXL, GXM) : "amlogic,meson-gx-uart"
eventually followed by : "amlogic,meson-ao-uart" if this UART interface
is in the "Always-On" power domain.
- reg : offset and length of the register set for the device.
- interrupts : identifier to the device interrupt
- clocks : a list of phandle + clock-specifier pairs, one for each
entry in clock names.
- clock-names :
* "xtal" for external xtal clock identifier
* "pclk" for the bus core clock, either the clk81 clock or the gate clock
* "baud" for the source of the baudrate generator, can be either the xtal
or the pclk.
e.g.
uart_A: serial@84c0 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
/* Use xtal as baud rate clock source */
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};

73
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@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson SoC UART Serial Interface
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
description: |
The Amlogic Meson SoC UART Serial Interface is present on a large range
of SoCs, and can be present either in the "Always-On" power domain or the
"Everything-Else" power domain.
The particularity of the "Always-On" Serial Interface is that the hardware
is active since power-on and does not need any clock gating and is usable
as very early serial console.
properties:
compatible:
oneOf:
- description: Always-on power domain UART controller
items:
- enum:
- amlogic,meson6-uart
- amlogic,meson8-uart
- amlogic,meson8b-uart
- amlogic,meson-gx-uart
- const: amlogic,meson-ao-uart
- description: Everything-Else power domain UART controller
enum:
- amlogic,meson6-uart
- amlogic,meson8-uart
- amlogic,meson8b-uart
- amlogic,meson-gx-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: external xtal clock identifier
- description: the bus core clock, either the clk81 clock or the gate clock
- description: the source of the baudrate generator, can be either the xtal or the pclk
clock-names:
items:
- const: xtal
- const: pclk
- const: baud
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
examples:
- |
serial@84c0 {
compatible = "amlogic,meson-gx-uart";
reg = <0x84c0 0x14>;
interrupts = <26>;
clocks = <&xtal>, <&pclk>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};

67
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@ -0,0 +1,67 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson SPI Communication Controller
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
allOf:
- $ref: "spi-controller.yaml#"
description: |
The Meson SPICC is a generic SPI controller for general purpose Full-Duplex
communications with dedicated 16 words RX/TX PIO FIFOs.
properties:
compatible:
enum:
- amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs
- amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs
interrupts:
maxItems: 1
reg:
maxItems: 1
resets:
maxItems: 1
clocks:
maxItems: 1
clock-names:
description: input clock for the baud rate generator
items:
- const: core
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
examples:
- |
spi@c1108d80 {
compatible = "amlogic,meson-gx-spicc";
reg = <0xc1108d80 0x80>;
interrupts = <112>;
clocks = <&clk81>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@0 {
compatible = "micrel,ks8995m";
spi-max-frequency = <1000000>;
reg = <0>;
};
};

53
Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml 100644
View File

@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson SPI Flash Controller
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
allOf:
- $ref: "spi-controller.yaml#"
description: |
The Meson SPIFC is a controller optimized for communication with SPI
NOR memories, without DMA support and a 64-byte unified transmit /
receive buffer.
properties:
compatible:
enum:
- amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
- amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
examples:
- |
spi@c1108c80 {
compatible = "amlogic,meson6-spifc";
reg = <0xc1108c80 0x80>;
clocks = <&clk81>;
#address-cells = <1>;
#size-cells = <0>;
flash: flash@0 {
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};

55
Documentation/devicetree/bindings/spi/spi-meson.txt
View File

@ -1,55 +0,0 @@
Amlogic Meson SPI controllers
* SPIFC (SPI Flash Controller)
The Meson SPIFC is a controller optimized for communication with SPI
NOR memories, without DMA support and a 64-byte unified transmit /
receive buffer.
Required properties:
- compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
- reg: physical base address and length of the controller registers
- clocks: phandle of the input clock for the baud rate generator
- #address-cells: should be 1
- #size-cells: should be 0
spi@c1108c80 {
compatible = "amlogic,meson6-spifc";
reg = <0xc1108c80 0x80>;
clocks = <&clk81>;
#address-cells = <1>;
#size-cells = <0>;
};
* SPICC (SPI Communication Controller)
The Meson SPICC is generic SPI controller for general purpose Full-Duplex
communications with dedicated 16 words RX/TX PIO FIFOs.
Required properties:
- compatible: should be:
"amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
"amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
- reg: physical base address and length of the controller registers
- interrupts: The interrupt specifier
- clock-names: Must contain "core"
- clocks: phandle of the input clock for the baud rate generator
- #address-cells: should be 1
- #size-cells: should be 0
Optional properties:
- resets: phandle of the internal reset line
See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
required and optional properties.
Example :
spi@c1108d80 {
compatible = "amlogic,meson-gx-spicc";
reg = <0xc1108d80 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&clk81>;
#address-cells = <1>;
#size-cells = <0>;
};

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -443,6 +443,8 @@ patternProperties:
description: Innolux Corporation
"^inside-secure,.*":
description: INSIDE Secure
"^inspur,.*":
description: Inspur Corporation
"^intel,.*":
description: Intel Corporation
"^intercontrol,.*":

37
Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml 100644
View File

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Meson GXBB SoCs Watchdog timer
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
properties:
compatible:
enum:
- amlogic,meson-gxbb-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
description:
A phandle to the clock of this PHY
required:
- compatible
- reg
- clocks
examples:
- |
watchdog@98d0 {
compatible = "amlogic,meson-gxbb-wdt";
reg = <0x98d0 0x10>;
clocks = <&xtal>;
};

16
Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt
View File

@ -1,16 +0,0 @@
Meson GXBB SoCs Watchdog timer
Required properties:
- compatible : should be "amlogic,meson-gxbb-wdt"
- reg : Specifies base physical address and size of the registers.
- clocks : Should be a phandle to the Watchdog clock source, for GXBB the xtal
is the default clock source.
Example:
wdt: watchdog@98d0 {
compatible = "amlogic,meson-gxbb-wdt";
reg = <0 0x98d0 0x0 0x10>;
clocks = <&xtal>;
};

1
Documentation/devicetree/writing-schema.rst
View File

@ -141,6 +141,7 @@ It is also possible to run checks with a single schema file by setting the
::
make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/trivial-devices.yaml
make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/trivial-devices.yaml

4
MAINTAINERS
View File

@ -1400,7 +1400,7 @@ F: drivers/pinctrl/actions/*
F: drivers/soc/actions/
F: include/dt-bindings/power/owl-*
F: include/linux/soc/actions/
F: Documentation/devicetree/bindings/arm/actions.txt
F: Documentation/devicetree/bindings/arm/actions.yaml
F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
F: Documentation/devicetree/bindings/dma/owl-dma.txt
F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
@ -2166,7 +2166,7 @@ M: Andreas Färber <afaerber@suse.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/realtek/
F: Documentation/devicetree/bindings/arm/realtek.txt
F: Documentation/devicetree/bindings/arm/realtek.yaml
ARM/RENESAS ARM64 ARCHITECTURE
M: Simon Horman <horms@verge.net.au>

6
Makefile
View File

@ -1514,8 +1514,10 @@ help:
@echo ''
@$(if $(dtstree), \
echo 'Devicetree:'; \
echo '* dtbs - Build device tree blobs for enabled boards'; \
echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'; \
echo '* dtbs - Build device tree blobs for enabled boards'; \
echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'; \
echo ' dt_binding_check - Validate device tree binding documents'; \
echo ' dtbs_check - Validate device tree source files';\
echo '')
@echo 'Userspace tools targets:'

2
drivers/iommu/arm-smmu.c
View File

@ -156,7 +156,7 @@ static int __find_legacy_master_phandle(struct device *dev, void *data)
int err;
of_for_each_phandle(it, err, dev->of_node, "mmu-masters",
"#stream-id-cells", 0)
"#stream-id-cells", -1)
if (it->node == np) {
*(void **)data = dev;
return 1;

2
drivers/iommu/mtk_iommu_v1.c
View File

@ -427,7 +427,7 @@ static int mtk_iommu_add_device(struct device *dev)
int err;
of_for_each_phandle(&it, err, dev->of_node, "iommus",
"#iommu-cells", 0) {
"#iommu-cells", -1) {
int count = of_phandle_iterator_args(&it, iommu_spec.args,
MAX_PHANDLE_ARGS);
iommu_spec.np = of_node_get(it.node);

58
drivers/of/base.c
View File

@ -1286,6 +1286,13 @@ int of_phandle_iterator_init(struct of_phandle_iterator *it,
memset(it, 0, sizeof(*it));
/*
* one of cell_count or cells_name must be provided to determine the
* argument length.
*/
if (cell_count < 0 && !cells_name)
return -EINVAL;
list = of_get_property(np, list_name, &size);
if (!list)
return -ENOENT;
@ -1335,11 +1342,20 @@ int of_phandle_iterator_next(struct of_phandle_iterator *it)
if (of_property_read_u32(it->node, it->cells_name,
&count)) {
pr_err("%pOF: could not get %s for %pOF\n",
it->parent,
it->cells_name,
it->node);
goto err;
/*
* If both cell_count and cells_name is given,
* fall back to cell_count in absence
* of the cells_name property
*/
if (it->cell_count >= 0) {
count = it->cell_count;
} else {
pr_err("%pOF: could not get %s for %pOF\n",
it->parent,
it->cells_name,
it->node);
goto err;
}
}
} else {
count = it->cell_count;
@ -1503,10 +1519,17 @@ int of_parse_phandle_with_args(const struct device_node *np, const char *list_na
const char *cells_name, int index,
struct of_phandle_args *out_args)
{
int cell_count = -1;
if (index < 0)
return -EINVAL;
return __of_parse_phandle_with_args(np, list_name, cells_name, 0,
index, out_args);
/* If cells_name is NULL we assume a cell count of 0 */
if (!cells_name)
cell_count = 0;
return __of_parse_phandle_with_args(np, list_name, cells_name,
cell_count, index, out_args);
}
EXPORT_SYMBOL(of_parse_phandle_with_args);
@ -1588,7 +1611,7 @@ int of_parse_phandle_with_args_map(const struct device_node *np,
if (!pass_name)
goto free;
ret = __of_parse_phandle_with_args(np, list_name, cells_name, 0, index,
ret = __of_parse_phandle_with_args(np, list_name, cells_name, -1, index,
out_args);
if (ret)
goto free;
@ -1756,7 +1779,24 @@ int of_count_phandle_with_args(const struct device_node *np, const char *list_na
struct of_phandle_iterator it;
int rc, cur_index = 0;
rc = of_phandle_iterator_init(&it, np, list_name, cells_name, 0);
/*
* If cells_name is NULL we assume a cell count of 0. This makes
* counting the phandles trivial as each 32bit word in the list is a
* phandle and no arguments are to consider. So we don't iterate through
* the list but just use the length to determine the phandle count.
*/
if (!cells_name) {
const __be32 *list;
int size;
list = of_get_property(np, list_name, &size);
if (!list)
return -ENOENT;
return size / sizeof(*list);
}
rc = of_phandle_iterator_init(&it, np, list_name, cells_name, -1);
if (rc)
return rc;

4
drivers/of/unittest.c
View File

@ -1044,8 +1044,10 @@ static void __init of_unittest_platform_populate(void)
test_bus = platform_device_register_full(&test_bus_info);
rc = PTR_ERR_OR_ZERO(test_bus);
unittest(!rc, "testbus registration failed; rc=%i\n", rc);
if (rc)
if (rc) {
of_node_put(np);
return;
}
test_bus->dev.of_node = np;
/*

7
include/dt-bindings/reset/hisi,hi6220-resets.h
View File

@ -73,4 +73,11 @@
#define MEDIA_MMU 6
#define MEDIA_XG2RAM1 7
#define AO_G3D 1
#define AO_CODECISP 2
#define AO_MCPU 4
#define AO_BBPHARQMEM 5
#define AO_HIFI 8
#define AO_ACPUSCUL2C 12
#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/