Merge branch 'topic/ioatdma' into for-linus
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commit
e3c373616a
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@ -321,7 +321,8 @@ EXPORT_SYMBOL_GPL(dca_get_tag);
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* @ops - pointer to struct of dca operation function pointers
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* @priv_size - size of extra mem to be added for provider's needs
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*/
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struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size)
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struct dca_provider *alloc_dca_provider(const struct dca_ops *ops,
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int priv_size)
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{
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struct dca_provider *dca;
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int alloc_size;
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@ -224,7 +224,7 @@ static u8 ioat_dca_get_tag(struct dca_provider *dca,
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return tag;
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}
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static struct dca_ops ioat_dca_ops = {
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static const struct dca_ops ioat_dca_ops = {
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.add_requester = ioat_dca_add_requester,
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.remove_requester = ioat_dca_remove_requester,
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.get_tag = ioat_dca_get_tag,
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@ -235,43 +235,11 @@ ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
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return ioat_dma->idx[index];
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}
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static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan)
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{
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u8 ver = ioat_chan->ioat_dma->version;
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u64 status;
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u32 status_lo;
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/* We need to read the low address first as this causes the
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* chipset to latch the upper bits for the subsequent read
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*/
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status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
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status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
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status <<= 32;
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status |= status_lo;
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return status;
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}
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#if BITS_PER_LONG == 64
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static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
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{
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u8 ver = ioat_chan->ioat_dma->version;
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u64 status;
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/* With IOAT v3.3 the status register is 64bit. */
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if (ver >= IOAT_VER_3_3)
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status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
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else
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status = ioat_chansts_32(ioat_chan);
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return status;
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return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
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}
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#else
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#define ioat_chansts ioat_chansts_32
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#endif
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static inline u64 ioat_chansts_to_addr(u64 status)
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{
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return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
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@ -99,19 +99,9 @@
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#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
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#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */
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#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
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#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
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#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
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? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
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#define IOAT1_CHANSTS_OFFSET_LOW 0x04
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#define IOAT2_CHANSTS_OFFSET_LOW 0x08
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#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
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? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
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#define IOAT1_CHANSTS_OFFSET_HIGH 0x08
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#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C
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#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
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? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
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/* IOAT1 define left for i7300_idle driver to not fail compiling */
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#define IOAT1_CHANSTS_OFFSET 0x04
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#define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
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#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL)
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#define IOAT_CHANSTS_SOFT_ERR 0x10ULL
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#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL
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@ -34,7 +34,7 @@ void dca_unregister_notify(struct notifier_block *nb);
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struct dca_provider {
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struct list_head node;
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struct dca_ops *ops;
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const struct dca_ops *ops;
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struct device *cd;
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int id;
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};
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@ -53,7 +53,8 @@ struct dca_ops {
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int (*dev_managed) (struct dca_provider *, struct device *);
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};
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struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size);
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struct dca_provider *alloc_dca_provider(const struct dca_ops *ops,
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int priv_size);
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void free_dca_provider(struct dca_provider *dca);
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int register_dca_provider(struct dca_provider *dca, struct device *dev);
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void unregister_dca_provider(struct dca_provider *dca, struct device *dev);
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