ath9k: Fix bugs in handling TX power
* Get power table offset from the EEPROM instead of using a hardcoded value of -5 if the EEPROM rev is >= 21. * Add support in the 4k eeprom code for tx power offset in case we have a 4k AR9280 implementation. * Fix tx power accuracy at high powers. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -134,6 +134,7 @@
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#define AR5416_EEP_MINOR_VER_17 0x11
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#define AR5416_EEP_MINOR_VER_19 0x13
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#define AR5416_EEP_MINOR_VER_20 0x14
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#define AR5416_EEP_MINOR_VER_21 0x15
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#define AR5416_EEP_MINOR_VER_22 0x16
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#define AR5416_NUM_5G_CAL_PIERS 8
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@ -154,7 +155,7 @@
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#define AR5416_BCHAN_UNUSED 0xFF
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#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
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#define AR5416_MAX_CHAINS 3
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#define AR5416_PWR_TABLE_OFFSET -5
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#define AR5416_PWR_TABLE_OFFSET_DB -5
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/* Rx gain type values */
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#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
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@ -302,7 +303,7 @@ struct base_eep_header {
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u8 txGainType;
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u8 rcChainMask;
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u8 desiredScaleCCK;
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u8 power_table_offset;
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u8 pwr_table_offset;
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u8 frac_n_5g;
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u8 futureBase_3[21];
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} __packed;
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@ -210,6 +210,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
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return pBase->rxMask;
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case EEP_FRAC_N_5G:
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return 0;
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case EEP_PWR_TABLE_OFFSET:
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return AR5416_PWR_TABLE_OFFSET_DB;
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default:
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return 0;
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}
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@ -753,7 +755,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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if (AR_SREV_9280_10_OR_LATER(ah)) {
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for (i = 0; i < Ar5416RateSize; i++)
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ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
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ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
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}
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/* OFDM power per rate */
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@ -291,6 +291,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
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return pBase->frac_n_5g;
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else
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return 0;
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case EEP_PWR_TABLE_OFFSET:
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if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
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return pBase->pwr_table_offset;
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else
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return AR5416_PWR_TABLE_OFFSET_DB;
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default:
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return 0;
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}
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@ -741,6 +746,76 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
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return;
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}
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static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
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u16 *gb,
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u16 numXpdGain,
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u16 pdGainOverlap_t2,
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int8_t pwr_table_offset,
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int16_t *diff)
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{
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u16 k;
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/* Prior to writing the boundaries or the pdadc vs. power table
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* into the chip registers the default starting point on the pdadc
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* vs. power table needs to be checked and the curve boundaries
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* adjusted accordingly
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*/
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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u16 gb_limit;
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if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
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/* get the difference in dB */
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*diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
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/* get the number of half dB steps */
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*diff *= 2;
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/* change the original gain boundary settings
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* by the number of half dB steps
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*/
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for (k = 0; k < numXpdGain; k++)
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gb[k] = (u16)(gb[k] - *diff);
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}
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/* Because of a hardware limitation, ensure the gain boundary
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* is not larger than (63 - overlap)
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*/
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gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
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for (k = 0; k < numXpdGain; k++)
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gb[k] = (u16)min(gb_limit, gb[k]);
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}
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return *diff;
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}
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static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
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int8_t pwr_table_offset,
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int16_t diff,
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u8 *pdadcValues)
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{
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#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
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u16 k;
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/* If this is a board that has a pwrTableOffset that differs from
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* the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
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* pdadc vs pwr table needs to be adjusted prior to writing to the
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* chip.
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*/
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
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/* shift the table to start at the new offset */
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for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
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pdadcValues[k] = pdadcValues[k + diff];
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}
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/* fill the back of the table */
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for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
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pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
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}
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}
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}
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#undef NUM_PDADC
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}
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static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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struct ath9k_channel *chan,
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int16_t *pTxPowerIndexOffset)
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@ -756,15 +831,18 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
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u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
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u16 numPiers, i, j;
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int16_t tMinCalPower;
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int16_t tMinCalPower, diff = 0;
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u16 numXpdGain, xpdMask;
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u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
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u32 reg32, regOffset, regChainOffset;
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int16_t modalIdx;
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int8_t pwr_table_offset;
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modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
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xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
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pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
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if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
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AR5416_EEP_MINOR_VER_2) {
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pdGainOverlap_t2 =
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@ -844,6 +922,13 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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numXpdGain);
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}
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diff = ath9k_change_gain_boundary_setting(ah,
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gainBoundaries,
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numXpdGain,
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pdGainOverlap_t2,
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pwr_table_offset,
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&diff);
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if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
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if (OLC_FOR_AR9280_20_LATER) {
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REG_WRITE(ah,
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@ -864,6 +949,10 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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}
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}
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ath9k_adjust_pdadc_values(ah, pwr_table_offset,
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diff, pdadcValues);
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regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
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for (j = 0; j < 32; j++) {
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reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
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@ -1199,8 +1288,13 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
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}
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if (AR_SREV_9280_10_OR_LATER(ah)) {
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for (i = 0; i < Ar5416RateSize; i++)
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ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
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for (i = 0; i < Ar5416RateSize; i++) {
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int8_t pwr_table_offset;
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pwr_table_offset = ah->eep_ops->get_eeprom(ah,
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EEP_PWR_TABLE_OFFSET);
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ratesArray[i] -= pwr_table_offset * 2;
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}
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}
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
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@ -1299,7 +1393,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
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if (AR_SREV_9280_10_OR_LATER(ah))
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regulatory->max_power_level =
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ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
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ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
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else
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regulatory->max_power_level = ratesArray[i];
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