Merge remote-tracking branches 'asoc/topic/davinci' and 'asoc/topic/dwc' into asoc-next
Mark Brown
commit
e449f7a394
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@ -0,0 +1,51 @@
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Texas Instruments DaVinci McBSP module
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This binding describes the "Multi-channel Buffered Serial Port" (McBSP)
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audio interface found in some TI DaVinci processors like the OMAP-L138 or AM180x.
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Required properties:
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~~~~~~~~~~~~~~~~~~~~
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- compatible :
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"ti,da850-mcbsp" : for DA850, AM180x and OPAM-L138 platforms
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- reg : physical base address and length of the controller memory mapped
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region(s).
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- reg-names : Should contain:
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* "mpu" for the main registers (required).
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* "dat" for the data FIFO (optional).
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- dmas: three element list of DMA controller phandles, DMA request line and
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TC channel ordered triplets.
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- dma-names: identifier string for each DMA request line in the dmas property.
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These strings correspond 1:1 with the ordered pairs in dmas. The dma
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identifiers must be "rx" and "tx".
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Optional properties:
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~~~~~~~~~~~~~~~~~~~~
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- interrupts : Interrupt numbers for McBSP
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- interrupt-names : Known interrupt names are "rx" and "tx"
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- pinctrl-0: Should specify pin control group used for this controller.
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- pinctrl-names: Should contain only one value - "default", for more details
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please refer to pinctrl-bindings.txt
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Example (AM1808):
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~~~~~~~~~~~~~~~~~
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mcbsp0: mcbsp@1d10000 {
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compatible = "ti,da850-mcbsp";
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pinctrl-names = "default";
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pinctrl-0 = <&mcbsp0_pins>;
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reg = <0x00110000 0x1000>,
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<0x00310000 0x1000>;
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reg-names = "mpu", "dat";
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interrupts = <97 98>;
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interrupts-names = "rx", "tx";
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dmas = <&edma0 3 1
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&edma0 2 1>;
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dma-names = "tx", "rx";
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status = "okay";
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};
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@ -16,7 +16,11 @@ config SND_EDMA_SOC
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- DRA7xx family
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config SND_DAVINCI_SOC_I2S
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tristate
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tristate "DaVinci Multichannel Buffered Serial Port (McBSP) support"
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depends on SND_EDMA_SOC
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help
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Say Y or M here if you want to have support for McBSP IP found in
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Texas Instruments DaVinci DA850 SoCs.
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config SND_DAVINCI_SOC_MCASP
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tristate "Multichannel Audio Serial Port (McASP) support"
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@ -4,9 +4,15 @@
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* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
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* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
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*
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* DT support (c) 2016 Petr Kulhavy, Barix AG <petr@barix.com>
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* based on davinci-mcasp.c DT support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* TODO:
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* on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers
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*/
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#include <linux/init.h>
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@ -650,13 +656,24 @@ static const struct snd_soc_component_driver davinci_i2s_component = {
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static int davinci_i2s_probe(struct platform_device *pdev)
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{
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struct snd_dmaengine_dai_dma_data *dma_data;
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struct davinci_mcbsp_dev *dev;
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struct resource *mem, *res;
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void __iomem *io_base;
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int *dma;
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int ret;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
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if (!mem) {
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dev_warn(&pdev->dev,
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"\"mpu\" mem resource not found, using index 0\n");
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "no mem resource?\n");
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return -ENODEV;
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}
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}
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io_base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(io_base))
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return PTR_ERR(io_base);
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@ -666,40 +683,44 @@ static int davinci_i2s_probe(struct platform_device *pdev)
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if (!dev)
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return -ENOMEM;
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dev->base = io_base;
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/* setup DMA, first TX, then RX */
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dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
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dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
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res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (res) {
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dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
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*dma = res->start;
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dma_data->filter_data = dma;
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} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
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dma_data->filter_data = "tx";
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} else {
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dev_err(&pdev->dev, "Missing DMA tx resource\n");
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return -ENODEV;
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}
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dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
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dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
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res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
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if (res) {
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dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
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*dma = res->start;
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dma_data->filter_data = dma;
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} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
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dma_data->filter_data = "rx";
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} else {
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dev_err(&pdev->dev, "Missing DMA rx resource\n");
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return -ENODEV;
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}
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dev->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(dev->clk))
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return -ENODEV;
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clk_enable(dev->clk);
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dev->base = io_base;
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dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
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(dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
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dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
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(dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
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/* first TX, then RX */
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res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (!res) {
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dev_err(&pdev->dev, "no DMA resource\n");
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ret = -ENXIO;
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goto err_release_clk;
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}
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dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
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*dma = res->start;
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dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = dma;
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res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
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if (!res) {
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dev_err(&pdev->dev, "no DMA resource\n");
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ret = -ENXIO;
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goto err_release_clk;
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}
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dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
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*dma = res->start;
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dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = dma;
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dev->dev = &pdev->dev;
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dev_set_drvdata(&pdev->dev, dev);
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@ -737,11 +758,18 @@ static int davinci_i2s_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id davinci_i2s_match[] = {
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{ .compatible = "ti,da850-mcbsp" },
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{},
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};
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MODULE_DEVICE_TABLE(of, davinci_i2s_match);
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static struct platform_driver davinci_mcbsp_driver = {
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.probe = davinci_i2s_probe,
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.remove = davinci_i2s_remove,
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.driver = {
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.name = "davinci-mcbsp",
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.of_match_table = of_match_ptr(davinci_i2s_match),
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},
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};
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@ -540,21 +540,19 @@ out:
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return ret;
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}
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static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
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int div, bool explicit)
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{
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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pm_runtime_get_sync(mcasp->dev);
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switch (div_id) {
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case 0: /* MCLK divider */
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case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
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AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
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AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
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break;
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case 1: /* BCLK divider */
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case MCASP_CLKDIV_BCLK: /* BCLK divider */
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
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ACLKXDIV(div - 1), ACLKXDIV_MASK);
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
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@ -563,7 +561,8 @@ static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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mcasp->bclk_div = div;
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break;
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case 2: /*
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case MCASP_CLKDIV_BCLK_FS_RATIO:
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/*
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* BCLK/LRCLK ratio descries how many bit-clock cycles
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* fit into one frame. The clock ratio is given for a
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* full period of data (for I2S format both left and
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@ -591,7 +590,9 @@ static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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int div)
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{
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return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
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return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
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}
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static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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@ -999,27 +1000,53 @@ static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
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}
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static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
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unsigned int bclk_freq,
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int *error_ppm)
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unsigned int bclk_freq, bool set)
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{
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int div = mcasp->sysclk_freq / bclk_freq;
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int rem = mcasp->sysclk_freq % bclk_freq;
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int error_ppm;
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unsigned int sysclk_freq = mcasp->sysclk_freq;
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u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
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int div = sysclk_freq / bclk_freq;
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int rem = sysclk_freq % bclk_freq;
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int aux_div = 1;
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if (div > (ACLKXDIV_MASK + 1)) {
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if (reg & AHCLKXE) {
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aux_div = div / (ACLKXDIV_MASK + 1);
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if (div % (ACLKXDIV_MASK + 1))
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aux_div++;
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sysclk_freq /= aux_div;
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div = sysclk_freq / bclk_freq;
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rem = sysclk_freq % bclk_freq;
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} else if (set) {
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dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
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sysclk_freq);
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}
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}
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if (rem != 0) {
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if (div == 0 ||
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((mcasp->sysclk_freq / div) - bclk_freq) >
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(bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
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((sysclk_freq / div) - bclk_freq) >
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(bclk_freq - (sysclk_freq / (div+1)))) {
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div++;
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rem = rem - bclk_freq;
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}
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}
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if (error_ppm)
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*error_ppm =
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(div*1000000 + (int)div64_long(1000000LL*rem,
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(int)bclk_freq))
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/div - 1000000;
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error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
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(int)bclk_freq)) / div - 1000000;
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return div;
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if (set) {
|
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if (error_ppm)
|
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dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
|
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error_ppm);
|
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|
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__davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
|
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if (reg & AHCLKXE)
|
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__davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
|
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aux_div, 0);
|
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}
|
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|
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return error_ppm;
|
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}
|
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|
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static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
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|
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@ -1044,18 +1071,11 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
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int slots = mcasp->tdm_slots;
|
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int rate = params_rate(params);
|
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int sbits = params_width(params);
|
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int ppm, div;
|
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|
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if (mcasp->slot_width)
|
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sbits = mcasp->slot_width;
|
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|
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div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
|
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&ppm);
|
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if (ppm)
|
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dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
|
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ppm);
|
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|
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__davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
|
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davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
|
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}
|
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|
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ret = mcasp_common_hw_param(mcasp, substream->stream,
|
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|
|
@ -1166,7 +1186,8 @@ static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
|
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davinci_mcasp_dai_rates[i];
|
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int ppm;
|
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|
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davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
|
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ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
|
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false);
|
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if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
|
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if (range.empty) {
|
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range.min = davinci_mcasp_dai_rates[i];
|
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|
|
@ -1205,8 +1226,9 @@ static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
|
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if (rd->mcasp->slot_width)
|
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sbits = rd->mcasp->slot_width;
|
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|
||||
davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate,
|
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&ppm);
|
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ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
|
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sbits * slots * rate,
|
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false);
|
||||
if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
|
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snd_mask_set(&nfmt, i);
|
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count++;
|
||||
|
|
@ -1230,11 +1252,15 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
|
|||
int i, dir;
|
||||
int tdm_slots = mcasp->tdm_slots;
|
||||
|
||||
if (mcasp->tdm_mask[substream->stream])
|
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tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
|
||||
/* Do not allow more then one stream per direction */
|
||||
if (mcasp->substreams[substream->stream])
|
||||
return -EBUSY;
|
||||
|
||||
mcasp->substreams[substream->stream] = substream;
|
||||
|
||||
if (mcasp->tdm_mask[substream->stream])
|
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tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
|
||||
|
||||
if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
|
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return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -306,4 +306,9 @@
|
|||
#define NUMEVT(x) (((x) & 0xFF) << 8)
|
||||
#define NUMDMA_MASK (0xFF)
|
||||
|
||||
/* clock divider IDs */
|
||||
#define MCASP_CLKDIV_AUXCLK 0 /* HCLK divider from AUXCLK */
|
||||
#define MCASP_CLKDIV_BCLK 1 /* BCLK divider from HCLK */
|
||||
#define MCASP_CLKDIV_BCLK_FS_RATIO 2 /* to set BCLK FS ration */
|
||||
|
||||
#endif /* DAVINCI_MCASP_H */
|
||||
|
|
|
|||
|
|
@ -100,6 +100,7 @@ struct dw_i2s_dev {
|
|||
struct device *dev;
|
||||
u32 ccr;
|
||||
u32 xfer_resolution;
|
||||
u32 fifo_th;
|
||||
|
||||
/* data related to DMA transfers b/w i2s and DMAC */
|
||||
union dw_i2s_snd_dma_data play_dma_data;
|
||||
|
|
@ -147,17 +148,18 @@ static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
|
|||
static void i2s_start(struct dw_i2s_dev *dev,
|
||||
struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct i2s_clk_config_data *config = &dev->config;
|
||||
u32 i, irq;
|
||||
i2s_write_reg(dev->i2s_base, IER, 1);
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
for (i = 0; i < 4; i++) {
|
||||
for (i = 0; i < (config->chan_nr / 2); i++) {
|
||||
irq = i2s_read_reg(dev->i2s_base, IMR(i));
|
||||
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
|
||||
}
|
||||
i2s_write_reg(dev->i2s_base, ITER, 1);
|
||||
} else {
|
||||
for (i = 0; i < 4; i++) {
|
||||
for (i = 0; i < (config->chan_nr / 2); i++) {
|
||||
irq = i2s_read_reg(dev->i2s_base, IMR(i));
|
||||
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
|
||||
}
|
||||
|
|
@ -231,14 +233,16 @@ static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
|
|||
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
i2s_write_reg(dev->i2s_base, TCR(ch_reg),
|
||||
dev->xfer_resolution);
|
||||
i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
|
||||
i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
|
||||
dev->fifo_th - 1);
|
||||
irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
|
||||
i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
|
||||
i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
|
||||
} else {
|
||||
i2s_write_reg(dev->i2s_base, RCR(ch_reg),
|
||||
dev->xfer_resolution);
|
||||
i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
|
||||
i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
|
||||
dev->fifo_th - 1);
|
||||
irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
|
||||
i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
|
||||
i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
|
||||
|
|
@ -498,6 +502,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
|
|||
*/
|
||||
u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
|
||||
u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
|
||||
u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
|
||||
u32 idx;
|
||||
|
||||
if (dev->capability & DWC_I2S_RECORD &&
|
||||
|
|
@ -536,6 +541,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
|
|||
dev->capability |= DW_I2S_SLAVE;
|
||||
}
|
||||
|
||||
dev->fifo_th = fifo_depth / 2;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue