drm/nv50/disp: more accurate function to determine active crtcs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
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6bdf68c9a4
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@ -50,6 +50,29 @@ nv50_sor_nr(struct drm_device *dev)
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return 4;
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return 4;
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}
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}
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u32
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nv50_display_active_crtcs(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 mask = 0;
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int i;
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if (dev_priv->chipset < 0x90 ||
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dev_priv->chipset == 0x92 ||
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dev_priv->chipset == 0xa0) {
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for (i = 0; i < 2; i++)
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mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
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} else {
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for (i = 0; i < 4; i++)
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mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
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}
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for (i = 0; i < 3; i++)
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mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
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return mask & 3;
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}
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static int
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static int
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evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
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evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
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{
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{
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@ -74,6 +74,8 @@ void nv50_display_destroy(struct drm_device *dev);
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int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
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int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
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int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
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int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
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u32 nv50_display_active_crtcs(struct drm_device *);
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int nv50_display_sync(struct drm_device *);
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int nv50_display_sync(struct drm_device *);
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int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
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int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
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struct nouveau_channel *chan);
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struct nouveau_channel *chan);
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@ -28,6 +28,7 @@
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#include "nouveau_hw.h"
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#include "nouveau_hw.h"
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#include "nouveau_pm.h"
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#include "nouveau_pm.h"
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#include "nouveau_hwsq.h"
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#include "nouveau_hwsq.h"
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#include "nv50_display.h"
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enum clk_src {
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enum clk_src {
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clk_src_crystal,
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clk_src_crystal,
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@ -535,6 +536,7 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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struct nv50_pm_state *info)
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struct nv50_pm_state *info)
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{
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 crtc_mask = nv50_display_active_crtcs(dev);
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struct nouveau_mem_exec_func exec = {
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struct nouveau_mem_exec_func exec = {
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.dev = dev,
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.dev = dev,
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.precharge = mclk_precharge,
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.precharge = mclk_precharge,
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@ -550,9 +552,8 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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};
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};
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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struct pll_lims pll;
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struct pll_lims pll;
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u32 crtc_mask = 0;
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int N, M, P;
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int N, M, P;
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int ret, i;
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int ret;
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/* use pcie refclock if possible, otherwise use mpll */
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/* use pcie refclock if possible, otherwise use mpll */
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info->mctrl = nv_rd32(dev, 0x004008);
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info->mctrl = nv_rd32(dev, 0x004008);
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@ -569,12 +570,6 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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info->mcoef = (N << 8) | M;
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info->mcoef = (N << 8) | M;
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}
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}
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/* determine active crtcs */
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for (i = 0; i < 2; i++) {
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if (nv_rd32(dev, NV50_PDISPLAY_CRTC_C(i, CLOCK)))
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crtc_mask |= (1 << i);
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}
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/* build the ucode which will reclock the memory for us */
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/* build the ucode which will reclock the memory for us */
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hwsq_init(hwsq);
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hwsq_init(hwsq);
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if (crtc_mask) {
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if (crtc_mask) {
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