drm/i915/chv: Add phy supports for Cherryview
Added programming phy layer for CHV based on "Application note for 1273 CHV Display phy". v2: Rebase the code and do some cleanup. v3: Rework based on Ville review. -Fix the macro where the ch info need to swap, and add parens to ? operator. -Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and DPIO_PCS_SWING_CALC_1 and rename for meaningful. -Add some comments for CHV specific DPIO registers. -Change the dp margin registery value to decimal to align with the doc. -Fix the not clearing some value in vlv_dpio_read before write again. -Create new hdmi/dp encoder function for chv instead of share with valleyview. v4: Rebase the code after rename the DPIO registers define and upstream change. Based on Ville review. -For unique transition scale selection, after Ville point out, look like the doc might wrong for the bit 26. Use bit 27 for ch0 and ch1. -Break up some dpio write value into two/three steps for readability. -Remove unrelated change. -Add some shift define for some registers instead just give the hex value. -Fix a bug where write to wrong VLV_TX_DW3. v5: Based on Ville review. - Move tx lane latency optimal setting from chv_dp_pre_pll_enable to chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to chv_hdmi_pre_enable respectively. - Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400. - Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI. - Mask the old deemph and swing bits for hdmi. v6: Remove stub for pre_pll_enable for dp and hdmi. Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [vsyrjala: Don't touch panel power sequencing on DP] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1968,6 +1968,50 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
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mutex_unlock(&dev_priv->dpio_lock);
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}
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static void chv_pre_enable_dp(struct intel_encoder *encoder)
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{
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct edp_power_seq power_seq;
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struct intel_crtc *intel_crtc =
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to_intel_crtc(encoder->base.crtc);
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enum dpio_channel ch = vlv_dport_to_channel(dport);
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int pipe = intel_crtc->pipe;
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int data, i;
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/* Program Tx lane latency optimal setting*/
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mutex_lock(&dev_priv->dpio_lock);
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for (i = 0; i < 4; i++) {
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/* Set the latency optimal bit */
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data = (i == 1) ? 0x0 : 0x6;
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vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
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data << DPIO_FRC_LATENCY_SHFIT);
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/* Set the upar bit */
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data = (i == 1) ? 0x0 : 0x1;
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vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
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data << DPIO_UPAR_SHIFT);
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}
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/* Data lane stagger programming */
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/* FIXME: Fix up value only after power analysis */
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mutex_unlock(&dev_priv->dpio_lock);
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if (is_edp(intel_dp)) {
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/* init power sequencer on this pipe and port */
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intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
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&power_seq);
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}
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intel_enable_dp(encoder);
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vlv_wait_port_ready(dev_priv, dport);
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}
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/*
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* Native read with retry for link status and receiver capability reads for
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* cases where the sink may still be asleep.
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@ -2192,6 +2236,142 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
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return 0;
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}
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static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
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struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
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u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
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uint8_t train_set = intel_dp->train_set[0];
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enum dpio_channel ch = vlv_dport_to_channel(dport);
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int pipe = intel_crtc->pipe;
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switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
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case DP_TRAIN_PRE_EMPHASIS_0:
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switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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deemph_reg_value = 128;
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margin_reg_value = 52;
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break;
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case DP_TRAIN_VOLTAGE_SWING_600:
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deemph_reg_value = 128;
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margin_reg_value = 77;
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break;
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case DP_TRAIN_VOLTAGE_SWING_800:
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deemph_reg_value = 128;
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margin_reg_value = 102;
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break;
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case DP_TRAIN_VOLTAGE_SWING_1200:
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deemph_reg_value = 128;
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margin_reg_value = 154;
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/* FIXME extra to set for 1200 */
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break;
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default:
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return 0;
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}
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break;
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case DP_TRAIN_PRE_EMPHASIS_3_5:
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switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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deemph_reg_value = 85;
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margin_reg_value = 78;
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break;
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case DP_TRAIN_VOLTAGE_SWING_600:
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deemph_reg_value = 85;
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margin_reg_value = 116;
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break;
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case DP_TRAIN_VOLTAGE_SWING_800:
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deemph_reg_value = 85;
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margin_reg_value = 154;
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break;
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default:
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return 0;
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}
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break;
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case DP_TRAIN_PRE_EMPHASIS_6:
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switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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deemph_reg_value = 64;
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margin_reg_value = 104;
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break;
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case DP_TRAIN_VOLTAGE_SWING_600:
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deemph_reg_value = 64;
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margin_reg_value = 154;
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break;
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default:
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return 0;
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}
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break;
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case DP_TRAIN_PRE_EMPHASIS_9_5:
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switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_400:
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deemph_reg_value = 43;
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margin_reg_value = 154;
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break;
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default:
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return 0;
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}
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break;
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default:
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return 0;
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}
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mutex_lock(&dev_priv->dpio_lock);
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/* Clear calc init */
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vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
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/* Program swing deemph */
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val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
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val &= ~DPIO_SWING_DEEMPH9P5_MASK;
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val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
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/* Program swing margin */
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tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
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tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
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tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
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/* Disable unique transition scale */
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val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
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val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
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if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
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== DP_TRAIN_PRE_EMPHASIS_0) &&
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((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
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== DP_TRAIN_VOLTAGE_SWING_1200)) {
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/*
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* The document said it needs to set bit 27 for ch0 and bit 26
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* for ch1. Might be a typo in the doc.
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* For now, for this unique transition scale selection, set bit
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* 27 for ch0 and ch1.
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*/
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val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
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val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
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tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
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}
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/* Start swing calculation */
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vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
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(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
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/* LRC Bypass */
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val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
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val |= DPIO_LRC_BYPASS;
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vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
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mutex_unlock(&dev_priv->dpio_lock);
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return 0;
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}
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static void
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intel_get_adjust_train(struct intel_dp *intel_dp,
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const uint8_t link_status[DP_LINK_STATUS_SIZE])
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@ -2406,6 +2586,9 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
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} else if (IS_HASWELL(dev)) {
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signal_levels = intel_hsw_signal_levels(train_set);
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mask = DDI_BUF_EMP_MASK;
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} else if (IS_CHERRYVIEW(dev)) {
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signal_levels = intel_chv_signal_levels(intel_dp);
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mask = 0;
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} else if (IS_VALLEYVIEW(dev)) {
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signal_levels = intel_vlv_signal_levels(intel_dp);
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mask = 0;
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intel_encoder->disable = intel_disable_dp;
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intel_encoder->get_hw_state = intel_dp_get_hw_state;
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intel_encoder->get_config = intel_dp_get_config;
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if (IS_VALLEYVIEW(dev)) {
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if (IS_CHERRYVIEW(dev)) {
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intel_encoder->pre_enable = chv_pre_enable_dp;
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intel_encoder->enable = vlv_enable_dp;
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} else if (IS_VALLEYVIEW(dev)) {
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intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
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intel_encoder->pre_enable = vlv_pre_enable_dp;
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intel_encoder->enable = vlv_enable_dp;
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@ -1224,6 +1224,85 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
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mutex_unlock(&dev_priv->dpio_lock);
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}
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static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
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{
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struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc =
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to_intel_crtc(encoder->base.crtc);
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enum dpio_channel ch = vlv_dport_to_channel(dport);
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int pipe = intel_crtc->pipe;
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int data, i;
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u32 val;
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/* Program Tx latency optimal setting */
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mutex_lock(&dev_priv->dpio_lock);
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for (i = 0; i < 4; i++) {
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/* Set the latency optimal bit */
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data = (i == 1) ? 0x0 : 0x6;
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vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
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data << DPIO_FRC_LATENCY_SHFIT);
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/* Set the upar bit */
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data = (i == 1) ? 0x0 : 0x1;
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vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
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data << DPIO_UPAR_SHIFT);
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}
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/* Data lane stagger programming */
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/* FIXME: Fix up value only after power analysis */
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/* Clear calc init */
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vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
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/* FIXME: Program the support xxx V-dB */
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/* Use 800mV-0dB */
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val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
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val &= ~DPIO_SWING_DEEMPH9P5_MASK;
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val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
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val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
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val &= ~DPIO_SWING_MARGIN_MASK;
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val |= 102 << DPIO_SWING_MARGIN_SHIFT;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), val);
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/* Disable unique transition scale */
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val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
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val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
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/* Additional steps for 1200mV-0dB */
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#if 0
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val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
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if (ch)
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val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
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else
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val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
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vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
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vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
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(0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
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#endif
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/* Start swing calculation */
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vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
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DPIO_PCS_SWING_CALC_TX0_TX2 |
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DPIO_PCS_SWING_CALC_TX1_TX3);
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/* LRC Bypass */
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val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
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val |= DPIO_LRC_BYPASS;
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vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
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mutex_unlock(&dev_priv->dpio_lock);
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intel_enable_hdmi(encoder);
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vlv_wait_port_ready(dev_priv, dport);
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}
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static void intel_hdmi_destroy(struct drm_connector *connector)
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{
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drm_connector_cleanup(connector);
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intel_encoder->disable = intel_disable_hdmi;
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intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
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intel_encoder->get_config = intel_hdmi_get_config;
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if (IS_VALLEYVIEW(dev)) {
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if (IS_CHERRYVIEW(dev)) {
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intel_encoder->pre_enable = chv_hdmi_pre_enable;
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intel_encoder->enable = vlv_enable_hdmi;
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} else if (IS_VALLEYVIEW(dev)) {
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intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
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intel_encoder->pre_enable = vlv_hdmi_pre_enable;
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intel_encoder->enable = vlv_enable_hdmi;
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