MIPS: Check Loongson3 LL/SC errata workaround correctness
When Loongson3 LL/SC errata workarounds are enabled (ie.
CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) run a tool to scan through the
compiled kernel & ensure that the workaround is applied correctly. That
is, ensure that:
- Every LL or LLD instruction is preceded by a sync instruction.
- Any branches from within an LL/SC loop to outside of that loop
target a sync instruction.
Reasoning for these conditions can be found by reading the comment above
the definition of __SYNC_loongson3_war in arch/mips/include/asm/sync.h.
This tool will help ensure that we don't inadvertently introduce code
paths that miss the required workarounds.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
alistair/sunxi64-5.5-dsi
Paul Burton
parent
4dee90d7b5
commit
e4acfbc18f
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@ -14,6 +14,9 @@
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archscripts: scripts_basic
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$(Q)$(MAKE) $(build)=arch/mips/tools elf-entry
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ifeq ($(CONFIG_CPU_LOONGSON3_WORKAROUNDS),y)
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$(Q)$(MAKE) $(build)=arch/mips/tools loongson3-llsc-check
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endif
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$(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs
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KBUILD_DEFCONFIG := 32r2el_defconfig
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@ -3,7 +3,8 @@
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# Post-link MIPS pass
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# ===========================================================================
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#
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# 1. Insert relocations into vmlinux
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# 1. Check that Loongson3 LL/SC workarounds are applied correctly
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# 2. Insert relocations into vmlinux
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PHONY := __archpost
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__archpost:
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@ -11,6 +12,10 @@ __archpost:
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-include include/config/auto.conf
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include scripts/Kbuild.include
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CMD_LS3_LLSC = arch/mips/tools/loongson3-llsc-check
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quiet_cmd_ls3_llsc = LLSCCHK $@
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cmd_ls3_llsc = $(CMD_LS3_LLSC) $@
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CMD_RELOCS = arch/mips/boot/tools/relocs
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quiet_cmd_relocs = RELOCS $@
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cmd_relocs = $(CMD_RELOCS) $@
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@ -19,6 +24,9 @@ quiet_cmd_relocs = RELOCS $@
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vmlinux: FORCE
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@true
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ifeq ($(CONFIG_CPU_LOONGSON3_WORKAROUNDS),y)
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$(call if_changed,ls3_llsc)
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endif
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ifeq ($(CONFIG_RELOCATABLE),y)
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$(call if_changed,relocs)
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endif
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@ -1 +1,2 @@
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elf-entry
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loongson3-llsc-check
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@ -3,3 +3,8 @@ hostprogs-y := elf-entry
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PHONY += elf-entry
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elf-entry: $(obj)/elf-entry
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@:
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hostprogs-$(CONFIG_CPU_LOONGSON3_WORKAROUNDS) += loongson3-llsc-check
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PHONY += loongson3-llsc-check
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loongson3-llsc-check: $(obj)/loongson3-llsc-check
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@:
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@ -0,0 +1,307 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <byteswap.h>
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#include <elf.h>
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#include <endian.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#ifdef be32toh
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/* If libc provides le{16,32,64}toh() then we'll use them */
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#elif BYTE_ORDER == LITTLE_ENDIAN
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# define le16toh(x) (x)
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# define le32toh(x) (x)
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# define le64toh(x) (x)
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#elif BYTE_ORDER == BIG_ENDIAN
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# define le16toh(x) bswap_16(x)
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# define le32toh(x) bswap_32(x)
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# define le64toh(x) bswap_64(x)
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#endif
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/* MIPS opcodes, in bits 31:26 of an instruction */
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#define OP_SPECIAL 0x00
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#define OP_REGIMM 0x01
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#define OP_BEQ 0x04
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#define OP_BNE 0x05
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#define OP_BLEZ 0x06
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#define OP_BGTZ 0x07
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#define OP_BEQL 0x14
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#define OP_BNEL 0x15
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#define OP_BLEZL 0x16
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#define OP_BGTZL 0x17
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#define OP_LL 0x30
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#define OP_LLD 0x34
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#define OP_SC 0x38
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#define OP_SCD 0x3c
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/* Bits 20:16 of OP_REGIMM instructions */
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#define REGIMM_BLTZ 0x00
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#define REGIMM_BGEZ 0x01
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#define REGIMM_BLTZL 0x02
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#define REGIMM_BGEZL 0x03
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#define REGIMM_BLTZAL 0x10
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#define REGIMM_BGEZAL 0x11
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#define REGIMM_BLTZALL 0x12
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#define REGIMM_BGEZALL 0x13
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/* Bits 5:0 of OP_SPECIAL instructions */
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#define SPECIAL_SYNC 0x0f
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static void usage(FILE *f)
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{
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fprintf(f, "Usage: loongson3-llsc-check /path/to/vmlinux\n");
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}
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static int se16(uint16_t x)
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{
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return (int16_t)x;
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}
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static bool is_ll(uint32_t insn)
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{
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switch (insn >> 26) {
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case OP_LL:
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case OP_LLD:
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return true;
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default:
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return false;
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}
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}
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static bool is_sc(uint32_t insn)
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{
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switch (insn >> 26) {
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case OP_SC:
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case OP_SCD:
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return true;
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default:
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return false;
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}
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}
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static bool is_sync(uint32_t insn)
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{
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/* Bits 31:11 should all be zeroes */
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if (insn >> 11)
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return false;
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/* Bits 5:0 specify the SYNC special encoding */
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if ((insn & 0x3f) != SPECIAL_SYNC)
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return false;
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return true;
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}
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static bool is_branch(uint32_t insn, int *off)
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{
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switch (insn >> 26) {
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case OP_BEQ:
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case OP_BEQL:
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case OP_BNE:
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case OP_BNEL:
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case OP_BGTZ:
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case OP_BGTZL:
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case OP_BLEZ:
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case OP_BLEZL:
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*off = se16(insn) + 1;
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return true;
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case OP_REGIMM:
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switch ((insn >> 16) & 0x1f) {
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case REGIMM_BGEZ:
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case REGIMM_BGEZL:
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case REGIMM_BGEZAL:
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case REGIMM_BGEZALL:
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case REGIMM_BLTZ:
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case REGIMM_BLTZL:
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case REGIMM_BLTZAL:
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case REGIMM_BLTZALL:
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*off = se16(insn) + 1;
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return true;
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default:
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return false;
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}
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default:
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return false;
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}
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}
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static int check_ll(uint64_t pc, uint32_t *code, size_t sz)
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{
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ssize_t i, max, sc_pos;
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int off;
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/*
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* Every LL must be preceded by a sync instruction in order to ensure
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* that instruction reordering doesn't allow a prior memory access to
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* execute after the LL & cause erroneous results.
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*/
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if (!is_sync(le32toh(code[-1]))) {
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fprintf(stderr, "%" PRIx64 ": LL not preceded by sync\n", pc);
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return -EINVAL;
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}
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/* Find the matching SC instruction */
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max = sz / 4;
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for (sc_pos = 0; sc_pos < max; sc_pos++) {
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if (is_sc(le32toh(code[sc_pos])))
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break;
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}
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if (sc_pos >= max) {
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fprintf(stderr, "%" PRIx64 ": LL has no matching SC\n", pc);
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return -EINVAL;
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}
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/*
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* Check branches within the LL/SC loop target sync instructions,
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* ensuring that speculative execution can't generate memory accesses
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* due to instructions outside of the loop.
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*/
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for (i = 0; i < sc_pos; i++) {
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if (!is_branch(le32toh(code[i]), &off))
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continue;
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/*
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* If the branch target is within the LL/SC loop then we don't
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* need to worry about it.
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*/
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if ((off >= -i) && (off <= sc_pos))
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continue;
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/* If the branch targets a sync instruction we're all good... */
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if (is_sync(le32toh(code[i + off])))
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continue;
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/* ...but if not, we have a problem */
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fprintf(stderr, "%" PRIx64 ": Branch target not a sync\n",
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pc + (i * 4));
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return -EINVAL;
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}
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return 0;
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}
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static int check_code(uint64_t pc, uint32_t *code, size_t sz)
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{
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int err = 0;
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if (sz % 4) {
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fprintf(stderr, "%" PRIx64 ": Section size not a multiple of 4\n",
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pc);
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err = -EINVAL;
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sz -= (sz % 4);
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}
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if (is_ll(le32toh(code[0]))) {
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fprintf(stderr, "%" PRIx64 ": First instruction in section is an LL\n",
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pc);
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err = -EINVAL;
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}
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#define advance() ( \
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code++, \
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pc += 4, \
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sz -= 4 \
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)
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/*
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* Skip the first instructionm allowing check_ll to look backwards
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* unconditionally.
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*/
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advance();
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/* Now scan through the code looking for LL instructions */
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for (; sz; advance()) {
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if (is_ll(le32toh(code[0])))
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err |= check_ll(pc, code, sz);
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}
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return err;
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}
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int main(int argc, char *argv[])
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{
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int vmlinux_fd, status, err, i;
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const char *vmlinux_path;
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struct stat st;
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Elf64_Ehdr *eh;
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Elf64_Shdr *sh;
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void *vmlinux;
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status = EXIT_FAILURE;
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if (argc < 2) {
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usage(stderr);
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goto out_ret;
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}
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vmlinux_path = argv[1];
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vmlinux_fd = open(vmlinux_path, O_RDONLY);
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if (vmlinux_fd == -1) {
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perror("Unable to open vmlinux");
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goto out_ret;
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}
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err = fstat(vmlinux_fd, &st);
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if (err) {
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perror("Unable to stat vmlinux");
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goto out_close;
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}
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vmlinux = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, vmlinux_fd, 0);
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if (vmlinux == MAP_FAILED) {
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perror("Unable to mmap vmlinux");
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goto out_close;
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}
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eh = vmlinux;
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if (memcmp(eh->e_ident, ELFMAG, SELFMAG)) {
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fprintf(stderr, "vmlinux is not an ELF?\n");
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goto out_munmap;
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}
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if (eh->e_ident[EI_CLASS] != ELFCLASS64) {
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fprintf(stderr, "vmlinux is not 64b?\n");
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goto out_munmap;
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}
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if (eh->e_ident[EI_DATA] != ELFDATA2LSB) {
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fprintf(stderr, "vmlinux is not little endian?\n");
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goto out_munmap;
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}
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for (i = 0; i < le16toh(eh->e_shnum); i++) {
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sh = vmlinux + le64toh(eh->e_shoff) + (i * le16toh(eh->e_shentsize));
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if (sh->sh_type != SHT_PROGBITS)
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continue;
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if (!(sh->sh_flags & SHF_EXECINSTR))
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continue;
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err = check_code(le64toh(sh->sh_addr),
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vmlinux + le64toh(sh->sh_offset),
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le64toh(sh->sh_size));
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if (err)
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goto out_munmap;
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}
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status = EXIT_SUCCESS;
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out_munmap:
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munmap(vmlinux, st.st_size);
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out_close:
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close(vmlinux_fd);
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out_ret:
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return status;
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}
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