arm64: zynqmp: SoC CLK changes for v4.20
This patchset adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlu8k7oACgkQykllyylKDCFmPACfewJHUsKUhaX77Ew+Pup5tFzC GHgAn1Xb2fJF+9D4CSB+iwdQNPltuhBg =QShK -----END PGP SIGNATURE----- Merge tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx into next/drivers arm64: zynqmp: SoC CLK changes for v4.20 This patchset adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. * tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx: drivers: clk: Add ZynqMP clock driver dt-bindings: clock: Add bindings for ZynqMP clock driver firmware: xilinx: Add zynqmp IOCTL API for device control Documentation: xilinx: Add documentation for eemi APIs Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
e4c080a10a
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@ -17,6 +17,53 @@ Required properties:
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- "smc" : SMC #0, following the SMCCC
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- "hvc" : HVC #0, following the SMCCC
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--------------------------------------------------------------------------
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Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
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Zynq MPSoC firmware interface
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--------------------------------------------------------------------------
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The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
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tree. It reads required input clock frequencies from the devicetree and acts
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as clock provider for all clock consumers of PS clocks.
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See clock_bindings.txt for more information on the generic clock bindings.
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Required properties:
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- #clock-cells: Must be 1
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- compatible: Must contain: "xlnx,zynqmp-clk"
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- clocks: List of clock specifiers which are external input
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clocks to the given clock controller. Please refer
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the next section to find the input clocks for a
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given controller.
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- clock-names: List of clock names which are exteral input clocks
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to the given clock controller. Please refer to the
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clock bindings for more details.
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Input clocks for zynqmp Ultrascale+ clock controller:
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The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
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inputs. These required clock inputs are:
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- pss_ref_clk (PS reference clock)
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- video_clk (reference clock for video system )
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- pss_alt_ref_clk (alternative PS reference clock)
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- aux_ref_clk
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- gt_crx_ref_clk (transceiver reference clock)
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The following strings are optional parameters to the 'clock-names' property in
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order to provide an optional (E)MIO clock source:
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- swdt0_ext_clk
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- swdt1_ext_clk
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- gem0_emio_clk
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- gem1_emio_clk
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- gem2_emio_clk
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- gem3_emio_clk
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- mio_clk_XX # with XX = 00..77
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- mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
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Output clocks are registered based on clock information received
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from firmware. Output clocks indexes are mentioned in
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include/dt-bindings/clock/xlnx,zynqmp-clk.h.
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-------
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Example
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-------
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@ -25,5 +72,11 @@ firmware {
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zynqmp_firmware: zynqmp-firmware {
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compatible = "xlnx,zynqmp-firmware";
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method = "smc";
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zynqmp_clk: clock-controller {
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#clock-cells = <1>;
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compatible = "xlnx,zynqmp-clk";
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clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
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clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
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};
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};
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};
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@ -0,0 +1,67 @@
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---------------------------------------------------------------------
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Xilinx Zynq MPSoC EEMI Documentation
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---------------------------------------------------------------------
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Xilinx Zynq MPSoC Firmware Interface
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-------------------------------------
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The zynqmp-firmware node describes the interface to platform firmware.
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ZynqMP has an interface to communicate with secure firmware. Firmware
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driver provides an interface to firmware APIs. Interface APIs can be
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used by any driver to communicate with PMC(Platform Management Controller).
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Embedded Energy Management Interface (EEMI)
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----------------------------------------------
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The embedded energy management interface is used to allow software
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components running across different processing clusters on a chip or
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device to communicate with a power management controller (PMC) on a
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device to issue or respond to power management requests.
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EEMI ops is a structure containing all eemi APIs supported by Zynq MPSoC.
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The zynqmp-firmware driver maintain all EEMI APIs in zynqmp_eemi_ops
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structure. Any driver who want to communicate with PMC using EEMI APIs
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can call zynqmp_pm_get_eemi_ops().
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Example of EEMI ops:
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/* zynqmp-firmware driver maintain all EEMI APIs */
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struct zynqmp_eemi_ops {
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int (*get_api_version)(u32 *version);
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int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
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};
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static const struct zynqmp_eemi_ops eemi_ops = {
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.get_api_version = zynqmp_pm_get_api_version,
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.query_data = zynqmp_pm_query_data,
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};
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Example of EEMI ops usage:
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static const struct zynqmp_eemi_ops *eemi_ops;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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eemi_ops = zynqmp_pm_get_eemi_ops();
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if (!eemi_ops)
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return -ENXIO;
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ret = eemi_ops->query_data(qdata, ret_payload);
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IOCTL
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------
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IOCTL API is for device control and configuration. It is not a system
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IOCTL but it is an EEMI API. This API can be used by master to control
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any device specific configuration. IOCTL definitions can be platform
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specific. This API also manage shared device configuration.
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The following IOCTL IDs are valid for device control:
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- IOCTL_SET_PLL_FRAC_MODE 8
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- IOCTL_GET_PLL_FRAC_MODE 9
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- IOCTL_SET_PLL_FRAC_DATA 10
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- IOCTL_GET_PLL_FRAC_DATA 11
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Refer EEMI API guide [0] for IOCTL specific parameters and other EEMI APIs.
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References
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----------
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[0] Embedded Energy Management Interface (EEMI) API guide:
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https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf
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@ -299,5 +299,6 @@ source "drivers/clk/sunxi-ng/Kconfig"
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source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/ti/Kconfig"
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/zynqmp/Kconfig"
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endmenu
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@ -108,3 +108,4 @@ obj-$(CONFIG_X86) += x86/
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endif
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obj-$(CONFIG_ARCH_ZX) += zte/
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obj-$(CONFIG_ARCH_ZYNQ) += zynq/
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obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
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@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0
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config COMMON_CLK_ZYNQMP
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bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
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depends on ARCH_ZYNQMP || COMPILE_TEST
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depends on ZYNQMP_FIRMWARE
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help
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Support for the Zynqmp Ultrascale clock controller.
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It has a dependency on the PMU firmware.
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Say Y if you want to include clock support.
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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# Zynq Ultrascale+ MPSoC clock specific Makefile
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obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
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@ -0,0 +1,144 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC clock controller
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*
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* Copyright (C) 2016-2018 Xilinx
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*
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* Gated clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-zynqmp.h"
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/**
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* struct clk_gate - gating clock
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* @hw: handle between common and hardware-specific interfaces
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* @flags: hardware-specific flags
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* @clk_id: Id of clock
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*/
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struct zynqmp_clk_gate {
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struct clk_hw hw;
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u8 flags;
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u32 clk_id;
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};
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#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)
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/**
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* zynqmp_clk_gate_enable() - Enable clock
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: 0 on success else error code
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*/
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static int zynqmp_clk_gate_enable(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_enable(clk_id);
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if (ret)
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pr_warn_once("%s() clock enabled failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return ret;
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}
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/*
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* zynqmp_clk_gate_disable() - Disable clock
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* @hw: handle between common and hardware-specific interfaces
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*/
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static void zynqmp_clk_gate_disable(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_disable(clk_id);
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if (ret)
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pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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}
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/**
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* zynqmp_clk_gate_is_enable() - Check clock state
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: 1 if enabled, 0 if disabled else error code
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*/
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static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int state, ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getstate(clk_id, &state);
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if (ret) {
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pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return -EIO;
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}
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return state ? 1 : 0;
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}
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static const struct clk_ops zynqmp_clk_gate_ops = {
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.enable = zynqmp_clk_gate_enable,
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.disable = zynqmp_clk_gate_disable,
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.is_enabled = zynqmp_clk_gate_is_enabled,
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};
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/**
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* zynqmp_clk_register_gate() - Register a gate clock with the clock framework
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* @name: Name of this clock
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* @clk_id: Id of this clock
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
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*
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* Return: clock hardware of the registered clock gate
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*/
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struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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{
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struct zynqmp_clk_gate *gate;
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struct clk_hw *hw;
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int ret;
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struct clk_init_data init;
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/* allocate the gate */
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &zynqmp_clk_gate_ops;
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init.flags = nodes->flag;
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init.parent_names = parents;
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init.num_parents = 1;
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/* struct clk_gate assignments */
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gate->flags = nodes->type_flag;
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gate->hw.init = &init;
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gate->clk_id = clk_id;
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hw = &gate->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(gate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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@ -0,0 +1,141 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC mux
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*
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* Copyright (C) 2016-2018 Xilinx
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-zynqmp.h"
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/*
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* DOC: basic adjustable multiplexer clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is only affected by parent switching. No clk_set_rate support
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* parent - parent is adjustable through clk_set_parent
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*/
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/**
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* struct zynqmp_clk_mux - multiplexer clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @flags: hardware-specific flags
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* @clk_id: Id of clock
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*/
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struct zynqmp_clk_mux {
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struct clk_hw hw;
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u8 flags;
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u32 clk_id;
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};
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#define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
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/**
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* zynqmp_clk_mux_get_parent() - Get parent of clock
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: Parent index
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*/
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static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = mux->clk_id;
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u32 val;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getparent(clk_id, &val);
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if (ret)
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pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
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__func__, clk_name, ret);
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return val;
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}
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/**
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* zynqmp_clk_mux_set_parent() - Set parent of clock
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* @hw: handle between common and hardware-specific interfaces
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* @index: Parent index
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = mux->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_setparent(clk_id, index);
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if (ret)
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pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
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__func__, clk_name, ret);
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return ret;
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}
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static const struct clk_ops zynqmp_clk_mux_ops = {
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.get_parent = zynqmp_clk_mux_get_parent,
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.set_parent = zynqmp_clk_mux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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static const struct clk_ops zynqmp_clk_mux_ro_ops = {
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.get_parent = zynqmp_clk_mux_get_parent,
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};
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/**
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* zynqmp_clk_register_mux() - Register a mux table with the clock
|
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* framework
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* @name: Name of this clock
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* @clk_id: Id of this clock
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
|
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*
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* Return: clock hardware of the registered clock mux
|
||||
*/
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struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
|
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
|
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{
|
||||
struct zynqmp_clk_mux *mux;
|
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struct clk_hw *hw;
|
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struct clk_init_data init;
|
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int ret;
|
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|
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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if (nodes->type_flag & CLK_MUX_READ_ONLY)
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init.ops = &zynqmp_clk_mux_ro_ops;
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else
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init.ops = &zynqmp_clk_mux_ops;
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init.flags = nodes->flag;
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init.parent_names = parents;
|
||||
init.num_parents = num_parents;
|
||||
mux->flags = nodes->type_flag;
|
||||
mux->hw.init = &init;
|
||||
mux->clk_id = clk_id;
|
||||
|
||||
hw = &mux->hw;
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
if (ret) {
|
||||
kfree(hw);
|
||||
hw = ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return hw;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(zynqmp_clk_register_mux);
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Xilinx
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_ZYNQMP_H_
|
||||
#define __LINUX_CLK_ZYNQMP_H_
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <linux/firmware/xlnx-zynqmp.h>
|
||||
|
||||
/* Clock APIs payload parameters */
|
||||
#define CLK_GET_NAME_RESP_LEN 16
|
||||
#define CLK_GET_TOPOLOGY_RESP_WORDS 3
|
||||
#define CLK_GET_PARENTS_RESP_WORDS 3
|
||||
#define CLK_GET_ATTR_RESP_WORDS 1
|
||||
|
||||
enum topology_type {
|
||||
TYPE_INVALID,
|
||||
TYPE_MUX,
|
||||
TYPE_PLL,
|
||||
TYPE_FIXEDFACTOR,
|
||||
TYPE_DIV1,
|
||||
TYPE_DIV2,
|
||||
TYPE_GATE,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clock_topology - Clock topology
|
||||
* @type: Type of topology
|
||||
* @flag: Topology flags
|
||||
* @type_flag: Topology type specific flag
|
||||
*/
|
||||
struct clock_topology {
|
||||
u32 type;
|
||||
u32 flag;
|
||||
u32 type_flag;
|
||||
};
|
||||
|
||||
struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes);
|
||||
|
||||
struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes);
|
||||
|
||||
struct clk_hw *zynqmp_clk_register_divider(const char *name,
|
||||
u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes);
|
||||
|
||||
struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes);
|
||||
|
||||
struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
|
||||
u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,716 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Zynq UltraScale+ MPSoC clock controller
|
||||
*
|
||||
* Copyright (C) 2016-2018 Xilinx
|
||||
*
|
||||
* Based on drivers/clk/zynq/clkc.c
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include "clk-zynqmp.h"
|
||||
|
||||
#define MAX_PARENT 100
|
||||
#define MAX_NODES 6
|
||||
#define MAX_NAME_LEN 50
|
||||
|
||||
#define CLK_TYPE_SHIFT 2
|
||||
|
||||
#define PM_API_PAYLOAD_LEN 3
|
||||
|
||||
#define NA_PARENT 0xFFFFFFFF
|
||||
#define DUMMY_PARENT 0xFFFFFFFE
|
||||
|
||||
#define CLK_TYPE_FIELD_LEN 4
|
||||
#define CLK_TOPOLOGY_NODE_OFFSET 16
|
||||
#define NODES_PER_RESP 3
|
||||
|
||||
#define CLK_TYPE_FIELD_MASK 0xF
|
||||
#define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
|
||||
#define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
|
||||
|
||||
#define CLK_PARENTS_ID_LEN 16
|
||||
#define CLK_PARENTS_ID_MASK 0xFFFF
|
||||
|
||||
/* Flags for parents */
|
||||
#define PARENT_CLK_SELF 0
|
||||
#define PARENT_CLK_NODE1 1
|
||||
#define PARENT_CLK_NODE2 2
|
||||
#define PARENT_CLK_NODE3 3
|
||||
#define PARENT_CLK_NODE4 4
|
||||
#define PARENT_CLK_EXTERNAL 5
|
||||
|
||||
#define END_OF_CLK_NAME "END_OF_CLK"
|
||||
#define END_OF_TOPOLOGY_NODE 1
|
||||
#define END_OF_PARENTS 1
|
||||
#define RESERVED_CLK_NAME ""
|
||||
|
||||
#define CLK_VALID_MASK 0x1
|
||||
|
||||
enum clk_type {
|
||||
CLK_TYPE_OUTPUT,
|
||||
CLK_TYPE_EXTERNAL,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clock_parent - Clock parent
|
||||
* @name: Parent name
|
||||
* @id: Parent clock ID
|
||||
* @flag: Parent flags
|
||||
*/
|
||||
struct clock_parent {
|
||||
char name[MAX_NAME_LEN];
|
||||
int id;
|
||||
u32 flag;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct zynqmp_clock - Clock
|
||||
* @clk_name: Clock name
|
||||
* @valid: Validity flag of clock
|
||||
* @type: Clock type (Output/External)
|
||||
* @node: Clock topology nodes
|
||||
* @num_nodes: Number of nodes present in topology
|
||||
* @parent: Parent of clock
|
||||
* @num_parents: Number of parents of clock
|
||||
*/
|
||||
struct zynqmp_clock {
|
||||
char clk_name[MAX_NAME_LEN];
|
||||
u32 valid;
|
||||
enum clk_type type;
|
||||
struct clock_topology node[MAX_NODES];
|
||||
u32 num_nodes;
|
||||
struct clock_parent parent[MAX_PARENT];
|
||||
u32 num_parents;
|
||||
};
|
||||
|
||||
static const char clk_type_postfix[][10] = {
|
||||
[TYPE_INVALID] = "",
|
||||
[TYPE_MUX] = "_mux",
|
||||
[TYPE_GATE] = "",
|
||||
[TYPE_DIV1] = "_div1",
|
||||
[TYPE_DIV2] = "_div2",
|
||||
[TYPE_FIXEDFACTOR] = "_ff",
|
||||
[TYPE_PLL] = ""
|
||||
};
|
||||
|
||||
static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes)
|
||||
= {
|
||||
[TYPE_INVALID] = NULL,
|
||||
[TYPE_MUX] = zynqmp_clk_register_mux,
|
||||
[TYPE_PLL] = zynqmp_clk_register_pll,
|
||||
[TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor,
|
||||
[TYPE_DIV1] = zynqmp_clk_register_divider,
|
||||
[TYPE_DIV2] = zynqmp_clk_register_divider,
|
||||
[TYPE_GATE] = zynqmp_clk_register_gate
|
||||
};
|
||||
|
||||
static struct zynqmp_clock *clock;
|
||||
static struct clk_hw_onecell_data *zynqmp_data;
|
||||
static unsigned int clock_max_idx;
|
||||
static const struct zynqmp_eemi_ops *eemi_ops;
|
||||
|
||||
/**
|
||||
* zynqmp_is_valid_clock() - Check whether clock is valid or not
|
||||
* @clk_id: Clock index
|
||||
*
|
||||
* Return: 1 if clock is valid, 0 if clock is invalid else error code
|
||||
*/
|
||||
static inline int zynqmp_is_valid_clock(u32 clk_id)
|
||||
{
|
||||
if (clk_id > clock_max_idx)
|
||||
return -ENODEV;
|
||||
|
||||
return clock[clk_id].valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_get_clock_name() - Get name of clock from Clock index
|
||||
* @clk_id: Clock index
|
||||
* @clk_name: Name of clock
|
||||
*
|
||||
* Return: 0 on success else error code
|
||||
*/
|
||||
static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = zynqmp_is_valid_clock(clk_id);
|
||||
if (ret == 1) {
|
||||
strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ret == 0 ? -EINVAL : ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_get_clock_type() - Get type of clock
|
||||
* @clk_id: Clock index
|
||||
* @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
|
||||
*
|
||||
* Return: 0 on success else error code
|
||||
*/
|
||||
static int zynqmp_get_clock_type(u32 clk_id, u32 *type)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = zynqmp_is_valid_clock(clk_id);
|
||||
if (ret == 1) {
|
||||
*type = clock[clk_id].type;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ret == 0 ? -EINVAL : ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
|
||||
* @nclocks: Number of clocks in system/board.
|
||||
*
|
||||
* Call firmware API to get number of clocks.
|
||||
*
|
||||
* Return: 0 on success else error code.
|
||||
*/
|
||||
static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
|
||||
{
|
||||
struct zynqmp_pm_query_data qdata = {0};
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ret;
|
||||
|
||||
qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
|
||||
|
||||
ret = eemi_ops->query_data(qdata, ret_payload);
|
||||
*nclocks = ret_payload[1];
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pm_clock_get_name() - Get the name of clock for given id
|
||||
* @clock_id: ID of the clock to be queried
|
||||
* @name: Name of given clock
|
||||
*
|
||||
* This function is used to get name of clock specified by given
|
||||
* clock ID.
|
||||
*
|
||||
* Return: Returns 0, in case of error name would be 0
|
||||
*/
|
||||
static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
|
||||
{
|
||||
struct zynqmp_pm_query_data qdata = {0};
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
|
||||
qdata.qid = PM_QID_CLOCK_GET_NAME;
|
||||
qdata.arg1 = clock_id;
|
||||
|
||||
eemi_ops->query_data(qdata, ret_payload);
|
||||
memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
|
||||
* @clock_id: ID of the clock to be queried
|
||||
* @index: Node index of clock topology
|
||||
* @topology: Buffer to store nodes in topology and flags
|
||||
*
|
||||
* This function is used to get topology information for the clock
|
||||
* specified by given clock ID.
|
||||
*
|
||||
* This API will return 3 node of topology with a single response. To get
|
||||
* other nodes, master should call same API in loop with new
|
||||
* index till error is returned. E.g First call should have
|
||||
* index 0 which will return nodes 0,1 and 2. Next call, index
|
||||
* should be 3 which will return nodes 3,4 and 5 and so on.
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
|
||||
{
|
||||
struct zynqmp_pm_query_data qdata = {0};
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ret;
|
||||
|
||||
qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
|
||||
qdata.arg1 = clock_id;
|
||||
qdata.arg2 = index;
|
||||
|
||||
ret = eemi_ops->query_data(qdata, ret_payload);
|
||||
memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_clk_register_fixed_factor() - Register fixed factor with the
|
||||
* clock framework
|
||||
* @name: Name of this clock
|
||||
* @clk_id: Clock ID
|
||||
* @parents: Name of this clock's parents
|
||||
* @num_parents: Number of parents
|
||||
* @nodes: Clock topology node
|
||||
*
|
||||
* Return: clock hardware to the registered clock
|
||||
*/
|
||||
struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes)
|
||||
{
|
||||
u32 mult, div;
|
||||
struct clk_hw *hw;
|
||||
struct zynqmp_pm_query_data qdata = {0};
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ret;
|
||||
|
||||
qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
|
||||
qdata.arg1 = clk_id;
|
||||
|
||||
ret = eemi_ops->query_data(qdata, ret_payload);
|
||||
mult = ret_payload[1];
|
||||
div = ret_payload[2];
|
||||
|
||||
hw = clk_hw_register_fixed_factor(NULL, name,
|
||||
parents[0],
|
||||
nodes->flag, mult,
|
||||
div);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
|
||||
* @clock_id: Clock ID
|
||||
* @index: Parent index
|
||||
* @parents: 3 parents of the given clock
|
||||
*
|
||||
* This function is used to get 3 parents for the clock specified by
|
||||
* given clock ID.
|
||||
*
|
||||
* This API will return 3 parents with a single response. To get
|
||||
* other parents, master should call same API in loop with new
|
||||
* parent index till error is returned. E.g First call should have
|
||||
* index 0 which will return parents 0,1 and 2. Next call, index
|
||||
* should be 3 which will return parent 3,4 and 5 and so on.
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
|
||||
{
|
||||
struct zynqmp_pm_query_data qdata = {0};
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ret;
|
||||
|
||||
qdata.qid = PM_QID_CLOCK_GET_PARENTS;
|
||||
qdata.arg1 = clock_id;
|
||||
qdata.arg2 = index;
|
||||
|
||||
ret = eemi_ops->query_data(qdata, ret_payload);
|
||||
memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
|
||||
* @clock_id: Clock ID
|
||||
* @attr: Clock attributes
|
||||
*
|
||||
* This function is used to get clock's attributes(e.g. valid, clock type, etc).
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr)
|
||||
{
|
||||
struct zynqmp_pm_query_data qdata = {0};
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ret;
|
||||
|
||||
qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
|
||||
qdata.arg1 = clock_id;
|
||||
|
||||
ret = eemi_ops->query_data(qdata, ret_payload);
|
||||
memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* __zynqmp_clock_get_topology() - Get topology data of clock from firmware
|
||||
* response data
|
||||
* @topology: Clock topology
|
||||
* @data: Clock topology data received from firmware
|
||||
* @nnodes: Number of nodes
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int __zynqmp_clock_get_topology(struct clock_topology *topology,
|
||||
u32 *data, u32 *nnodes)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
|
||||
if (!(data[i] & CLK_TYPE_FIELD_MASK))
|
||||
return END_OF_TOPOLOGY_NODE;
|
||||
topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
|
||||
topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
|
||||
data[i]);
|
||||
topology[*nnodes].type_flag =
|
||||
FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
|
||||
(*nnodes)++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_clock_get_topology() - Get topology of clock from firmware using
|
||||
* PM_API
|
||||
* @clk_id: Clock index
|
||||
* @topology: Clock topology
|
||||
* @num_nodes: Number of nodes
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_clock_get_topology(u32 clk_id,
|
||||
struct clock_topology *topology,
|
||||
u32 *num_nodes)
|
||||
{
|
||||
int j, ret;
|
||||
u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
|
||||
|
||||
*num_nodes = 0;
|
||||
for (j = 0; j <= MAX_NODES; j += 3) {
|
||||
ret = zynqmp_pm_clock_get_topology(clk_id, j, pm_resp);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = __zynqmp_clock_get_topology(topology, pm_resp, num_nodes);
|
||||
if (ret == END_OF_TOPOLOGY_NODE)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* __zynqmp_clock_get_topology() - Get parents info of clock from firmware
|
||||
* response data
|
||||
* @parents: Clock parents
|
||||
* @data: Clock parents data received from firmware
|
||||
* @nparent: Number of parent
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int __zynqmp_clock_get_parents(struct clock_parent *parents, u32 *data,
|
||||
u32 *nparent)
|
||||
{
|
||||
int i;
|
||||
struct clock_parent *parent;
|
||||
|
||||
for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
|
||||
if (data[i] == NA_PARENT)
|
||||
return END_OF_PARENTS;
|
||||
|
||||
parent = &parents[i];
|
||||
parent->id = data[i] & CLK_PARENTS_ID_MASK;
|
||||
if (data[i] == DUMMY_PARENT) {
|
||||
strcpy(parent->name, "dummy_name");
|
||||
parent->flag = 0;
|
||||
} else {
|
||||
parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
|
||||
if (zynqmp_get_clock_name(parent->id, parent->name))
|
||||
continue;
|
||||
}
|
||||
*nparent += 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
|
||||
* @clk_id: Clock index
|
||||
* @parents: Clock parents
|
||||
* @num_parents: Total number of parents
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
|
||||
u32 *num_parents)
|
||||
{
|
||||
int j = 0, ret;
|
||||
u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
|
||||
|
||||
*num_parents = 0;
|
||||
do {
|
||||
/* Get parents from firmware */
|
||||
ret = zynqmp_pm_clock_get_parents(clk_id, j, pm_resp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = __zynqmp_clock_get_parents(&parents[j], pm_resp,
|
||||
num_parents);
|
||||
if (ret == END_OF_PARENTS)
|
||||
return 0;
|
||||
j += PM_API_PAYLOAD_LEN;
|
||||
} while (*num_parents <= MAX_PARENT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_get_parent_list() - Create list of parents name
|
||||
* @np: Device node
|
||||
* @clk_id: Clock index
|
||||
* @parent_list: List of parent's name
|
||||
* @num_parents: Total number of parents
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id,
|
||||
const char **parent_list, u32 *num_parents)
|
||||
{
|
||||
int i = 0, ret;
|
||||
u32 total_parents = clock[clk_id].num_parents;
|
||||
struct clock_topology *clk_nodes;
|
||||
struct clock_parent *parents;
|
||||
|
||||
clk_nodes = clock[clk_id].node;
|
||||
parents = clock[clk_id].parent;
|
||||
|
||||
for (i = 0; i < total_parents; i++) {
|
||||
if (!parents[i].flag) {
|
||||
parent_list[i] = parents[i].name;
|
||||
} else if (parents[i].flag == PARENT_CLK_EXTERNAL) {
|
||||
ret = of_property_match_string(np, "clock-names",
|
||||
parents[i].name);
|
||||
if (ret < 0)
|
||||
strcpy(parents[i].name, "dummy_name");
|
||||
parent_list[i] = parents[i].name;
|
||||
} else {
|
||||
strcat(parents[i].name,
|
||||
clk_type_postfix[clk_nodes[parents[i].flag - 1].
|
||||
type]);
|
||||
parent_list[i] = parents[i].name;
|
||||
}
|
||||
}
|
||||
|
||||
*num_parents = total_parents;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_register_clk_topology() - Register clock topology
|
||||
* @clk_id: Clock index
|
||||
* @clk_name: Clock Name
|
||||
* @num_parents: Total number of parents
|
||||
* @parent_names: List of parents name
|
||||
*
|
||||
* Return: Returns either clock hardware or error+reason
|
||||
*/
|
||||
static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
|
||||
int num_parents,
|
||||
const char **parent_names)
|
||||
{
|
||||
int j;
|
||||
u32 num_nodes;
|
||||
char *clk_out = NULL;
|
||||
struct clock_topology *nodes;
|
||||
struct clk_hw *hw = NULL;
|
||||
|
||||
nodes = clock[clk_id].node;
|
||||
num_nodes = clock[clk_id].num_nodes;
|
||||
|
||||
for (j = 0; j < num_nodes; j++) {
|
||||
/*
|
||||
* Clock name received from firmware is output clock name.
|
||||
* Intermediate clock names are postfixed with type of clock.
|
||||
*/
|
||||
if (j != (num_nodes - 1)) {
|
||||
clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name,
|
||||
clk_type_postfix[nodes[j].type]);
|
||||
} else {
|
||||
clk_out = kasprintf(GFP_KERNEL, "%s", clk_name);
|
||||
}
|
||||
|
||||
if (!clk_topology[nodes[j].type])
|
||||
continue;
|
||||
|
||||
hw = (*clk_topology[nodes[j].type])(clk_out, clk_id,
|
||||
parent_names,
|
||||
num_parents,
|
||||
&nodes[j]);
|
||||
if (IS_ERR(hw))
|
||||
pr_warn_once("%s() %s register fail with %ld\n",
|
||||
__func__, clk_name, PTR_ERR(hw));
|
||||
|
||||
parent_names[0] = clk_out;
|
||||
}
|
||||
kfree(clk_out);
|
||||
return hw;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_register_clocks() - Register clocks
|
||||
* @np: Device node
|
||||
*
|
||||
* Return: 0 on success else error code
|
||||
*/
|
||||
static int zynqmp_register_clocks(struct device_node *np)
|
||||
{
|
||||
int ret;
|
||||
u32 i, total_parents = 0, type = 0;
|
||||
const char *parent_names[MAX_PARENT];
|
||||
|
||||
for (i = 0; i < clock_max_idx; i++) {
|
||||
char clk_name[MAX_NAME_LEN];
|
||||
|
||||
/* get clock name, continue to next clock if name not found */
|
||||
if (zynqmp_get_clock_name(i, clk_name))
|
||||
continue;
|
||||
|
||||
/* Check if clock is valid and output clock.
|
||||
* Do not register invalid or external clock.
|
||||
*/
|
||||
ret = zynqmp_get_clock_type(i, &type);
|
||||
if (ret || type != CLK_TYPE_OUTPUT)
|
||||
continue;
|
||||
|
||||
/* Get parents of clock*/
|
||||
if (zynqmp_get_parent_list(np, i, parent_names,
|
||||
&total_parents)) {
|
||||
WARN_ONCE(1, "No parents found for %s\n",
|
||||
clock[i].clk_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
zynqmp_data->hws[i] =
|
||||
zynqmp_register_clk_topology(i, clk_name,
|
||||
total_parents,
|
||||
parent_names);
|
||||
}
|
||||
|
||||
for (i = 0; i < clock_max_idx; i++) {
|
||||
if (IS_ERR(zynqmp_data->hws[i])) {
|
||||
pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
|
||||
clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
|
||||
WARN_ON(1);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_get_clock_info() - Get clock information from firmware using PM_API
|
||||
*/
|
||||
static void zynqmp_get_clock_info(void)
|
||||
{
|
||||
int i, ret;
|
||||
u32 attr, type = 0;
|
||||
|
||||
for (i = 0; i < clock_max_idx; i++) {
|
||||
zynqmp_pm_clock_get_name(i, clock[i].clk_name);
|
||||
if (!strcmp(clock[i].clk_name, RESERVED_CLK_NAME))
|
||||
continue;
|
||||
|
||||
ret = zynqmp_pm_clock_get_attributes(i, &attr);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
clock[i].valid = attr & CLK_VALID_MASK;
|
||||
clock[i].type = attr >> CLK_TYPE_SHIFT ? CLK_TYPE_EXTERNAL :
|
||||
CLK_TYPE_OUTPUT;
|
||||
}
|
||||
|
||||
/* Get topology of all clock */
|
||||
for (i = 0; i < clock_max_idx; i++) {
|
||||
ret = zynqmp_get_clock_type(i, &type);
|
||||
if (ret || type != CLK_TYPE_OUTPUT)
|
||||
continue;
|
||||
|
||||
ret = zynqmp_clock_get_topology(i, clock[i].node,
|
||||
&clock[i].num_nodes);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
ret = zynqmp_clock_get_parents(i, clock[i].parent,
|
||||
&clock[i].num_parents);
|
||||
if (ret)
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_clk_setup() - Setup the clock framework and register clocks
|
||||
* @np: Device node
|
||||
*
|
||||
* Return: 0 on success else error code
|
||||
*/
|
||||
static int zynqmp_clk_setup(struct device_node *np)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
zynqmp_data = kzalloc(sizeof(*zynqmp_data) + sizeof(*zynqmp_data) *
|
||||
clock_max_idx, GFP_KERNEL);
|
||||
if (!zynqmp_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
|
||||
if (!clock) {
|
||||
kfree(zynqmp_data);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
zynqmp_get_clock_info();
|
||||
zynqmp_register_clocks(np);
|
||||
|
||||
zynqmp_data->num = clock_max_idx;
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zynqmp_clock_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
if (!eemi_ops)
|
||||
return -ENXIO;
|
||||
|
||||
ret = zynqmp_clk_setup(dev->of_node);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id zynqmp_clock_of_match[] = {
|
||||
{.compatible = "xlnx,zynqmp-clk"},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
|
||||
|
||||
static struct platform_driver zynqmp_clock_driver = {
|
||||
.driver = {
|
||||
.name = "zynqmp_clock",
|
||||
.of_match_table = zynqmp_clock_of_match,
|
||||
},
|
||||
.probe = zynqmp_clock_probe,
|
||||
};
|
||||
module_platform_driver(zynqmp_clock_driver);
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Zynq UltraScale+ MPSoC Divider support
|
||||
*
|
||||
* Copyright (C) 2016-2018 Xilinx
|
||||
*
|
||||
* Adjustable divider clock implementation
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include "clk-zynqmp.h"
|
||||
|
||||
/*
|
||||
* DOC: basic adjustable divider clock that cannot gate
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
|
||||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_zynqmp_clk_divider(_hw) \
|
||||
container_of(_hw, struct zynqmp_clk_divider, hw)
|
||||
|
||||
#define CLK_FRAC BIT(13) /* has a fractional parent */
|
||||
|
||||
/**
|
||||
* struct zynqmp_clk_divider - adjustable divider clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @flags: Hardware specific flags
|
||||
* @clk_id: Id of clock
|
||||
* @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
|
||||
*/
|
||||
struct zynqmp_clk_divider {
|
||||
struct clk_hw hw;
|
||||
u8 flags;
|
||||
u32 clk_id;
|
||||
u32 div_type;
|
||||
};
|
||||
|
||||
static inline int zynqmp_divider_get_val(unsigned long parent_rate,
|
||||
unsigned long rate)
|
||||
{
|
||||
return DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @parent_rate: rate of parent clock
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 clk_id = divider->clk_id;
|
||||
u32 div_type = divider->div_type;
|
||||
u32 div, value;
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
ret = eemi_ops->clock_getdivider(clk_id, &div);
|
||||
|
||||
if (ret)
|
||||
pr_warn_once("%s() get divider failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
|
||||
if (div_type == TYPE_DIV1)
|
||||
value = div & 0xFFFF;
|
||||
else
|
||||
value = div >> 16;
|
||||
|
||||
return DIV_ROUND_UP_ULL(parent_rate, value);
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_clk_divider_round_rate() - Round rate of divider clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @rate: rate of clock to be set
|
||||
* @prate: rate of parent clock
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 clk_id = divider->clk_id;
|
||||
u32 div_type = divider->div_type;
|
||||
u32 bestdiv;
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
/* if read only, just return current value */
|
||||
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
|
||||
ret = eemi_ops->clock_getdivider(clk_id, &bestdiv);
|
||||
|
||||
if (ret)
|
||||
pr_warn_once("%s() get divider failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
if (div_type == TYPE_DIV1)
|
||||
bestdiv = bestdiv & 0xFFFF;
|
||||
else
|
||||
bestdiv = bestdiv >> 16;
|
||||
|
||||
return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
|
||||
}
|
||||
|
||||
bestdiv = zynqmp_divider_get_val(*prate, rate);
|
||||
|
||||
if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&
|
||||
(divider->flags & CLK_FRAC))
|
||||
bestdiv = rate % *prate ? 1 : bestdiv;
|
||||
*prate = rate * bestdiv;
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_clk_divider_set_rate() - Set rate of divider clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @rate: rate of clock to be set
|
||||
* @parent_rate: rate of parent clock
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 clk_id = divider->clk_id;
|
||||
u32 div_type = divider->div_type;
|
||||
u32 value, div;
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
value = zynqmp_divider_get_val(parent_rate, rate);
|
||||
if (div_type == TYPE_DIV1) {
|
||||
div = value & 0xFFFF;
|
||||
div |= 0xffff << 16;
|
||||
} else {
|
||||
div = 0xffff;
|
||||
div |= value << 16;
|
||||
}
|
||||
|
||||
ret = eemi_ops->clock_setdivider(clk_id, div);
|
||||
|
||||
if (ret)
|
||||
pr_warn_once("%s() set divider failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct clk_ops zynqmp_clk_divider_ops = {
|
||||
.recalc_rate = zynqmp_clk_divider_recalc_rate,
|
||||
.round_rate = zynqmp_clk_divider_round_rate,
|
||||
.set_rate = zynqmp_clk_divider_set_rate,
|
||||
};
|
||||
|
||||
/**
|
||||
* zynqmp_clk_register_divider() - Register a divider clock
|
||||
* @name: Name of this clock
|
||||
* @clk_id: Id of clock
|
||||
* @parents: Name of this clock's parents
|
||||
* @num_parents: Number of parents
|
||||
* @nodes: Clock topology node
|
||||
*
|
||||
* Return: clock hardware to registered clock divider
|
||||
*/
|
||||
struct clk_hw *zynqmp_clk_register_divider(const char *name,
|
||||
u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes)
|
||||
{
|
||||
struct zynqmp_clk_divider *div;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
int ret;
|
||||
|
||||
/* allocate the divider */
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &zynqmp_clk_divider_ops;
|
||||
init.flags = nodes->flag;
|
||||
init.parent_names = parents;
|
||||
init.num_parents = 1;
|
||||
|
||||
/* struct clk_divider assignments */
|
||||
div->flags = nodes->type_flag;
|
||||
div->hw.init = &init;
|
||||
div->clk_id = clk_id;
|
||||
div->div_type = nodes->type;
|
||||
|
||||
hw = &div->hw;
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
if (ret) {
|
||||
kfree(div);
|
||||
hw = ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return hw;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(zynqmp_clk_register_divider);
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Zynq UltraScale+ MPSoC PLL driver
|
||||
*
|
||||
* Copyright (C) 2016-2018 Xilinx
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include "clk-zynqmp.h"
|
||||
|
||||
/**
|
||||
* struct zynqmp_pll - PLL clock
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
* @clk_id: PLL clock ID
|
||||
*/
|
||||
struct zynqmp_pll {
|
||||
struct clk_hw hw;
|
||||
u32 clk_id;
|
||||
};
|
||||
|
||||
#define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
|
||||
|
||||
#define PLL_FBDIV_MIN 25
|
||||
#define PLL_FBDIV_MAX 125
|
||||
|
||||
#define PS_PLL_VCO_MIN 1500000000
|
||||
#define PS_PLL_VCO_MAX 3000000000UL
|
||||
|
||||
enum pll_mode {
|
||||
PLL_MODE_INT,
|
||||
PLL_MODE_FRAC,
|
||||
};
|
||||
|
||||
#define FRAC_OFFSET 0x8
|
||||
#define PLLFCFG_FRAC_EN BIT(31)
|
||||
#define FRAC_DIV BIT(16) /* 2^16 */
|
||||
|
||||
/**
|
||||
* zynqmp_pll_get_mode() - Get mode of PLL
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
*
|
||||
* Return: Mode of PLL
|
||||
*/
|
||||
static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
|
||||
{
|
||||
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
|
||||
u32 clk_id = clk->clk_id;
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0,
|
||||
ret_payload);
|
||||
if (ret)
|
||||
pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
|
||||
return ret_payload[1];
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pll_set_mode() - Set the PLL mode
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
* @on: Flag to determine the mode
|
||||
*/
|
||||
static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
|
||||
{
|
||||
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
|
||||
u32 clk_id = clk->clk_id;
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
int ret;
|
||||
u32 mode;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
if (on)
|
||||
mode = PLL_MODE_FRAC;
|
||||
else
|
||||
mode = PLL_MODE_INT;
|
||||
|
||||
ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL);
|
||||
if (ret)
|
||||
pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pll_round_rate() - Round a clock frequency
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
* @rate: Desired clock frequency
|
||||
* @prate: Clock frequency of parent clock
|
||||
*
|
||||
* Return: Frequency closest to @rate the hardware can generate
|
||||
*/
|
||||
static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
u32 fbdiv;
|
||||
long rate_div, f;
|
||||
|
||||
/* Enable the fractional mode if needed */
|
||||
rate_div = (rate * FRAC_DIV) / *prate;
|
||||
f = rate_div % FRAC_DIV;
|
||||
zynqmp_pll_set_mode(hw, !!f);
|
||||
|
||||
if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
|
||||
if (rate > PS_PLL_VCO_MAX) {
|
||||
fbdiv = rate / PS_PLL_VCO_MAX;
|
||||
rate = rate / (fbdiv + 1);
|
||||
}
|
||||
if (rate < PS_PLL_VCO_MIN) {
|
||||
fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
|
||||
rate = rate * fbdiv;
|
||||
}
|
||||
return rate;
|
||||
}
|
||||
|
||||
fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
|
||||
fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
|
||||
return *prate * fbdiv;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pll_recalc_rate() - Recalculate clock frequency
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
* @parent_rate: Clock frequency of parent clock
|
||||
*
|
||||
* Return: Current clock frequency
|
||||
*/
|
||||
static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
|
||||
u32 clk_id = clk->clk_id;
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 fbdiv, data;
|
||||
unsigned long rate, frac;
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
ret = eemi_ops->clock_getdivider(clk_id, &fbdiv);
|
||||
if (ret)
|
||||
pr_warn_once("%s() get divider failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
|
||||
rate = parent_rate * fbdiv;
|
||||
if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
|
||||
eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0,
|
||||
ret_payload);
|
||||
data = ret_payload[1];
|
||||
frac = (parent_rate * data) / FRAC_DIV;
|
||||
rate = rate + frac;
|
||||
}
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pll_set_rate() - Set rate of PLL
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
* @rate: Frequency of clock to be set
|
||||
* @parent_rate: Clock frequency of parent clock
|
||||
*
|
||||
* Set PLL divider to set desired rate.
|
||||
*
|
||||
* Returns: rate which is set on success else error code
|
||||
*/
|
||||
static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
|
||||
u32 clk_id = clk->clk_id;
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 fbdiv;
|
||||
long rate_div, frac, m, f;
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
|
||||
rate_div = (rate * FRAC_DIV) / parent_rate;
|
||||
m = rate_div / FRAC_DIV;
|
||||
f = rate_div % FRAC_DIV;
|
||||
m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
|
||||
rate = parent_rate * m;
|
||||
frac = (parent_rate * f) / FRAC_DIV;
|
||||
|
||||
ret = eemi_ops->clock_setdivider(clk_id, m);
|
||||
if (ret)
|
||||
pr_warn_once("%s() set divider failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
|
||||
eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
|
||||
|
||||
return rate + frac;
|
||||
}
|
||||
|
||||
fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
|
||||
fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
|
||||
ret = eemi_ops->clock_setdivider(clk_id, fbdiv);
|
||||
if (ret)
|
||||
pr_warn_once("%s() set divider failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
|
||||
return parent_rate * fbdiv;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pll_is_enabled() - Check if a clock is enabled
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
*
|
||||
* Return: 1 if the clock is enabled, 0 otherwise
|
||||
*/
|
||||
static int zynqmp_pll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 clk_id = clk->clk_id;
|
||||
unsigned int state;
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
ret = eemi_ops->clock_getstate(clk_id, &state);
|
||||
if (ret) {
|
||||
pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return state ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pll_enable() - Enable clock
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
*
|
||||
* Return: 0 on success else error code
|
||||
*/
|
||||
static int zynqmp_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 clk_id = clk->clk_id;
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
if (zynqmp_pll_is_enabled(hw))
|
||||
return 0;
|
||||
|
||||
ret = eemi_ops->clock_enable(clk_id);
|
||||
if (ret)
|
||||
pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pll_disable() - Disable clock
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
*/
|
||||
static void zynqmp_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct zynqmp_pll *clk = to_zynqmp_pll(hw);
|
||||
const char *clk_name = clk_hw_get_name(hw);
|
||||
u32 clk_id = clk->clk_id;
|
||||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
if (!zynqmp_pll_is_enabled(hw))
|
||||
return;
|
||||
|
||||
ret = eemi_ops->clock_disable(clk_id);
|
||||
if (ret)
|
||||
pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
}
|
||||
|
||||
static const struct clk_ops zynqmp_pll_ops = {
|
||||
.enable = zynqmp_pll_enable,
|
||||
.disable = zynqmp_pll_disable,
|
||||
.is_enabled = zynqmp_pll_is_enabled,
|
||||
.round_rate = zynqmp_pll_round_rate,
|
||||
.recalc_rate = zynqmp_pll_recalc_rate,
|
||||
.set_rate = zynqmp_pll_set_rate,
|
||||
};
|
||||
|
||||
/**
|
||||
* zynqmp_clk_register_pll() - Register PLL with the clock framework
|
||||
* @name: PLL name
|
||||
* @clk_id: Clock ID
|
||||
* @parents: Name of this clock's parents
|
||||
* @num_parents: Number of parents
|
||||
* @nodes: Clock topology node
|
||||
*
|
||||
* Return: clock hardware to the registered clock
|
||||
*/
|
||||
struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
|
||||
const char * const *parents,
|
||||
u8 num_parents,
|
||||
const struct clock_topology *nodes)
|
||||
{
|
||||
struct zynqmp_pll *pll;
|
||||
struct clk_hw *hw;
|
||||
struct clk_init_data init;
|
||||
int ret;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &zynqmp_pll_ops;
|
||||
init.flags = nodes->flag;
|
||||
init.parent_names = parents;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
pll->hw.init = &init;
|
||||
pll->clk_id = clk_id;
|
||||
|
||||
hw = &pll->hw;
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
if (ret) {
|
||||
kfree(pll);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
|
||||
if (ret < 0)
|
||||
pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
|
@ -428,6 +428,47 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_is_valid_ioctl() - Check whether IOCTL ID is valid or not
|
||||
* @ioctl_id: IOCTL ID
|
||||
*
|
||||
* Return: 1 if IOCTL is valid else 0
|
||||
*/
|
||||
static inline int zynqmp_is_valid_ioctl(u32 ioctl_id)
|
||||
{
|
||||
switch (ioctl_id) {
|
||||
case IOCTL_SET_PLL_FRAC_MODE:
|
||||
case IOCTL_GET_PLL_FRAC_MODE:
|
||||
case IOCTL_SET_PLL_FRAC_DATA:
|
||||
case IOCTL_GET_PLL_FRAC_DATA:
|
||||
return 1;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* zynqmp_pm_ioctl() - PM IOCTL API for device control and configs
|
||||
* @node_id: Node ID of the device
|
||||
* @ioctl_id: ID of the requested IOCTL
|
||||
* @arg1: Argument 1 to requested IOCTL call
|
||||
* @arg2: Argument 2 to requested IOCTL call
|
||||
* @out: Returned output value
|
||||
*
|
||||
* This function calls IOCTL to firmware for device control and configuration.
|
||||
*
|
||||
* Return: Returns status, either success or error+reason
|
||||
*/
|
||||
static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2,
|
||||
u32 *out)
|
||||
{
|
||||
if (!zynqmp_is_valid_ioctl(ioctl_id))
|
||||
return -EINVAL;
|
||||
|
||||
return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, ioctl_id,
|
||||
arg1, arg2, out);
|
||||
}
|
||||
|
||||
static const struct zynqmp_eemi_ops eemi_ops = {
|
||||
.get_api_version = zynqmp_pm_get_api_version,
|
||||
.query_data = zynqmp_pm_query_data,
|
||||
|
|
@ -440,6 +481,7 @@ static const struct zynqmp_eemi_ops eemi_ops = {
|
|||
.clock_getrate = zynqmp_pm_clock_getrate,
|
||||
.clock_setparent = zynqmp_pm_clock_setparent,
|
||||
.clock_getparent = zynqmp_pm_clock_getparent,
|
||||
.ioctl = zynqmp_pm_ioctl,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -0,0 +1,116 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Xilinx Zynq MPSoC Firmware layer
|
||||
*
|
||||
* Copyright (C) 2014-2018 Xilinx, Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
|
||||
#define _DT_BINDINGS_CLK_ZYNQMP_H
|
||||
|
||||
#define IOPLL 0
|
||||
#define RPLL 1
|
||||
#define APLL 2
|
||||
#define DPLL 3
|
||||
#define VPLL 4
|
||||
#define IOPLL_TO_FPD 5
|
||||
#define RPLL_TO_FPD 6
|
||||
#define APLL_TO_LPD 7
|
||||
#define DPLL_TO_LPD 8
|
||||
#define VPLL_TO_LPD 9
|
||||
#define ACPU 10
|
||||
#define ACPU_HALF 11
|
||||
#define DBF_FPD 12
|
||||
#define DBF_LPD 13
|
||||
#define DBG_TRACE 14
|
||||
#define DBG_TSTMP 15
|
||||
#define DP_VIDEO_REF 16
|
||||
#define DP_AUDIO_REF 17
|
||||
#define DP_STC_REF 18
|
||||
#define GDMA_REF 19
|
||||
#define DPDMA_REF 20
|
||||
#define DDR_REF 21
|
||||
#define SATA_REF 22
|
||||
#define PCIE_REF 23
|
||||
#define GPU_REF 24
|
||||
#define GPU_PP0_REF 25
|
||||
#define GPU_PP1_REF 26
|
||||
#define TOPSW_MAIN 27
|
||||
#define TOPSW_LSBUS 28
|
||||
#define GTGREF0_REF 29
|
||||
#define LPD_SWITCH 30
|
||||
#define LPD_LSBUS 31
|
||||
#define USB0_BUS_REF 32
|
||||
#define USB1_BUS_REF 33
|
||||
#define USB3_DUAL_REF 34
|
||||
#define USB0 35
|
||||
#define USB1 36
|
||||
#define CPU_R5 37
|
||||
#define CPU_R5_CORE 38
|
||||
#define CSU_SPB 39
|
||||
#define CSU_PLL 40
|
||||
#define PCAP 41
|
||||
#define IOU_SWITCH 42
|
||||
#define GEM_TSU_REF 43
|
||||
#define GEM_TSU 44
|
||||
#define GEM0_REF 45
|
||||
#define GEM1_REF 46
|
||||
#define GEM2_REF 47
|
||||
#define GEM3_REF 48
|
||||
#define GEM0_TX 49
|
||||
#define GEM1_TX 50
|
||||
#define GEM2_TX 51
|
||||
#define GEM3_TX 52
|
||||
#define QSPI_REF 53
|
||||
#define SDIO0_REF 54
|
||||
#define SDIO1_REF 55
|
||||
#define UART0_REF 56
|
||||
#define UART1_REF 57
|
||||
#define SPI0_REF 58
|
||||
#define SPI1_REF 59
|
||||
#define NAND_REF 60
|
||||
#define I2C0_REF 61
|
||||
#define I2C1_REF 62
|
||||
#define CAN0_REF 63
|
||||
#define CAN1_REF 64
|
||||
#define CAN0 65
|
||||
#define CAN1 66
|
||||
#define DLL_REF 67
|
||||
#define ADMA_REF 68
|
||||
#define TIMESTAMP_REF 69
|
||||
#define AMS_REF 70
|
||||
#define PL0_REF 71
|
||||
#define PL1_REF 72
|
||||
#define PL2_REF 73
|
||||
#define PL3_REF 74
|
||||
#define WDT 75
|
||||
#define IOPLL_INT 76
|
||||
#define IOPLL_PRE_SRC 77
|
||||
#define IOPLL_HALF 78
|
||||
#define IOPLL_INT_MUX 79
|
||||
#define IOPLL_POST_SRC 80
|
||||
#define RPLL_INT 81
|
||||
#define RPLL_PRE_SRC 82
|
||||
#define RPLL_HALF 83
|
||||
#define RPLL_INT_MUX 84
|
||||
#define RPLL_POST_SRC 85
|
||||
#define APLL_INT 86
|
||||
#define APLL_PRE_SRC 87
|
||||
#define APLL_HALF 88
|
||||
#define APLL_INT_MUX 89
|
||||
#define APLL_POST_SRC 90
|
||||
#define DPLL_INT 91
|
||||
#define DPLL_PRE_SRC 92
|
||||
#define DPLL_HALF 93
|
||||
#define DPLL_INT_MUX 94
|
||||
#define DPLL_POST_SRC 95
|
||||
#define VPLL_INT 96
|
||||
#define VPLL_PRE_SRC 97
|
||||
#define VPLL_HALF 98
|
||||
#define VPLL_INT_MUX 99
|
||||
#define VPLL_POST_SRC 100
|
||||
#define CAN0_MIO 101
|
||||
#define CAN1_MIO 102
|
||||
|
||||
#endif
|
||||
|
|
@ -34,7 +34,8 @@
|
|||
|
||||
enum pm_api_id {
|
||||
PM_GET_API_VERSION = 1,
|
||||
PM_QUERY_DATA = 35,
|
||||
PM_IOCTL = 34,
|
||||
PM_QUERY_DATA,
|
||||
PM_CLOCK_ENABLE,
|
||||
PM_CLOCK_DISABLE,
|
||||
PM_CLOCK_GETSTATE,
|
||||
|
|
@ -71,6 +72,7 @@ enum pm_query_id {
|
|||
PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
|
||||
PM_QID_CLOCK_GET_PARENTS,
|
||||
PM_QID_CLOCK_GET_ATTRIBUTES,
|
||||
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -99,6 +101,7 @@ struct zynqmp_eemi_ops {
|
|||
int (*clock_getrate)(u32 clock_id, u64 *rate);
|
||||
int (*clock_setparent)(u32 clock_id, u32 parent_id);
|
||||
int (*clock_getparent)(u32 clock_id, u32 *parent_id);
|
||||
int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
|
||||
};
|
||||
|
||||
#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
|
||||
|
|
|
|||
Loading…
Reference in New Issue