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msm: 8x60: setup correct handlers for private interrupts 

Private Peripheral interrupts could be edge triggered or level triggered
depending on the platform. Initialize handlers for these in board file.

Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
hifive-unleashed-5.1
Abhijeet Dharmapurikar 2010-02-01 12:30:28 -08:00 committed by Daniel Walker
parent 569fb6e3e6
commit e4fbb68f45
1 changed files with 1 additions and 1 deletions
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arch/arm/mach-msm/board-msm8x60.c
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@ -44,7 +44,7 @@ static void __init msm8x60_init_irq(void)
{
unsigned int i;
gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
gic_cpu_init(0, MSM_QGIC_CPU_BASE);