powerpc/virtex: Add Xilinx ML510 reference design support
Signed-off-by: Roderick Colenbrander <thunderbird2k@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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@ -156,7 +156,7 @@ config YOSEMITE
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# This option enables support for the IBM PPC440GX evaluation board.
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# This option enables support for the IBM PPC440GX evaluation board.
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config XILINX_VIRTEX440_GENERIC_BOARD
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config XILINX_VIRTEX440_GENERIC_BOARD
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bool "Generic Xilinx Virtex 440 board"
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bool "Generic Xilinx Virtex 5 FXT board support"
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depends on 44x
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depends on 44x
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default n
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default n
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select XILINX_VIRTEX_5_FXT
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select XILINX_VIRTEX_5_FXT
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@ -171,6 +171,17 @@ config XILINX_VIRTEX440_GENERIC_BOARD
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Most Virtex 5 designs should use this unless it needs to do some
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Most Virtex 5 designs should use this unless it needs to do some
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special configuration at board probe time.
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special configuration at board probe time.
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config XILINX_ML510
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bool "Xilinx ML510 extra support"
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depends on XILINX_VIRTEX440_GENERIC_BOARD
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select PPC_PCI_CHOICE
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select XILINX_PCI if PCI
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select PPC_INDIRECT_PCI if PCI
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select PPC_I8259 if PCI
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help
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This option enables extra support for features on the Xilinx ML510
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board. The ML510 has a PCI bus with ALI south bridge.
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config PPC44x_SIMPLE
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config PPC44x_SIMPLE
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bool "Simple PowerPC 44x board support"
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bool "Simple PowerPC 44x board support"
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depends on 44x
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depends on 44x
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@ -4,3 +4,4 @@ obj-$(CONFIG_EBONY) += ebony.o
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obj-$(CONFIG_SAM440EP) += sam440ep.o
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obj-$(CONFIG_SAM440EP) += sam440ep.o
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obj-$(CONFIG_WARP) += warp.o
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obj-$(CONFIG_WARP) += warp.o
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obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
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obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
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obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
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29
arch/powerpc/platforms/44x/virtex_ml510.c
Normal file
29
arch/powerpc/platforms/44x/virtex_ml510.c
Normal file
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@ -0,0 +1,29 @@
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#include <asm/i8259.h>
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#include <linux/pci.h>
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#include "44x.h"
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/**
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* ml510_ail_quirk
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*/
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static void __devinit ml510_ali_quirk(struct pci_dev *dev)
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{
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/* Enable the IDE controller */
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pci_write_config_byte(dev, 0x58, 0x4c);
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/* Assign irq 14 to the primary ide channel */
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pci_write_config_byte(dev, 0x44, 0x0d);
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/* Assign irq 15 to the secondary ide channel */
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pci_write_config_byte(dev, 0x75, 0x0f);
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/* Set the ide controller in native mode */
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pci_write_config_byte(dev, 0x09, 0xff);
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/* INTB = disabled, INTA = disabled */
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pci_write_config_byte(dev, 0x48, 0x00);
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/* INTD = disabled, INTC = disabled */
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pci_write_config_byte(dev, 0x4a, 0x00);
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/* Audio = INT7, Modem = disabled. */
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pci_write_config_byte(dev, 0x4b, 0x60);
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/* USB = INT7 */
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pci_write_config_byte(dev, 0x74, 0x06);
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}
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DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
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@ -257,6 +257,11 @@ static void __init xilinx_i8259_setup_cascade(void)
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i8259_init(cascade_node, 0);
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i8259_init(cascade_node, 0);
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set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
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set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
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/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
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/* This looks like a dirty hack to me --gcl */
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outb(0xc0, 0x4d0);
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outb(0xc0, 0x4d1);
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out:
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out:
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of_node_put(cascade_node);
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of_node_put(cascade_node);
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}
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}
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