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Here are the main MIPS changes for 4.19. 

An overview of the general architecture changes:
 
   - Massive DMA ops refactoring from Christoph Hellwig (huzzah for
     deleting crufty code!).
 
   - We introduce NT_MIPS_DSP & NT_MIPS_FP_MODE ELF notes & corresponding
     regsets to expose DSP ASE & floating point mode state respectively,
     both for live debugging & core dumps.
 
   - We better optimize our code by hard-coding cpu_has_* macros at
     compile time where their values are known due to the ISA revision
     that the kernel build is targeting.
 
   - The EJTAG exception handler now better handles SMP systems, where it
     was previously possible for CPUs to clobber a register value saved
     by another CPU.
 
   - Our implementation of memset() gained a couple of fixes for MIPSr6
     systems to return correct values in some cases where stores fault.
 
   - We now implement ioremap_wc() using the uncached-accelerated cache
     coherency attribute where supported, which is detected during boot,
     and fall back to plain uncached access where necessary. The
     MIPS-specific (and unused in tree) ioremap_uncached_accelerated() &
     ioremap_cacheable_cow() are removed.
 
   - The prctl(PR_SET_FP_MODE, ...) syscall is better supported for SMP
     systems by reworking the way we ensure remote CPUs that may be
     running threads within the affected process switch mode.
 
   - Systems using the MIPS Coherence Manager will now set the
     MIPS_IC_SNOOPS_REMOTE flag to avoid some unnecessary cache
     maintenance overhead when flushing the icache.
 
   - A few fixes were made for building with clang/LLVM, which
     now sucessfully builds kernels for many of our platforms.
 
   - Miscellaneous cleanups all over.
 
 And some platform-specific changes:
 
   - ar7 gained stubs for a few clock API functions to fix build failures
     for some drivers.
 
   - ath79 gained support for a few new SoCs, a few fixes & better
     gpio-keys support.
 
   - Ci20 now exposes its SPI bus using the spi-gpio driver.
 
   - The generic platform can now auto-detect a suitable value for
     PHYS_OFFSET based upon the memory map described by the device tree,
     allowing us to avoid wasting memory on page book-keeping for systems
     where RAM starts at a non-zero physical address.
 
   - Ingenic systems using the jz4740 platform code now link their
     vmlinuz higher to allow for kernels of a realistic size.
 
   - Loongson32 now builds the kernel targeting MIPSr1 rather than MIPSr2
     to avoid CPU errata.
 
   - Loongson64 gains a couple of fixes, a workaround for a write
     buffering issue & support for the Loongson 3A R3.1 CPU.
 
   - Malta now uses the piix4-poweroff driver to handle powering down.
 
   - Microsemi Ocelot gained support for its SPI bus & NOR flash, its
     second MDIO bus and can now be supported by a FIT/.itb image.
 
   - Octeon saw a bunch of header cleanups which remove a lot of
     duplicate or unused code.
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Merge tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton:
 "Here are the main MIPS changes for 4.19.

  An overview of the general architecture changes:

   - Massive DMA ops refactoring from Christoph Hellwig (huzzah for
     deleting crufty code!).

   - We introduce NT_MIPS_DSP & NT_MIPS_FP_MODE ELF notes &
     corresponding regsets to expose DSP ASE & floating point mode state
     respectively, both for live debugging & core dumps.

   - We better optimize our code by hard-coding cpu_has_* macros at
     compile time where their values are known due to the ISA revision
     that the kernel build is targeting.

   - The EJTAG exception handler now better handles SMP systems, where
     it was previously possible for CPUs to clobber a register value
     saved by another CPU.

   - Our implementation of memset() gained a couple of fixes for MIPSr6
     systems to return correct values in some cases where stores fault.

   - We now implement ioremap_wc() using the uncached-accelerated cache
     coherency attribute where supported, which is detected during boot,
     and fall back to plain uncached access where necessary. The
     MIPS-specific (and unused in tree) ioremap_uncached_accelerated() &
     ioremap_cacheable_cow() are removed.

   - The prctl(PR_SET_FP_MODE, ...) syscall is better supported for SMP
     systems by reworking the way we ensure remote CPUs that may be
     running threads within the affected process switch mode.

   - Systems using the MIPS Coherence Manager will now set the
     MIPS_IC_SNOOPS_REMOTE flag to avoid some unnecessary cache
     maintenance overhead when flushing the icache.

   - A few fixes were made for building with clang/LLVM, which now
     sucessfully builds kernels for many of our platforms.

   - Miscellaneous cleanups all over.

  And some platform-specific changes:

   - ar7 gained stubs for a few clock API functions to fix build
     failures for some drivers.

   - ath79 gained support for a few new SoCs, a few fixes & better
     gpio-keys support.

   - Ci20 now exposes its SPI bus using the spi-gpio driver.

   - The generic platform can now auto-detect a suitable value for
     PHYS_OFFSET based upon the memory map described by the device tree,
     allowing us to avoid wasting memory on page book-keeping for
     systems where RAM starts at a non-zero physical address.

   - Ingenic systems using the jz4740 platform code now link their
     vmlinuz higher to allow for kernels of a realistic size.

   - Loongson32 now builds the kernel targeting MIPSr1 rather than
     MIPSr2 to avoid CPU errata.

   - Loongson64 gains a couple of fixes, a workaround for a write
     buffering issue & support for the Loongson 3A R3.1 CPU.

   - Malta now uses the piix4-poweroff driver to handle powering down.

   - Microsemi Ocelot gained support for its SPI bus & NOR flash, its
     second MDIO bus and can now be supported by a FIT/.itb image.

   - Octeon saw a bunch of header cleanups which remove a lot of
     duplicate or unused code"

* tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (123 commits)
  MIPS: Remove remnants of UASM_ISA
  MIPS: netlogic: xlr: Remove erroneous check in nlm_fmn_send()
  MIPS: VDSO: Force link endianness
  MIPS: Always specify -EB or -EL when using clang
  MIPS: Use dins to simplify __write_64bit_c0_split()
  MIPS: Use read-write output operand in __write_64bit_c0_split()
  MIPS: Avoid using array as parameter to write_c0_kpgd()
  MIPS: vdso: Allow clang's --target flag in VDSO cflags
  MIPS: genvdso: Remove GOT checks
  MIPS: Remove obsolete MIPS checks for DST node "chosen@0"
  MIPS: generic: Remove input symbols from defconfig
  MIPS: Delete unused code in linux32.c
  MIPS: Remove unused sys_32_mmap2
  MIPS: Remove nabi_no_regargs
  mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123
  mips: dts: mscc: Add spi on Ocelot
  MIPS: Loongson: Merge load addresses
  MIPS: Loongson: Set Loongson32 to MIPS32R1
  MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller
  MIPS: generic: Select MIPS_AUTO_PFN_OFFSET
  ...
hifive-unleashed-5.1
Linus Torvalds 2018-08-13 19:24:32 -07:00
parent 2280a5360e 22f20a1103
commit e5a32b5b21
178 changed files with 2959 additions and 12254 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
View File

@ -3,7 +3,7 @@
Required properties:
- compatible: "qca,ar7100-usb-phy"
- #phys-cells: should be 0
- reset-names: "usb-phy"[, "usb-suspend-override"]
- reset-names: "phy"[, "suspend-override"]
- resets: references to the reset controllers
Example:
@ -11,7 +11,7 @@ Example:
usb-phy {
compatible = "qca,ar7100-usb-phy";
reset-names = "usb-phy", "usb-suspend-override";
reset-names = "phy", "suspend-override";
resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>;

56
arch/mips/Kconfig
View File

@ -16,6 +16,7 @@ config MIPS
select BUILDTIME_EXTABLE_SORT
select CLONE_BACKWARDS
select CPU_PM if CPU_IDLE
select DMA_DIRECT_OPS
select GENERIC_ATOMIC64 if !64BIT
select GENERIC_CLOCKEVENTS
select GENERIC_CMOS_UPDATE
@ -97,6 +98,7 @@ config MIPS_GENERIC
select HW_HAS_PCI
select IRQ_MIPS_CPU
select LIBFDT
select MIPS_AUTO_PFN_OFFSET
select MIPS_CPU_SCACHE
select MIPS_GIC
select MIPS_L1_CACHE_SHIFT_7
@ -193,6 +195,7 @@ config ATH79
select CSRC_R4K
select DMA_NONCOHERENT
select GPIOLIB
select PINCTRL
select HAVE_CLK
select COMMON_CLK
select CLKDEV_LOOKUP
@ -211,6 +214,8 @@ config ATH79
config BMIPS_GENERIC
bool "Broadcom Generic BMIPS kernel"
select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
select ARCH_HAS_PHYS_TO_DMA
select BOOT_RAW
select NO_EXCEPT_FILL
select USE_OF
@ -438,7 +443,6 @@ config MACH_LOONGSON32
config MACH_LOONGSON64
bool "Loongson-2/3 family of machines"
select ARCH_HAS_PHYS_TO_DMA
select SYS_SUPPORTS_ZBOOT
help
This enables the support of Loongson-2/3 family of machines.
@ -662,11 +666,11 @@ config SGI_IP22
config SGI_IP27
bool "SGI IP27 (Origin200/2000)"
select ARCH_HAS_PHYS_TO_DMA
select FW_ARC
select FW_ARC64
select BOOT_ELF64
select DEFAULT_SGI_PARTITION
select DMA_COHERENT
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
select NR_CPUS_DEFAULT_64
@ -721,6 +725,7 @@ config SGI_IP28
config SGI_IP32
bool "SGI IP32 (O2)"
select ARCH_HAS_PHYS_TO_DMA
select FW_ARC
select FW_ARC32
select BOOT_ELF32
@ -743,7 +748,6 @@ config SGI_IP32
config SIBYTE_CRHINE
bool "Sibyte BCM91120C-CRhine"
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@ -753,7 +757,6 @@ config SIBYTE_CRHINE
config SIBYTE_CARMEL
bool "Sibyte BCM91120x-Carmel"
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@ -763,7 +766,6 @@ config SIBYTE_CARMEL
config SIBYTE_CRHONE
bool "Sibyte BCM91125C-CRhone"
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1125
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@ -774,7 +776,6 @@ config SIBYTE_CRHONE
config SIBYTE_RHONE
bool "Sibyte BCM91125E-Rhone"
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1125H
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@ -784,7 +785,6 @@ config SIBYTE_RHONE
config SIBYTE_SWARM
bool "Sibyte BCM91250A-SWARM"
select BOOT_ELF32
select DMA_COHERENT
select HAVE_PATA_PLATFORM
select SIBYTE_SB1250
select SWAP_IO_SPACE
@ -797,7 +797,6 @@ config SIBYTE_SWARM
config SIBYTE_LITTLESUR
bool "Sibyte BCM91250C2-LittleSur"
select BOOT_ELF32
select DMA_COHERENT
select HAVE_PATA_PLATFORM
select SIBYTE_SB1250
select SWAP_IO_SPACE
@ -809,7 +808,6 @@ config SIBYTE_LITTLESUR
config SIBYTE_SENTOSA
bool "Sibyte BCM91250E-Sentosa"
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
@ -819,7 +817,6 @@ config SIBYTE_SENTOSA
config SIBYTE_BIGSUR
bool "Sibyte BCM91480B-BigSur"
select BOOT_ELF32
select DMA_COHERENT
select NR_CPUS_DEFAULT_4
select SIBYTE_BCM1x80
select SWAP_IO_SPACE
@ -895,8 +892,8 @@ config CAVIUM_OCTEON_SOC
bool "Cavium Networks Octeon SoC based boards"
select CEVT_R4K
select ARCH_HAS_PHYS_TO_DMA
select HAS_RAPIDIO
select PHYS_ADDR_T_64BIT
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select EDAC_SUPPORT
@ -945,7 +942,6 @@ config NLM_XLR_BOARD
select PHYS_ADDR_T_64BIT
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select DMA_COHERENT
select NR_CPUS_DEFAULT_32
select CEVT_R4K
select CSRC_R4K
@ -973,7 +969,6 @@ config NLM_XLP_BOARD
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select DMA_COHERENT
select NR_CPUS_DEFAULT_32
select CEVT_R4K
select CSRC_R4K
@ -992,7 +987,6 @@ config MIPS_PARAVIRT
bool "Para-Virtualized guest system"
select CEVT_R4K
select CSRC_R4K
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
@ -1118,12 +1112,14 @@ config DMA_PERDEV_COHERENT
bool
select DMA_MAYBE_COHERENT
config DMA_COHERENT
bool
config DMA_NONCOHERENT
bool
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_SYNC_DMA_FOR_CPU
select NEED_DMA_MAP_STATE
select DMA_NONCOHERENT_MMAP
select DMA_NONCOHERENT_CACHE_SYNC
select DMA_NONCOHERENT_OPS
config SYS_HAS_EARLY_PRINTK
bool
@ -1365,6 +1361,7 @@ choice
config CPU_LOONGSON3
bool "Loongson 3 CPU"
depends on SYS_HAS_CPU_LOONGSON3
select ARCH_HAS_PHYS_TO_DMA
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
@ -1427,7 +1424,8 @@ config CPU_LOONGSON1B
select LEDS_GPIO_REGISTER
help
The Loongson 1B is a 32-bit SoC, which implements the MIPS32
release 2 instruction set.
Release 1 instruction set and part of the MIPS32 Release 2
instruction set.
config CPU_LOONGSON1C
bool "Loongson 1C"
@ -1436,7 +1434,8 @@ config CPU_LOONGSON1C
select LEDS_GPIO_REGISTER
help
The Loongson 1C is a 32-bit SoC, which implements the MIPS32
release 2 instruction set.
Release 1 instruction set and part of the MIPS32 Release 2
instruction set.
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
@ -1831,11 +1830,12 @@ config CPU_LOONGSON2
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
select ARCH_HAS_PHYS_TO_DMA
config CPU_LOONGSON1
bool
select CPU_MIPS32
select CPU_MIPSR2
select CPU_MIPSR1
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@ -1979,12 +1979,6 @@ config SYS_HAS_CPU_XLR
config SYS_HAS_CPU_XLP
bool
config MIPS_MALTA_PM
depends on MIPS_MALTA
depends on PCI
bool
default y
#
# CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@ -2994,6 +2988,9 @@ config PGTABLE_LEVELS
default 3 if 64BIT && !PAGE_SIZE_64KB
default 2
config MIPS_AUTO_PFN_OFFSET
bool
source "init/Kconfig"
source "kernel/Kconfig.freezer"
@ -3115,10 +3112,13 @@ config ZONE_DMA32
source "drivers/pcmcia/Kconfig"
config HAS_RAPIDIO
bool
default n
config RAPIDIO
tristate "RapidIO support"
depends on PCI
default n
depends on HAS_RAPIDIO || PCI
help
If you say Y here, the kernel will include drivers and
infrastructure code to support RapidIO interconnect devices.

22
arch/mips/Makefile
View File

@ -122,12 +122,22 @@ cflags-y += -ffreestanding
# are used, so we kludge that here. A bug has been filed at
# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413.
#
# clang doesn't suffer from these issues and our checks against -dumpmachine
# don't work so well when cross compiling, since without providing --target
# clang's output will be based upon the build machine. So for clang we simply
# unconditionally specify -EB or -EL as appropriate.
#
ifeq ($(cc-name),clang)
cflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -EL
else
undef-all += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__
undef-all += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__
predef-be += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__
predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
endif
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
-fno-omit-frame-pointer
@ -155,15 +165,11 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
-Wa,-mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
-Wa,-mips32r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
-Wa,-mips64 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
-Wa,-mips64r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \

3
arch/mips/alchemy/board-gpr.c
View File

@ -34,6 +34,7 @@
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <prom.h>
@ -60,7 +61,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(unsigned char c)
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
}

3
arch/mips/alchemy/board-mtx1.c
View File

@ -31,6 +31,7 @@
#include <mtd/mtd-abi.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/gpio-au1000.h>
#include <asm/mach-au1x00/au1xxx_eth.h>
@ -58,7 +59,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(unsigned char c)
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
}

3
arch/mips/alchemy/board-xxs1500.c
View File

@ -29,6 +29,7 @@
#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h>
#include <prom.h>
@ -55,7 +56,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(unsigned char c)
void prom_putchar(char c)
{
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
}

3
arch/mips/alchemy/devboards/platform.c
View File

@ -14,6 +14,7 @@
#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <asm/setup.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
@ -36,7 +37,7 @@ void __init prom_init(void)
add_memory_region(0, memsize, BOOT_MEM_RAM);
}
void prom_putchar(unsigned char c)
void prom_putchar(char c)
{
if (alchemy_get_cputype() == ALCHEMY_CPU_AU1300)
alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);

29
arch/mips/ar7/clock.c
View File

@ -476,3 +476,32 @@ void __init ar7_init_clocks(void)
/* adjust vbus clock rate */
vbus_clk.rate = bus_clk.rate / 2;
}
/* dummy functions, should not be called */
long clk_round_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL(clk_get_parent);

4
arch/mips/ar7/prom.c
View File

@ -25,6 +25,7 @@
#include <linux/string.h>
#include <linux/io.h>
#include <asm/bootinfo.h>
#include <asm/setup.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
@ -259,10 +260,9 @@ static inline void serial_out(int offset, int value)
writel(value, (void *)PORT(offset));
}
int prom_putchar(char c)
void prom_putchar(char c)
{
while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
;
serial_out(UART_TX, c);
return 1;
}

1
arch/mips/ath25/Kconfig
View File

@ -12,6 +12,7 @@ config SOC_AR2315
config PCI_AR2315
bool "Atheros AR2315 PCI controller support"
depends on SOC_AR2315
select ARCH_HAS_PHYS_TO_DMA
select HW_HAS_PCI
select PCI
default y

6
arch/mips/ath25/board.c
View File

@ -146,10 +146,10 @@ int __init ath25_find_config(phys_addr_t base, unsigned long size)
pr_info("Fixing up empty mac addresses\n");
config->reset_config_gpio = 0xffff;
config->sys_led_gpio = 0xffff;
random_ether_addr(config->wlan0_mac);
eth_random_addr(config->wlan0_mac);
config->wlan0_mac[0] &= ~0x06;
random_ether_addr(config->enet0_mac);
random_ether_addr(config->enet1_mac);
eth_random_addr(config->enet0_mac);
eth_random_addr(config->enet1_mac);
}
}

5
arch/mips/ath25/early_printk.c
View File

@ -9,6 +9,7 @@
#include <linux/mm.h>
#include <linux/io.h>
#include <linux/serial_reg.h>
#include <asm/setup.h>
#include "devices.h"
#include "ar2315_regs.h"
@ -25,7 +26,7 @@ static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg)
return __raw_readl(base + 4 * reg);
}
void prom_putchar(unsigned char ch)
void prom_putchar(char ch)
{
static void __iomem *base;
@ -38,7 +39,7 @@ void prom_putchar(unsigned char ch)
while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
;
prom_uart_wr(base, UART_TX, ch);
prom_uart_wr(base, UART_TX, (unsigned char)ch);
while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
;
}

193
arch/mips/ath79/clock.c
View File

@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(void)
iounmap(dpll_base);
}
static void __init qca953x_clocks_init(void)
{
unsigned long ref_rate;
unsigned long cpu_rate;
unsigned long ddr_rate;
unsigned long ahb_rate;
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
u32 bootstrap;
bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
ref_rate = 40 * 1000 * 1000;
else
ref_rate = 25 * 1000 * 1000;
pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
QCA953X_PLL_CPU_CONFIG_NINT_MASK;
frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
cpu_pll = nint * ref_rate / ref_div;
cpu_pll += frac * (ref_rate >> 6) / ref_div;
cpu_pll /= (1 << out_div);
pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
QCA953X_PLL_DDR_CONFIG_NINT_MASK;
frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
ddr_pll = nint * ref_rate / ref_div;
ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
ddr_pll /= (1 << out_div);
clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
cpu_rate = cpu_pll / (postdiv + 1);
else
cpu_rate = ddr_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
ddr_rate = ddr_pll / (postdiv + 1);
else
ddr_rate = cpu_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
ahb_rate = ddr_pll / (postdiv + 1);
else
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
ath79_add_sys_clkdev("cpu", cpu_rate);
ath79_add_sys_clkdev("ddr", ddr_rate);
ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
}
static void __init qca955x_clocks_init(void)
{
unsigned long ref_rate;
@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(void)
clk_add_alias("uart", NULL, "ref", NULL);
}
static void __init qca956x_clocks_init(void)
{
unsigned long ref_rate;
unsigned long cpu_rate;
unsigned long ddr_rate;
unsigned long ahb_rate;
u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
u32 bootstrap;
/*
* QCA956x timer init workaround has to be applied right before setting
* up the clock. Else, there will be no jiffies
*/
u32 misc;
misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
ref_rate = 40 * 1000 * 1000;
else
ref_rate = 25 * 1000 * 1000;
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
cpu_pll = nint * ref_rate / ref_div;
cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
cpu_pll /= (1 << out_div);
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
ddr_pll = nint * ref_rate / ref_div;
ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
ddr_pll /= (1 << out_div);
clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
cpu_rate = ddr_pll / (postdiv + 1);
else
cpu_rate = cpu_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
ddr_rate = cpu_pll / (postdiv + 1);
else
ddr_rate = ddr_pll / (postdiv + 1);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
ahb_rate = ddr_pll / (postdiv + 1);
else
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
ath79_add_sys_clkdev("cpu", cpu_rate);
ath79_add_sys_clkdev("ddr", ddr_rate);
ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
}
void __init ath79_clocks_init(void)
{
if (soc_is_ar71xx())
@ -450,8 +639,12 @@ void __init ath79_clocks_init(void)
ar933x_clocks_init();
else if (soc_is_ar934x())
ar934x_clocks_init();
else if (soc_is_qca953x())
qca953x_clocks_init();
else if (soc_is_qca955x())
qca955x_clocks_init();
else if (soc_is_qca956x() || soc_is_tp9343())
qca956x_clocks_init();
else
BUG();
}

8
arch/mips/ath79/common.c
View File

@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
else if (soc_is_qca953x())
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else if (soc_is_qca956x() || soc_is_tp9343())
reg = QCA956X_RESET_REG_RESET_MODULE;
else
BUG();
@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
else if (soc_is_qca953x())
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else if (soc_is_qca956x() || soc_is_tp9343())
reg = QCA956X_RESET_REG_RESET_MODULE;
else
BUG();

64
arch/mips/ath79/early_printk.c
View File

@ -13,12 +13,13 @@
#include <linux/errno.h>
#include <linux/serial_reg.h>
#include <asm/addrspace.h>
#include <asm/setup.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ar933x_uart.h>
static void (*_prom_putchar) (unsigned char);
static void (*_prom_putchar)(char);
static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
{
@ -33,31 +34,72 @@ static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
static void prom_putchar_ar71xx(unsigned char ch)
static void prom_putchar_ar71xx(char ch)
{
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
__raw_writel(ch, base + UART_TX * 4);
__raw_writel((unsigned char)ch, base + UART_TX * 4);
prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
}
static void prom_putchar_ar933x(unsigned char ch)
static void prom_putchar_ar933x(char ch)
{
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR);
__raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
__raw_writel(AR933X_UART_DATA_TX_CSR | (unsigned char)ch,
base + AR933X_UART_DATA_REG);
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR);
}
static void prom_putchar_dummy(unsigned char ch)
static void prom_putchar_dummy(char ch)
{
/* nothing to do */
}
static void prom_enable_uart(u32 id)
{
void __iomem *gpio_base;
u32 uart_en;
u32 t;
switch (id) {
case REV_ID_MAJOR_AR71XX:
uart_en = AR71XX_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR7240:
case REV_ID_MAJOR_AR7241:
case REV_ID_MAJOR_AR7242:
uart_en = AR724X_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR913X:
uart_en = AR913X_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR9330:
case REV_ID_MAJOR_AR9331:
uart_en = AR933X_GPIO_FUNC_UART_EN;
break;
case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344:
/* TODO */
default:
return;
}
gpio_base = (void __iomem *)KSEG1ADDR(AR71XX_GPIO_BASE);
t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
t |= uart_en;
__raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
}
static void prom_putchar_init(void)
{
void __iomem *base;
@ -76,8 +118,12 @@ static void prom_putchar_init(void)
case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344:
case REV_ID_MAJOR_QCA9533:
case REV_ID_MAJOR_QCA9533_V2:
case REV_ID_MAJOR_QCA9556:
case REV_ID_MAJOR_QCA9558:
case REV_ID_MAJOR_TP9343:
case REV_ID_MAJOR_QCA956X:
_prom_putchar = prom_putchar_ar71xx;
break;
@ -88,11 +134,13 @@ static void prom_putchar_init(void)
default:
_prom_putchar = prom_putchar_dummy;
break;
return;
}
prom_enable_uart(id);
}
void prom_putchar(unsigned char ch)
void prom_putchar(char ch)
{
if (!_prom_putchar)
prom_putchar_init();

35
arch/mips/ath79/setup.c
View File

@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
static void ath79_restart(char *command)
{
local_irq_disable();
ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
for (;;)
if (cpu_wait)
@ -59,6 +60,7 @@ static void __init ath79_detect_sys_type(void)
u32 major;
u32 minor;
u32 rev = 0;
u32 ver = 1;
id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
major = id & REV_ID_MAJOR_MASK;
@ -151,6 +153,17 @@ static void __init ath79_detect_sys_type(void)
rev = id & AR934X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_QCA9533_V2:
ver = 2;
ath79_soc_rev = 2;
/* drop through */
case REV_ID_MAJOR_QCA9533:
ath79_soc = ATH79_SOC_QCA9533;
chip = "9533";
rev = id & QCA953X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_QCA9556:
ath79_soc = ATH79_SOC_QCA9556;
chip = "9556";
@ -163,14 +176,30 @@ static void __init ath79_detect_sys_type(void)
rev = id & QCA955X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_QCA956X:
ath79_soc = ATH79_SOC_QCA956X;
chip = "956X";
rev = id & QCA956X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_TP9343:
ath79_soc = ATH79_SOC_TP9343;
chip = "9343";
rev = id & QCA956X_REV_ID_REVISION_MASK;
break;
default:
panic("ath79: unknown SoC, id:0x%08x", id);
}
ath79_soc_rev = rev;
if (ver == 1)
ath79_soc_rev = rev;
if (soc_is_qca955x())
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
chip, ver, rev);
else if (soc_is_tp9343())
sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
chip, rev);
else
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);

1
arch/mips/bcm63xx/early_printk.c
View File

@ -8,6 +8,7 @@
#include <bcm63xx_io.h>
#include <linux/serial_bcm63xx.h>
#include <asm/setup.h>
static void wait_xfered(void)
{

32
arch/mips/bmips/dma.c
View File

@ -17,7 +17,7 @@
#include <linux/printk.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <dma-coherence.h>
#include <asm/bmips.h>
/*
* BCM338x has configurable address translation windows which allow the
@ -40,7 +40,7 @@ static struct bmips_dma_range *bmips_dma_ranges;
#define FLUSH_RAC 0x100
static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa)
dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t pa)
{
struct bmips_dma_range *r;
@ -52,17 +52,7 @@ static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa)
return pa;
}
dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
{
return bmips_phys_to_dma(dev, virt_to_phys(addr));
}
dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
{
return bmips_phys_to_dma(dev, page_to_phys(page));
}
unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
{
struct bmips_dma_range *r;
@ -74,6 +64,22 @@ unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
return dma_addr;
}
void arch_sync_dma_for_cpu_all(struct device *dev)
{
void __iomem *cbr = BMIPS_GET_CBR();
u32 cfg;
if (boot_cpu_type() != CPU_BMIPS3300 &&
boot_cpu_type() != CPU_BMIPS4350 &&
boot_cpu_type() != CPU_BMIPS4380)
return;
/* Flush stale data out of the readahead cache */
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
__raw_readl(cbr + BMIPS_RAC_CONFIG);
}
static int __init bmips_init_dma_ranges(void)
{
struct device_node *np =

7
arch/mips/bmips/setup.c
View File

@ -202,13 +202,6 @@ void __init device_tree_init(void)
of_node_put(np);
}
int __init plat_of_setup(void)
{
return __dt_register_buses("simple-bus", NULL);
}
arch_initcall(plat_of_setup);
static int __init plat_dev_init(void)
{
of_clk_init(NULL);

54
arch/mips/boot/Makefile
View File

@ -105,28 +105,29 @@ $(obj)/uImage: $(obj)/uImage.$(suffix-y)
# Flattened Image Tree (.itb) images
#
targets += vmlinux.itb
targets += vmlinux.gz.itb
targets += vmlinux.bz2.itb
targets += vmlinux.lzma.itb
targets += vmlinux.lzo.itb
ifeq ($(ADDR_BITS),32)
itb_addr_cells = 1
itb_addr_cells = 1
endif
ifeq ($(ADDR_BITS),64)
itb_addr_cells = 2
itb_addr_cells = 2
endif
quiet_cmd_its_cat = CAT $@
cmd_its_cat = cat $^ >$@
targets += vmlinux.its.S
$(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS))
quiet_cmd_its_cat = CAT $@
cmd_its_cat = cat $(filter-out $(PHONY), $^) >$@
$(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS)) FORCE
$(call if_changed,its_cat)
targets += vmlinux.its
targets += vmlinux.gz.its
targets += vmlinux.bz2.its
targets += vmlinux.lzmo.its
targets += vmlinux.lzo.its
quiet_cmd_cpp_its_S = ITS $@
cmd_cpp_its_S = $(CPP) $(cpp_flags) -P -C -o $@ $< \
-D__ASSEMBLY__ \
cmd_cpp_its_S = $(CPP) -P -C -o $@ $< \
-DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
-DVMLINUX_BINARY="\"$(3)\"" \
-DVMLINUX_COMPRESSION="\"$(2)\"" \
@ -136,19 +137,25 @@ quiet_cmd_cpp_its_S = ITS $@
-DADDR_CELLS=$(itb_addr_cells)
$(obj)/vmlinux.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,none,vmlinux.bin)
$(call if_changed,cpp_its_S,none,vmlinux.bin)
$(obj)/vmlinux.gz.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz)
$(call if_changed,cpp_its_S,gzip,vmlinux.bin.gz)
$(obj)/vmlinux.bz2.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2)
$(call if_changed,cpp_its_S,bzip2,vmlinux.bin.bz2)
$(obj)/vmlinux.lzma.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma)
$(call if_changed,cpp_its_S,lzma,vmlinux.bin.lzma)
$(obj)/vmlinux.lzo.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo)
$(call if_changed,cpp_its_S,lzo,vmlinux.bin.lzo)
targets += vmlinux.itb
targets += vmlinux.gz.itb
targets += vmlinux.bz2.itb
targets += vmlinux.lzma.itb
targets += vmlinux.lzo.itb
quiet_cmd_itb-image = ITB $@
cmd_itb-image = \
@ -162,14 +169,5 @@ quiet_cmd_itb-image = ITB $@
$(obj)/vmlinux.itb: $(obj)/vmlinux.its $(obj)/vmlinux.bin FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.gz.itb: $(obj)/vmlinux.gz.its $(obj)/vmlinux.bin.gz FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.bz2.itb: $(obj)/vmlinux.bz2.its $(obj)/vmlinux.bin.bz2 FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.lzma.itb: $(obj)/vmlinux.lzma.its $(obj)/vmlinux.bin.lzma FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.lzo.itb: $(obj)/vmlinux.lzo.its $(obj)/vmlinux.bin.lzo FORCE
$(obj)/vmlinux.%.itb: $(obj)/vmlinux.%.its $(obj)/vmlinux.bin.% FORCE
$(call if_changed,itb-image,$<)

3
arch/mips/boot/compressed/uart-prom.c
View File

@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
extern void prom_putchar(unsigned char ch);
#include <asm/setup.h>
void putc(char c)
{

19
arch/mips/boot/dts/ingenic/jz4780.dtsi
View File

@ -155,6 +155,25 @@
};
};
spi_gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <2>;
gpio-miso = <&gpe 14 0>;
gpio-sck = <&gpe 15 0>;
gpio-mosi = <&gpe 17 0>;
cs-gpios = <&gpe 16 0
&gpe 18 0>;
spidev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
uart0: serial@10030000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10030000 0x100>;

2
arch/mips/boot/dts/mscc/Makefile
View File

@ -1,3 +1,3 @@
dtb-$(CONFIG_LEGACY_BOARD_OCELOT) += ocelot_pcb123.dtb
dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

32
arch/mips/boot/dts/mscc/ocelot.dtsi
View File

@ -91,6 +91,17 @@
status = "disabled";
};
spi: spi@101000 {
compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x101000 0x100>, <0x3c 0x18>;
interrupts = <9>;
clocks = <&ahb_clk>;
status = "disabled";
};
switch@1010000 {
compatible = "mscc,vsc7514-switch";
reg = <0x1010000 0x10000>,
@ -168,6 +179,9 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
interrupt-controller;
interrupts = <13>;
#interrupt-cells = <2>;
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
@ -178,13 +192,18 @@
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
miim1: miim1 {
pins = "GPIO_14", "GPIO_15";
function = "miim1";
};
};
mdio0: mdio@107009c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x107009c 0x36>, <0x10700f0 0x8>;
reg = <0x107009c 0x24>, <0x10700f0 0x8>;
interrupts = <14>;
status = "disabled";
@ -201,5 +220,16 @@
reg = <3>;
};
};
mdio1: mdio@10700c0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x10700c0 0x24>;
interrupts = <15>;
pinctrl-names = "default";
pinctrl-0 = <&miim1>;
status = "disabled";
};
};
};

10
arch/mips/boot/dts/mscc/ocelot_pcb123.dts
View File

@ -26,6 +26,16 @@
status = "okay";
};
&spi {
status = "okay";
flash@0 {
compatible = "macronix,mx25l25635f", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&mdio0 {
status = "okay";
};

2
arch/mips/boot/dts/qca/ar9132.dtsi
View File

@ -161,7 +161,7 @@
usb_phy: usb-phy {
compatible = "qca,ar7100-usb-phy";
reset-names = "usb-phy", "usb-suspend-override";
reset-names = "phy", "suspend-override";
resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>;

3
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
View File

@ -22,11 +22,10 @@
};
gpio-keys {
compatible = "gpio-keys-polled";
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <20>;
button@0 {
label = "reset";
linux,code = <KEY_RESTART>;

2
arch/mips/boot/dts/qca/ar9331.dtsi
View File

@ -146,7 +146,7 @@
usb_phy: usb-phy {
compatible = "qca,ar7100-usb-phy";
reset-names = "usb-phy", "usb-suspend-override";
reset-names = "phy", "suspend-override";
resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>;

5
arch/mips/boot/dts/qca/ar9331_dpt_module.dts
View File

@ -29,11 +29,10 @@
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "reset";

5
arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts
View File

@ -47,11 +47,10 @@
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "jumpstart";

5
arch/mips/boot/dts/qca/ar9331_omega.dts
View File

@ -29,11 +29,10 @@
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "reset";

5
arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts
View File

@ -47,11 +47,10 @@
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "wps";

61
arch/mips/boot/ecoff.h
View File

@ -2,14 +2,17 @@
/*
* Some ECOFF definitions.
*/
#include <stdint.h>
typedef struct filehdr {
unsigned short f_magic; /* magic number */
unsigned short f_nscns; /* number of sections */
long f_timdat; /* time & date stamp */
long f_symptr; /* file pointer to symbolic header */
long f_nsyms; /* sizeof(symbolic hdr) */
unsigned short f_opthdr; /* sizeof(optional hdr) */
unsigned short f_flags; /* flags */
uint16_t f_magic; /* magic number */
uint16_t f_nscns; /* number of sections */
int32_t f_timdat; /* time & date stamp */
int32_t f_symptr; /* file pointer to symbolic header */
int32_t f_nsyms; /* sizeof(symbolic hdr) */
uint16_t f_opthdr; /* sizeof(optional hdr) */
uint16_t f_flags; /* flags */
} FILHDR;
#define FILHSZ sizeof(FILHDR)
@ -18,32 +21,32 @@ typedef struct filehdr {
typedef struct scnhdr {
char s_name[8]; /* section name */
long s_paddr; /* physical address, aliased s_nlib */
long s_vaddr; /* virtual address */
long s_size; /* section size */
long s_scnptr; /* file ptr to raw data for section */
long s_relptr; /* file ptr to relocation */
long s_lnnoptr; /* file ptr to gp histogram */
unsigned short s_nreloc; /* number of relocation entries */
unsigned short s_nlnno; /* number of gp histogram entries */
long s_flags; /* flags */
int32_t s_paddr; /* physical address, aliased s_nlib */
int32_t s_vaddr; /* virtual address */
int32_t s_size; /* section size */
int32_t s_scnptr; /* file ptr to raw data for section */
int32_t s_relptr; /* file ptr to relocation */
int32_t s_lnnoptr; /* file ptr to gp histogram */
uint16_t s_nreloc; /* number of relocation entries */
uint16_t s_nlnno; /* number of gp histogram entries */
int32_t s_flags; /* flags */
} SCNHDR;
#define SCNHSZ sizeof(SCNHDR)
#define SCNROUND ((long)16)
#define SCNROUND ((int32_t)16)
typedef struct aouthdr {
short magic; /* see above */
short vstamp; /* version stamp */
long tsize; /* text size in bytes, padded to DW bdry*/
long dsize; /* initialized data " " */
long bsize; /* uninitialized data " " */
long entry; /* entry pt. */
long text_start; /* base of text used for this file */
long data_start; /* base of data used for this file */
long bss_start; /* base of bss used for this file */
long gprmask; /* general purpose register mask */
long cprmask[4]; /* co-processor register masks */
long gp_value; /* the gp value used for this object */
int16_t magic; /* see above */
int16_t vstamp; /* version stamp */
int32_t tsize; /* text size in bytes, padded to DW bdry*/
int32_t dsize; /* initialized data " " */
int32_t bsize; /* uninitialized data " " */
int32_t entry; /* entry pt. */
int32_t text_start; /* base of text used for this file */
int32_t data_start; /* base of data used for this file */
int32_t bss_start; /* base of bss used for this file */
int32_t gprmask; /* general purpose register mask */
int32_t cprmask[4]; /* co-processor register masks */
int32_t gp_value; /* the gp value used for this object */
} AOUTHDR;
#define AOUTHSZ sizeof(AOUTHDR)

31
arch/mips/boot/elf2ecoff.c
View File

@ -43,6 +43,8 @@
#include <limits.h>
#include <netinet/in.h>
#include <stdlib.h>
#include <stdint.h>
#include <inttypes.h>
#include "ecoff.h"
@ -55,8 +57,8 @@
/* -------------------------------------------------------------------- */
struct sect {
unsigned long vaddr;
unsigned long len;
uint32_t vaddr;
uint32_t len;
};
int *symTypeTable;
@ -153,16 +155,16 @@ static char *saveRead(int file, off_t offset, off_t len, char *name)
}
#define swab16(x) \
((unsigned short)( \
(((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
(((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
((uint16_t)( \
(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \
(((uint16_t)(x) & (uint16_t)0xff00U) >> 8) ))
#define swab32(x) \
((unsigned int)( \
(((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
(((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \
(((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \
(((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
(((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24) ))
static void convert_elf_hdr(Elf32_Ehdr * e)
{
@ -274,7 +276,7 @@ int main(int argc, char *argv[])
struct aouthdr eah;
struct scnhdr esecs[6];
int infile, outfile;
unsigned long cur_vma = ULONG_MAX;
uint32_t cur_vma = UINT32_MAX;
int addflag = 0;
int nosecs;
@ -518,7 +520,7 @@ int main(int argc, char *argv[])
for (i = 0; i < nosecs; i++) {
printf
("Section %d: %s phys %lx size %lx file offset %lx\n",
("Section %d: %s phys %"PRIx32" size %"PRIx32"\t file offset %"PRIx32"\n",
i, esecs[i].s_name, esecs[i].s_paddr,
esecs[i].s_size, esecs[i].s_scnptr);
}
@ -564,17 +566,16 @@ int main(int argc, char *argv[])
the section can be loaded before copying. */
if (ph[i].p_type == PT_LOAD && ph[i].p_filesz) {
if (cur_vma != ph[i].p_vaddr) {
unsigned long gap =
ph[i].p_vaddr - cur_vma;
uint32_t gap = ph[i].p_vaddr - cur_vma;
char obuf[1024];
if (gap > 65536) {
fprintf(stderr,
"Intersegment gap (%ld bytes) too large.\n",
"Intersegment gap (%"PRId32" bytes) too large.\n",
gap);
exit(1);
}
fprintf(stderr,
"Warning: %ld byte intersegment gap.\n",
"Warning: %d byte intersegment gap.\n",
gap);
memset(obuf, 0, sizeof obuf);
while (gap) {

197
arch/mips/cavium-octeon/dma-octeon.c
View File

@ -11,9 +11,7 @@
* Copyright (C) 2010 Cavium Networks, Inc.
*/
#include <linux/dma-direct.h>
#include <linux/scatterlist.h>
#include <linux/bootmem.h>
#include <linux/export.h>
#include <linux/swiotlb.h>
#include <linux/types.h>
#include <linux/init.h>
@ -24,10 +22,16 @@
#include <asm/octeon/octeon.h>
#ifdef CONFIG_PCI
#include <linux/pci.h>
#include <asm/octeon/pci-octeon.h>
#include <asm/octeon/cvmx-npi-defs.h>
#include <asm/octeon/cvmx-pci-defs.h>
struct octeon_dma_map_ops {
dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
};
static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
{
if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
@ -61,6 +65,11 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
return daddr;
}
static const struct octeon_dma_map_ops octeon_gen1_ops = {
.phys_to_dma = octeon_gen1_phys_to_dma,
.dma_to_phys = octeon_gen1_dma_to_phys,
};
static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
return octeon_hole_phys_to_dma(paddr);
@ -71,6 +80,11 @@ static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
return octeon_hole_dma_to_phys(daddr);
}
static const struct octeon_dma_map_ops octeon_gen2_ops = {
.phys_to_dma = octeon_gen2_phys_to_dma,
.dma_to_phys = octeon_gen2_dma_to_phys,
};
static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
@ -93,6 +107,11 @@ static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
return daddr;
}
static const struct octeon_dma_map_ops octeon_big_ops = {
.phys_to_dma = octeon_big_phys_to_dma,
.dma_to_phys = octeon_big_dma_to_phys,
};
static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
phys_addr_t paddr)
{
@ -121,105 +140,51 @@ static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
return daddr;
}
#endif /* CONFIG_PCI */
static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size, enum dma_data_direction direction,
unsigned long attrs)
{
dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
direction, attrs);
mb();
return daddr;
}
static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction direction, unsigned long attrs)
{
int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
mb();
return r;
}
static void octeon_dma_sync_single_for_device(struct device *dev,
dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
{
swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
mb();
}
static void octeon_dma_sync_sg_for_device(struct device *dev,
struct scatterlist *sg, int nelems, enum dma_data_direction direction)
{
swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
mb();
}
static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
{
void *ret = swiotlb_alloc(dev, size, dma_handle, gfp, attrs);
mb();
return ret;
}
static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
return paddr;
}
static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
{
return daddr;
}
struct octeon_dma_map_ops {
const struct dma_map_ops dma_map_ops;
dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
static const struct octeon_dma_map_ops octeon_small_ops = {
.phys_to_dma = octeon_small_phys_to_dma,
.dma_to_phys = octeon_small_dma_to_phys,
};
static const struct octeon_dma_map_ops *octeon_pci_dma_ops;
void __init octeon_pci_dma_init(void)
{
switch (octeon_dma_bar_type) {
case OCTEON_DMA_BAR_TYPE_PCIE:
octeon_pci_dma_ops = &octeon_gen1_ops;
break;
case OCTEON_DMA_BAR_TYPE_PCIE2:
octeon_pci_dma_ops = &octeon_gen2_ops;
break;
case OCTEON_DMA_BAR_TYPE_BIG:
octeon_pci_dma_ops = &octeon_big_ops;
break;
case OCTEON_DMA_BAR_TYPE_SMALL:
octeon_pci_dma_ops = &octeon_small_ops;
break;
default:
BUG();
}
}
#endif /* CONFIG_PCI */
dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
struct octeon_dma_map_ops,
dma_map_ops);
return ops->phys_to_dma(dev, paddr);
#ifdef CONFIG_PCI
if (dev && dev_is_pci(dev))
return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
#endif
return paddr;
}
EXPORT_SYMBOL(__phys_to_dma);
phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
struct octeon_dma_map_ops,
dma_map_ops);
return ops->dma_to_phys(dev, daddr);
#ifdef CONFIG_PCI
if (dev && dev_is_pci(dev))
return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
#endif
return daddr;
}
EXPORT_SYMBOL(__dma_to_phys);
static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
.dma_map_ops = {
.alloc = octeon_dma_alloc_coherent,
.free = swiotlb_free,
.map_page = octeon_dma_map_page,
.unmap_page = swiotlb_unmap_page,
.map_sg = octeon_dma_map_sg,
.unmap_sg = swiotlb_unmap_sg_attrs,
.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
.sync_single_for_device = octeon_dma_sync_single_for_device,
.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
.sync_sg_for_device = octeon_dma_sync_sg_for_device,
.mapping_error = swiotlb_dma_mapping_error,
.dma_supported = swiotlb_dma_supported
},
.phys_to_dma = octeon_unity_phys_to_dma,
.dma_to_phys = octeon_unity_dma_to_phys
};
char *octeon_swiotlb;
@ -283,52 +248,4 @@ void __init plat_swiotlb_setup(void)
if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
panic("Cannot allocate SWIOTLB buffer");
mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
}
#ifdef CONFIG_PCI
static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
.dma_map_ops = {
.alloc = octeon_dma_alloc_coherent,
.free = swiotlb_free,
.map_page = octeon_dma_map_page,
.unmap_page = swiotlb_unmap_page,
.map_sg = octeon_dma_map_sg,
.unmap_sg = swiotlb_unmap_sg_attrs,
.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
.sync_single_for_device = octeon_dma_sync_single_for_device,
.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
.sync_sg_for_device = octeon_dma_sync_sg_for_device,
.mapping_error = swiotlb_dma_mapping_error,
.dma_supported = swiotlb_dma_supported
},
};
const struct dma_map_ops *octeon_pci_dma_map_ops;
void __init octeon_pci_dma_init(void)
{
switch (octeon_dma_bar_type) {
case OCTEON_DMA_BAR_TYPE_PCIE2:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
break;
case OCTEON_DMA_BAR_TYPE_PCIE:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
break;
case OCTEON_DMA_BAR_TYPE_BIG:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
break;
case OCTEON_DMA_BAR_TYPE_SMALL:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
break;
default:
BUG();
}
octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
}
#endif /* CONFIG_PCI */

5
arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -42,9 +42,6 @@
#include <asm/octeon/cvmx-asxx-defs.h>
#include <asm/octeon/cvmx-dbg-defs.h>
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_asxx_enable(int block);
/**
* Probe RGMII ports and determine the number present
*

7
arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -39,10 +39,7 @@
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsx-defs.h>
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
#include <asm/octeon/cvmx-pcsxx-defs.h>
/**
* Perform initialization required only once for an SGMII port.

8
arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -25,10 +25,6 @@
* Contact Cavium Networks for more information
***********************license end**************************************/
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_spxx_int_msk_enable(int index);
void __cvmx_interrupt_stxx_int_msk_enable(int index);
/*
* Functions for SPI initialization, configuration,
* and monitoring.
@ -41,6 +37,8 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
#include <asm/octeon/cvmx-pip-defs.h>
#include <asm/octeon/cvmx-pko-defs.h>
#include <asm/octeon/cvmx-spxx-defs.h>
#include <asm/octeon/cvmx-stxx-defs.h>
/*
* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI

7
arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -39,12 +39,9 @@
#include <asm/octeon/cvmx-pko-defs.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsx-defs.h>
#include <asm/octeon/cvmx-pcsxx-defs.h>
void __cvmx_interrupt_gmxx_enable(int interface);
void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
int __cvmx_helper_xaui_enumerate(int interface)
{
union cvmx_gmxx_hg2_control gmx_hg2_control;

2
arch/mips/cavium-octeon/octeon-irq.c
View File

@ -814,7 +814,7 @@ static int octeon_irq_ciu_set_affinity(struct irq_data *data,
pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
if (cpumask_test_cpu(cpu, dest) && enable_one) {
enable_one = 0;
enable_one = false;
__set_bit(cd->bit, pen);
} else {
__clear_bit(cd->bit, pen);

4
arch/mips/cavium-octeon/octeon-platform.c
View File

@ -322,6 +322,7 @@ static int __init octeon_ehci_device_init(void)
return 0;
pd = of_find_device_by_node(ehci_node);
of_node_put(ehci_node);
if (!pd)
return 0;
@ -384,6 +385,7 @@ static int __init octeon_ohci_device_init(void)
return 0;
pd = of_find_device_by_node(ohci_node);
of_node_put(ohci_node);
if (!pd)
return 0;
@ -1067,6 +1069,6 @@ end_led:
static int __init octeon_publish_devices(void)
{
return of_platform_bus_probe(NULL, octeon_ids, NULL);
return of_platform_populate(NULL, octeon_ids, NULL, NULL);
}
arch_initcall(octeon_publish_devices);

8
arch/mips/cavium-octeon/setup.c
View File

@ -36,6 +36,7 @@
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/time.h>
#include <asm/octeon/octeon.h>
@ -1108,7 +1109,7 @@ void __init plat_mem_setup(void)
* Emit one character to the boot UART. Exported for use by the
* watchdog timer.
*/
int prom_putchar(char c)
void prom_putchar(char c)
{
uint64_t lsrval;
@ -1119,7 +1120,6 @@ int prom_putchar(char c)
/* Write the byte */
cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
return 1;
}
EXPORT_SYMBOL(prom_putchar);
@ -1154,11 +1154,7 @@ void __init prom_free_prom_memory(void)
}
void __init octeon_fill_mac_addresses(void);
int octeon_prune_device_tree(void);
extern const char __appended_dtb;
extern const char __dtb_octeon_3xxx_begin;
extern const char __dtb_octeon_68xx_begin;
void __init device_tree_init(void)
{
const void *fdt;

2
arch/mips/configs/ci20_defconfig
View File

@ -92,6 +92,8 @@ CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_INGENIC=y
# CONFIG_HWMON is not set

3
arch/mips/configs/generic_defconfig
View File

@ -43,9 +43,6 @@ CONFIG_NETFILTER=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_SCSI=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_HW_RANDOM=y
# CONFIG_HWMON is not set

1
arch/mips/configs/malta_defconfig
View File

@ -317,6 +317,7 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/malta_kvm_defconfig
View File

@ -328,6 +328,7 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/malta_kvm_guest_defconfig
View File

@ -330,6 +330,7 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/malta_qemu_32r6_defconfig
View File

@ -133,6 +133,7 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/maltaaprp_defconfig
View File

@ -133,6 +133,7 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/maltasmvp_defconfig
View File

@ -134,6 +134,7 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/maltasmvp_eva_defconfig
View File

@ -137,6 +137,7 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/maltaup_defconfig
View File

@ -132,6 +132,7 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/configs/maltaup_xpa_defconfig
View File

@ -326,6 +326,7 @@ CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_PIIX4_POWEROFF=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_HWMON is not set
CONFIG_FB=y

1
arch/mips/fw/arc/arc_con.c
View File

@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/console.h>
#include <linux/fs.h>
#include <asm/setup.h>
#include <asm/sgialib.h>
static void prom_console_write(struct console *co, const char *s,

1
arch/mips/fw/arc/promlib.c
View File

@ -9,6 +9,7 @@
#include <linux/kernel.h>
#include <asm/sgialib.h>
#include <asm/bcache.h>
#include <asm/setup.h>
/*
* IP22 boardcache is not compatible with board caches. Thus we disable it

1
arch/mips/fw/sni/sniprom.c
View File

@ -19,6 +19,7 @@
#include <asm/mipsprom.h>
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
#include <asm/setup.h>
/* special SNI prom calls */
/*

12
arch/mips/generic/Kconfig
View File

@ -35,13 +35,13 @@ config LEGACY_BOARD_OCELOT
depends on LEGACY_BOARD_SEAD3=n
select LEGACY_BOARDS
select MSCC_OCELOT
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
config MSCC_OCELOT
bool
select GPIOLIB
select MSCC_OCELOT_IRQ
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
comment "FIT/UHI Boards"
@ -65,6 +65,14 @@ config FIT_IMAGE_FDT_XILFPGA
Enable this to include the FDT for the MIPSfpga platform
from Imagination Technologies in the FIT kernel image.
config FIT_IMAGE_FDT_OCELOT_PCB123
bool "Include FDT for Microsemi Ocelot PCB123"
select MSCC_OCELOT
help
Enable this to include the FDT for the Ocelot PCB123 platform
from Microsemi in the FIT kernel image.
This requires u-boot on the platform.
config VIRT_BOARD_RANCHU
bool "Support Ranchu platform for Android emulator"
help

1
arch/mips/generic/Platform
View File

@ -16,4 +16,5 @@ all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
its-y := vmlinux.its.S
its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
its-$(CONFIG_FIT_IMAGE_FDT_OCELOT_PCB123) += board-ocelot_pcb123.its.S
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S

23
arch/mips/generic/board-ocelot_pcb123.its.S 100644
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/ {
images {
fdt@ocelot_pcb123 {
description = "MSCC Ocelot PCB123 Device Tree";
data = /incbin/("boot/dts/mscc/ocelot_pcb123.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
};
configurations {
conf@ocelot_pcb123 {
description = "Ocelot Linux kernel";
kernel = "kernel@0";
fdt = "fdt@ocelot_pcb123";
};
};
};

14
arch/mips/generic/init.c
View File

@ -14,7 +14,6 @@
#include <linux/init.h>
#include <linux/irqchip.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <asm/bootinfo.h>
#include <asm/fw/fw.h>
@ -204,22 +203,11 @@ void __init arch_init_irq(void)
"mti,cpu-interrupt-controller");
if (!cpu_has_veic && !intc_node)
mips_cpu_irq_init();
of_node_put(intc_node);
irqchip_init();
}
static int __init publish_devices(void)
{
if (!of_have_populated_dt())
panic("Device-tree not present");
if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
panic("Failed to populate DT");
return 0;
}
arch_initcall(publish_devices);
void __init prom_free_prom_memory(void)
{
}

4
arch/mips/generic/yamon-dt.c
View File

@ -27,8 +27,6 @@ __init int yamon_dt_append_cmdline(void *fdt)
/* find or add chosen node */
chosen_off = fdt_path_offset(fdt, "/chosen");
if (chosen_off == -FDT_ERR_NOTFOUND)
chosen_off = fdt_path_offset(fdt, "/chosen@0");
if (chosen_off == -FDT_ERR_NOTFOUND)
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
if (chosen_off < 0) {
@ -220,8 +218,6 @@ __init int yamon_dt_serial_config(void *fdt)
/* find or add chosen node */
chosen_off = fdt_path_offset(fdt, "/chosen");
if (chosen_off == -FDT_ERR_NOTFOUND)
chosen_off = fdt_path_offset(fdt, "/chosen@0");
if (chosen_off == -FDT_ERR_NOTFOUND)
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
if (chosen_off < 0) {

1
arch/mips/include/asm/Kbuild
View File

@ -8,6 +8,7 @@ generic-y += irq_work.h
generic-y += local64.h
generic-y += mcs_spinlock.h
generic-y += mm-arch-hooks.h
generic-y += msi.h
generic-y += parport.h
generic-y += percpu.h
generic-y += preempt.h

195
arch/mips/include/asm/atomic.h
View File

@ -22,6 +22,17 @@
#include <asm/cmpxchg.h>
#include <asm/war.h>
/*
* Using a branch-likely instruction to check the result of an sc instruction
* works around a bug present in R10000 CPUs prior to revision 3.0 that could
* cause ll-sc sequences to execute non-atomically.
*/
#if R10000_LLSC_WAR
# define __scbeqz "beqzl"
#else
# define __scbeqz "beqz"
#endif
#define ATOMIC_INIT(i) { (i) }
/*
@ -44,31 +55,18 @@
#define ATOMIC_OP(op, c_op, asm_op) \
static __inline__ void atomic_##op(int i, atomic_t * v) \
{ \
if (kernel_uses_llsc && R10000_LLSC_WAR) { \
if (kernel_uses_llsc) { \
int temp; \
\
__asm__ __volatile__( \
" .set arch=r4000 \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: ll %0, %1 # atomic_" #op " \n" \
" " #asm_op " %0, %2 \n" \
" sc %0, %1 \n" \
" beqzl %0, 1b \n" \
"\t" __scbeqz " %0, 1b \n" \
" .set mips0 \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
int temp; \
\
do { \
__asm__ __volatile__( \
" .set "MIPS_ISA_LEVEL" \n" \
" ll %0, %1 # atomic_" #op "\n" \
" " #asm_op " %0, %2 \n" \
" sc %0, %1 \n" \
" .set mips0 \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} while (unlikely(!temp)); \
} else { \
unsigned long flags; \
\
@ -83,36 +81,20 @@ static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
{ \
int result; \
\
if (kernel_uses_llsc && R10000_LLSC_WAR) { \
if (kernel_uses_llsc) { \
int temp; \
\
__asm__ __volatile__( \
" .set arch=r4000 \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: ll %1, %2 # atomic_" #op "_return \n" \
" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
" beqzl %0, 1b \n" \
"\t" __scbeqz " %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
int temp; \
\
do { \
__asm__ __volatile__( \
" .set "MIPS_ISA_LEVEL" \n" \
" ll %1, %2 # atomic_" #op "_return \n" \
" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} while (unlikely(!result)); \
\
result = temp; result c_op i; \
} else { \
unsigned long flags; \
\
@ -131,36 +113,20 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
{ \
int result; \
\
if (kernel_uses_llsc && R10000_LLSC_WAR) { \
if (kernel_uses_llsc) { \
int temp; \
\
__asm__ __volatile__( \
" .set arch=r4000 \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: ll %1, %2 # atomic_fetch_" #op " \n" \
" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
" beqzl %0, 1b \n" \
"\t" __scbeqz " %0, 1b \n" \
" move %0, %1 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
int temp; \
\
do { \
__asm__ __volatile__( \
" .set "MIPS_ISA_LEVEL" \n" \
" ll %1, %2 # atomic_fetch_" #op " \n" \
" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} while (unlikely(!result)); \
\
result = temp; \
} else { \
unsigned long flags; \
\
@ -218,38 +184,17 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
smp_mb__before_llsc();
if (kernel_uses_llsc && R10000_LLSC_WAR) {
int temp;
__asm__ __volatile__(
" .set arch=r4000 \n"
"1: ll %1, %2 # atomic_sub_if_positive\n"
" subu %0, %1, %3 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
" .set noreorder \n"
" beqzl %0, 1b \n"
" subu %0, %1, %3 \n"
" .set reorder \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp),
"+" GCC_OFF_SMALL_ASM() (v->counter)
: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
: "memory");
} else if (kernel_uses_llsc) {
if (kernel_uses_llsc) {
int temp;
__asm__ __volatile__(
" .set "MIPS_ISA_LEVEL" \n"
"1: ll %1, %2 # atomic_sub_if_positive\n"
" subu %0, %1, %3 \n"
" move %1, %0 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
" .set noreorder \n"
" beqz %0, 1b \n"
" subu %0, %1, %3 \n"
" .set reorder \n"
" sc %1, %2 \n"
"\t" __scbeqz " %1, 1b \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp),
@ -301,31 +246,18 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
#define ATOMIC64_OP(op, c_op, asm_op) \
static __inline__ void atomic64_##op(long i, atomic64_t * v) \
{ \
if (kernel_uses_llsc && R10000_LLSC_WAR) { \
if (kernel_uses_llsc) { \
long temp; \
\
__asm__ __volatile__( \
" .set arch=r4000 \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: lld %0, %1 # atomic64_" #op " \n" \
" " #asm_op " %0, %2 \n" \
" scd %0, %1 \n" \
" beqzl %0, 1b \n" \
"\t" __scbeqz " %0, 1b \n" \
" .set mips0 \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
long temp; \
\
do { \
__asm__ __volatile__( \
" .set "MIPS_ISA_LEVEL" \n" \
" lld %0, %1 # atomic64_" #op "\n" \
" " #asm_op " %0, %2 \n" \
" scd %0, %1 \n" \
" .set mips0 \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} while (unlikely(!temp)); \
} else { \
unsigned long flags; \
\
@ -340,37 +272,20 @@ static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
{ \
long result; \
\
if (kernel_uses_llsc && R10000_LLSC_WAR) { \
if (kernel_uses_llsc) { \
long temp; \
\
__asm__ __volatile__( \
" .set arch=r4000 \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: lld %1, %2 # atomic64_" #op "_return\n" \
" " #asm_op " %0, %1, %3 \n" \
" scd %0, %2 \n" \
" beqzl %0, 1b \n" \
"\t" __scbeqz " %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
long temp; \
\
do { \
__asm__ __volatile__( \
" .set "MIPS_ISA_LEVEL" \n" \
" lld %1, %2 # atomic64_" #op "_return\n" \
" " #asm_op " %0, %1, %3 \n" \
" scd %0, %2 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"=" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
: "memory"); \
} while (unlikely(!result)); \
\
result = temp; result c_op i; \
} else { \
unsigned long flags; \
\
@ -393,33 +308,16 @@ static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
long temp; \
\
__asm__ __volatile__( \
" .set arch=r4000 \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: lld %1, %2 # atomic64_fetch_" #op "\n" \
" " #asm_op " %0, %1, %3 \n" \
" scd %0, %2 \n" \
" beqzl %0, 1b \n" \
"\t" __scbeqz " %0, 1b \n" \
" move %0, %1 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i)); \
} else if (kernel_uses_llsc) { \
long temp; \
\
do { \
__asm__ __volatile__( \
" .set "MIPS_ISA_LEVEL" \n" \
" lld %1, %2 # atomic64_fetch_" #op "\n" \
" " #asm_op " %0, %1, %3 \n" \
" scd %0, %2 \n" \
" .set mips0 \n" \
: "=&r" (result), "=&r" (temp), \
"=" GCC_OFF_SMALL_ASM() (v->counter) \
: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
: "memory"); \
} while (unlikely(!result)); \
\
result = temp; \
} else { \
unsigned long flags; \
\
@ -478,38 +376,17 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
smp_mb__before_llsc();
if (kernel_uses_llsc && R10000_LLSC_WAR) {
long temp;
__asm__ __volatile__(
" .set arch=r4000 \n"
"1: lld %1, %2 # atomic64_sub_if_positive\n"
" dsubu %0, %1, %3 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
" .set noreorder \n"
" beqzl %0, 1b \n"
" dsubu %0, %1, %3 \n"
" .set reorder \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp),
"=" GCC_OFF_SMALL_ASM() (v->counter)
: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
: "memory");
} else if (kernel_uses_llsc) {
if (kernel_uses_llsc) {
long temp;
__asm__ __volatile__(
" .set "MIPS_ISA_LEVEL" \n"
"1: lld %1, %2 # atomic64_sub_if_positive\n"
" dsubu %0, %1, %3 \n"
" move %1, %0 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
" .set noreorder \n"
" beqz %0, 1b \n"
" dsubu %0, %1, %3 \n"
" .set reorder \n"
" scd %1, %2 \n"
"\t" __scbeqz " %1, 1b \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp),

16
arch/mips/include/asm/bmips.h
View File

@ -123,22 +123,6 @@ static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
barrier();
}
static inline void bmips_post_dma_flush(struct device *dev)
{
void __iomem *cbr = BMIPS_GET_CBR();
u32 cfg;
if (boot_cpu_type() != CPU_BMIPS3300 &&
boot_cpu_type() != CPU_BMIPS4350 &&
boot_cpu_type() != CPU_BMIPS4380)
return;
/* Flush stale data out of the readahead cache */
cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
__raw_readl(cbr + BMIPS_RAC_CONFIG);
}
#endif /* !defined(__ASSEMBLY__) */
#endif /* _ASM_BMIPS_H */

176
arch/mips/include/asm/cpu-features.h
View File

@ -14,39 +14,77 @@
#include <asm/isa-rev.h>
#include <cpu-feature-overrides.h>
#define __ase(ase) (cpu_data[0].ases & (ase))
#define __opt(opt) (cpu_data[0].options & (opt))
/*
* Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during
* boot (typically by cpu_probe()).
*
* Note that these should only be used in cases where a kernel built for an
* older ISA *cannot* run on a CPU which supports the feature in question. For
* example this may be used for features introduced with MIPSr6, since a kernel
* built for an older ISA cannot run on a MIPSr6 CPU. This should not be used
* for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a
* MIPSr2 CPU.
*/
#define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase))
#define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt))
/*
* Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during
* boot (typically by cpu_probe()).
*
* These are for use with features that are optional up until a particular ISA
* revision & then become required.
*/
#define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase))
#define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt))
/*
* Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during
* boot (typically by cpu_probe()).
*
* These are for use with features that are optional up until a particular ISA
* revision & are then removed - ie. no longer present in any CPU implementing
* the given ISA revision.
*/
#define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase))
#define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt))
/*
* SMP assumption: Options of CPU 0 are a superset of all processors.
* This is true for all known MIPS systems.
*/
#ifndef cpu_has_tlb
#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
#define cpu_has_tlb __opt(MIPS_CPU_TLB)
#endif
#ifndef cpu_has_ftlb
#define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB)
#define cpu_has_ftlb __opt(MIPS_CPU_FTLB)
#endif
#ifndef cpu_has_tlbinv
#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
#define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV)
#endif
#ifndef cpu_has_segments
#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
#define cpu_has_segments __opt(MIPS_CPU_SEGMENTS)
#endif
#ifndef cpu_has_eva
#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
#define cpu_has_eva __opt(MIPS_CPU_EVA)
#endif
#ifndef cpu_has_htw
#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
#define cpu_has_htw __opt(MIPS_CPU_HTW)
#endif
#ifndef cpu_has_ldpte
#define cpu_has_ldpte (cpu_data[0].options & MIPS_CPU_LDPTE)
#define cpu_has_ldpte __opt(MIPS_CPU_LDPTE)
#endif
#ifndef cpu_has_rixiex
#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
#define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX)
#endif
#ifndef cpu_has_maar
#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
#define cpu_has_maar __opt(MIPS_CPU_MAAR)
#endif
#ifndef cpu_has_rw_llb
#define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
#define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB)
#endif
/*
@ -59,18 +97,18 @@
#define cpu_has_3kex (!cpu_has_4kex)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
#define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
#define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache 0
#define cpu_has_8k_cache 0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache 0
@ -83,92 +121,92 @@
#define raw_cpu_has_fpu cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
#define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
#define cpu_has_counter __opt(MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
#define cpu_has_watch __opt(MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
#define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
#define cpu_has_vce __opt(MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
#define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
#define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
#define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
#define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
#define cpu_has_ejtag __opt(MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
#define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC)
#endif
#ifndef cpu_has_bp_ghist
#define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST)
#define cpu_has_bp_ghist __opt(MIPS_CPU_BP_GHIST)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc cpu_has_llsc
#endif
#ifndef cpu_has_guestctl0ext
#define cpu_has_guestctl0ext (cpu_data[0].options & MIPS_CPU_GUESTCTL0EXT)
#define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT)
#endif
#ifndef cpu_has_guestctl1
#define cpu_has_guestctl1 (cpu_data[0].options & MIPS_CPU_GUESTCTL1)
#define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1)
#endif
#ifndef cpu_has_guestctl2
#define cpu_has_guestctl2 (cpu_data[0].options & MIPS_CPU_GUESTCTL2)
#define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2)
#endif
#ifndef cpu_has_guestid
#define cpu_has_guestid (cpu_data[0].options & MIPS_CPU_GUESTID)
#define cpu_has_guestid __opt(MIPS_CPU_GUESTID)
#endif
#ifndef cpu_has_drg
#define cpu_has_drg (cpu_data[0].options & MIPS_CPU_DRG)
#define cpu_has_drg __opt(MIPS_CPU_DRG)
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
#define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mips16e2
#define cpu_has_mips16e2 (cpu_data[0].ases & MIPS_ASE_MIPS16E2)
#define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
#define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
#define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS)
#endif
#ifndef cpu_has_rixi
#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
#define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI)
#endif
#ifndef cpu_has_mmips
# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
# define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS)
# else
# define cpu_has_mmips 0
# endif
#endif
#ifndef cpu_has_lpa
#define cpu_has_lpa (cpu_data[0].options & MIPS_CPU_LPA)
#define cpu_has_lpa __opt(MIPS_CPU_LPA)
#endif
#ifndef cpu_has_mvh
#define cpu_has_mvh (cpu_data[0].options & MIPS_CPU_MVH)
#define cpu_has_mvh __opt(MIPS_CPU_MVH)
#endif
#ifndef cpu_has_xpa
#define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh)
@ -338,32 +376,32 @@
#endif
#ifndef cpu_has_dsp
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
#define cpu_has_dsp __ase(MIPS_ASE_DSP)
#endif
#ifndef cpu_has_dsp2
#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
#define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P)
#endif
#ifndef cpu_has_dsp3
#define cpu_has_dsp3 (cpu_data[0].ases & MIPS_ASE_DSP3)
#define cpu_has_dsp3 __ase(MIPS_ASE_DSP3)
#endif
#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
#define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT)
#endif
#ifndef cpu_has_vp
#define cpu_has_vp (cpu_data[0].options & MIPS_CPU_VP)
#define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP)
#endif
#ifndef cpu_has_userlocal
#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
#define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI)
#endif
#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
# define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
@ -405,19 +443,19 @@
#endif
#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
# define cpu_has_vint __opt(MIPS_CPU_VINT)
#elif !defined(cpu_has_vint)
# define cpu_has_vint 0
#endif
#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
# define cpu_has_veic __opt(MIPS_CPU_VEIC)
#elif !defined(cpu_has_veic)
# define cpu_has_veic 0
#endif
#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES)
#endif
#ifndef cpu_dcache_line_size
@ -438,63 +476,63 @@
#endif
#ifndef cpu_has_perf_cntr_intr_bit
#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
#define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI)
#endif
#ifndef cpu_has_vz
#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
#define cpu_has_vz __ase(MIPS_ASE_VZ)
#endif
#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
# define cpu_has_msa __ase(MIPS_ASE_MSA)
#elif !defined(cpu_has_msa)
# define cpu_has_msa 0
#endif
#ifndef cpu_has_ufr
# define cpu_has_ufr (cpu_data[0].options & MIPS_CPU_UFR)
# define cpu_has_ufr __opt(MIPS_CPU_UFR)
#endif
#ifndef cpu_has_fre
# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
# define cpu_has_fre __opt(MIPS_CPU_FRE)
#endif
#ifndef cpu_has_cdmm
# define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
# define cpu_has_cdmm __opt(MIPS_CPU_CDMM)
#endif
#ifndef cpu_has_small_pages
# define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP)
# define cpu_has_small_pages __opt(MIPS_CPU_SP)
#endif
#ifndef cpu_has_nan_legacy
#define cpu_has_nan_legacy (cpu_data[0].options & MIPS_CPU_NAN_LEGACY)
#define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY)
#endif
#ifndef cpu_has_nan_2008
#define cpu_has_nan_2008 (cpu_data[0].options & MIPS_CPU_NAN_2008)
#define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008)
#endif
#ifndef cpu_has_ebase_wg
# define cpu_has_ebase_wg (cpu_data[0].options & MIPS_CPU_EBASE_WG)
# define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG)
#endif
#ifndef cpu_has_badinstr
# define cpu_has_badinstr (cpu_data[0].options & MIPS_CPU_BADINSTR)
# define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR)
#endif
#ifndef cpu_has_badinstrp
# define cpu_has_badinstrp (cpu_data[0].options & MIPS_CPU_BADINSTRP)
# define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP)
#endif
#ifndef cpu_has_contextconfig
# define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC)
# define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC)
#endif
#ifndef cpu_has_perf
# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
# define cpu_has_perf __opt(MIPS_CPU_PERF)
#endif
#if defined(CONFIG_SMP) && (MIPS_ISA_REV >= 6)
#ifdef CONFIG_SMP
/*
* Some systems share FTLB RAMs between threads within a core (siblings in
* kernel parlance). This means that FTLB entries may become invalid at almost
@ -507,7 +545,7 @@
*/
# ifndef cpu_has_shared_ftlb_ram
# define cpu_has_shared_ftlb_ram \
(current_cpu_data.options & MIPS_CPU_SHARED_FTLB_RAM)
__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM)
# endif
/*
@ -524,9 +562,9 @@
*/
# ifndef cpu_has_shared_ftlb_entries
# define cpu_has_shared_ftlb_entries \
(current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)
__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES)
# endif
#endif /* SMP && MIPS_ISA_REV >= 6 */
#endif /* SMP */
#ifndef cpu_has_shared_ftlb_ram
# define cpu_has_shared_ftlb_ram 0
@ -537,7 +575,7 @@
#ifdef CONFIG_MIPS_MT_SMP
# define cpu_has_mipsmt_pertccounters \
(cpu_data[0].options & MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
__isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
#else
# define cpu_has_mipsmt_pertccounters 0
#endif /* CONFIG_MIPS_MT_SMP */

51
arch/mips/include/asm/cpu.h
View File

@ -225,31 +225,32 @@
* Definitions for 7:0 on legacy processors
*/
#define PRID_REV_TX4927 0x0022
#define PRID_REV_TX4937 0x0030
#define PRID_REV_R4400 0x0040
#define PRID_REV_R3000A 0x0030
#define PRID_REV_R3000 0x0020
#define PRID_REV_R2000A 0x0010
#define PRID_REV_TX3912 0x0010
#define PRID_REV_TX3922 0x0030
#define PRID_REV_TX3927 0x0040
#define PRID_REV_VR4111 0x0050
#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
#define PRID_REV_VR4121 0x0060
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
#define PRID_REV_LOONGSON1B 0x0020
#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON3A_R1 0x0005
#define PRID_REV_LOONGSON3B_R1 0x0006
#define PRID_REV_LOONGSON3B_R2 0x0007
#define PRID_REV_LOONGSON3A_R2 0x0008
#define PRID_REV_LOONGSON3A_R3 0x0009
#define PRID_REV_TX4927 0x0022
#define PRID_REV_TX4937 0x0030
#define PRID_REV_R4400 0x0040
#define PRID_REV_R3000A 0x0030
#define PRID_REV_R3000 0x0020
#define PRID_REV_R2000A 0x0010
#define PRID_REV_TX3912 0x0010
#define PRID_REV_TX3922 0x0030
#define PRID_REV_TX3927 0x0040
#define PRID_REV_VR4111 0x0050
#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
#define PRID_REV_VR4121 0x0060
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
#define PRID_REV_LOONGSON1B 0x0020
#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON3A_R1 0x0005
#define PRID_REV_LOONGSON3B_R1 0x0006
#define PRID_REV_LOONGSON3B_R2 0x0007
#define PRID_REV_LOONGSON3A_R2 0x0008
#define PRID_REV_LOONGSON3A_R3_0 0x0009
#define PRID_REV_LOONGSON3A_R3_1 0x000d
/*
* Older processors used to encode processor version and revision in two

6
arch/mips/include/asm/dma-coherence.h
View File

@ -21,10 +21,10 @@ enum coherent_io_user_state {
extern enum coherent_io_user_state coherentio;
extern int hw_coherentio;
#else
#ifdef CONFIG_DMA_COHERENT
#define coherentio IO_COHERENCE_ENABLED
#else
#ifdef CONFIG_DMA_NONCOHERENT
#define coherentio IO_COHERENCE_DISABLED
#else
#define coherentio IO_COHERENCE_ENABLED
#endif
#define hw_coherentio 0
#endif /* CONFIG_DMA_MAYBE_COHERENT */

17
arch/mips/include/asm/dma-direct.h
View File

@ -1 +1,16 @@
#include <asm/dma-coherence.h>
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _MIPS_DMA_DIRECT_H
#define _MIPS_DMA_DIRECT_H 1
static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
if (!dev->dma_mask)
return false;
return addr + size - 1 <= *dev->dma_mask;
}
dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
#endif /* _MIPS_DMA_DIRECT_H */

20
arch/mips/include/asm/dma-mapping.h
View File

@ -2,19 +2,21 @@
#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
#include <linux/scatterlist.h>
#include <asm/dma-coherence.h>
#include <asm/cache.h>
#include <linux/swiotlb.h>
#ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */
#include <dma-coherence.h>
#endif
extern const struct dma_map_ops *mips_dma_map_ops;
extern const struct dma_map_ops jazz_dma_ops;
static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
{
return mips_dma_map_ops;
#if defined(CONFIG_MACH_JAZZ)
return &jazz_dma_ops;
#elif defined(CONFIG_SWIOTLB)
return &swiotlb_dma_ops;
#elif defined(CONFIG_DMA_NONCOHERENT_OPS)
return &dma_noncoherent_ops;
#else
return &dma_direct_ops;
#endif
}
#define arch_setup_dma_ops arch_setup_dma_ops

40
arch/mips/include/asm/io.h
View File

@ -12,6 +12,8 @@
#ifndef _ASM_IO_H
#define _ASM_IO_H
#define ARCH_HAS_IOREMAP_WC
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/types.h>
@ -141,14 +143,14 @@ static inline void * phys_to_virt(unsigned long address)
/*
* ISA I/O bus memory addresses are 1:1 with the physical address.
*/
static inline unsigned long isa_virt_to_bus(volatile void * address)
static inline unsigned long isa_virt_to_bus(volatile void *address)
{
return (unsigned long)address - PAGE_OFFSET;
return virt_to_phys(address);
}
static inline void * isa_bus_to_virt(unsigned long address)
static inline void *isa_bus_to_virt(unsigned long address)
{
return (void *)(address + PAGE_OFFSET);
return phys_to_virt(address);
}
#define isa_page_to_bus page_to_phys
@ -278,15 +280,25 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si
#define ioremap_cache ioremap_cachable
/*
* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
* requests a cachable mapping, ioremap_uncached_accelerated requests a
* mapping using the uncached accelerated mode which isn't supported on
* all processors.
* ioremap_wc - map bus memory into CPU space
* @offset: bus address of the memory
* @size: size of the resource to map
*
* ioremap_wc performs a platform specific sequence of operations to
* make bus memory CPU accessible via the readb/readw/readl/writeb/
* writew/writel functions and the other mmio helpers. The returned
* address is not guaranteed to be usable directly as a virtual
* address.
*
* This version of ioremap ensures that the memory is marked uncachable
* but accelerated by means of write-combining feature. It is specifically
* useful for PCIe prefetchable windows, which may vastly improve a
* communications performance. If it was determined on boot stage, what
* CPU CCA doesn't support UCA, the method shall fall-back to the
* _CACHE_UNCACHED option (see cpu_probe() method).
*/
#define ioremap_cacheable_cow(offset, size) \
__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
#define ioremap_uncached_accelerated(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
#define ioremap_wc(offset, size) \
__ioremap_mode((offset), (size), boot_cpu_data.writecombine)
static inline void iounmap(const volatile void __iomem *addr)
{
@ -590,7 +602,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
*
* This API used to be exported; it now is for arch code internal use only.
*/
#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
#ifdef CONFIG_DMA_NONCOHERENT
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
@ -609,7 +621,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
#define dma_cache_inv(start,size) \
do { (void) (start); (void) (size); } while (0)
#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
#endif /* CONFIG_DMA_NONCOHERENT */
/*
* Read a 32-bit register that requires a 64-bit read cycle on the bus.

3
arch/mips/include/asm/mach-ar7/spaces.h
View File

@ -17,9 +17,6 @@
#define PAGE_OFFSET _AC(0x94000000, UL)
#define PHYS_OFFSET _AC(0x14000000, UL)
#define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */
#define IO_BASE UNCAC_BASE
#include <asm/mach-generic/spaces.h>
#endif /* __ASM_AR7_SPACES_H */

76
arch/mips/include/asm/mach-ath25/dma-coherence.h
View File

@ -1,76 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
*
*/
#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
#define __ASM_MACH_ATH25_DMA_COHERENCE_H
#include <linux/device.h>
/*
* We need some arbitrary non-zero value to be programmed to the BAR1 register
* of PCI host controller to enable DMA. The same value should be used as the
* offset to calculate the physical address of DMA buffer for PCI devices.
*/
#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
static inline dma_addr_t ath25_dev_offset(struct device *dev)
{
#ifdef CONFIG_PCI
extern struct bus_type pci_bus_type;
if (dev && dev->bus == &pci_bus_type)
return AR2315_PCI_HOST_SDRAM_BASEADDR;
#endif
return 0;
}
static inline dma_addr_t
plat_map_dma_mem(struct device *dev, void *addr, size_t size)
{
return virt_to_phys(addr) + ath25_dev_offset(dev);
}
static inline dma_addr_t
plat_map_dma_mem_page(struct device *dev, struct page *page)
{
return page_to_phys(page) + ath25_dev_offset(dev);
}
static inline unsigned long
plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
{
return dma_addr - ath25_dev_offset(dev);
}
static inline void
plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
return 1;
}
static inline int plat_device_is_coherent(struct device *dev)
{
#ifdef CONFIG_DMA_COHERENT
return 1;
#endif
#ifdef CONFIG_DMA_NONCOHERENT
return 0;
#endif
}
static inline void plat_post_dma_flush(struct device *dev)
{
}
#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */

769
arch/mips/include/asm/mach-ath79/ar71xx_regs.h
View File

@ -20,6 +20,10 @@
#include <linux/bitops.h>
#define AR71XX_APB_BASE 0x18000000
#define AR71XX_GE0_BASE 0x19000000
#define AR71XX_GE0_SIZE 0x10000
#define AR71XX_GE1_BASE 0x1a000000
#define AR71XX_GE1_SIZE 0x10000
#define AR71XX_EHCI_BASE 0x1b000000
#define AR71XX_EHCI_SIZE 0x1000
#define AR71XX_OHCI_BASE 0x1c000000
@ -39,6 +43,8 @@
#define AR71XX_PLL_SIZE 0x100
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
#define AR71XX_RESET_SIZE 0x100
#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
#define AR71XX_MII_SIZE 0x100
#define AR71XX_PCI_MEM_BASE 0x10000000
#define AR71XX_PCI_MEM_SIZE 0x07000000
@ -81,18 +87,39 @@
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE 0x14
#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
#define AR933X_GMAC_SIZE 0x04
#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR933X_WMAC_SIZE 0x20000
#define AR933X_EHCI_BASE 0x1b000000
#define AR933X_EHCI_SIZE 0x1000
#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
#define AR934X_GMAC_SIZE 0x14
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE 0x20000
#define AR934X_EHCI_BASE 0x1b000000
#define AR934X_EHCI_SIZE 0x200
#define AR934X_NFC_BASE 0x1b000200
#define AR934X_NFC_SIZE 0xb8
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
#define AR934X_SRIF_SIZE 0x1000
#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
#define QCA953X_GMAC_SIZE 0x14
#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define QCA953X_WMAC_SIZE 0x20000
#define QCA953X_EHCI_BASE 0x1b000000
#define QCA953X_EHCI_SIZE 0x200
#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
#define QCA953X_SRIF_SIZE 0x1000
#define QCA953X_PCI_CFG_BASE0 0x14000000
#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
#define QCA953X_PCI_MEM_BASE0 0x10000000
#define QCA953X_PCI_MEM_SIZE 0x02000000
#define QCA955X_PCI_MEM_BASE0 0x10000000
#define QCA955X_PCI_MEM_BASE1 0x12000000
#define QCA955X_PCI_MEM_SIZE 0x02000000
@ -106,11 +133,72 @@
#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
#define QCA955X_PCI_CTRL_SIZE 0x100
#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
#define QCA955X_GMAC_SIZE 0x40
#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define QCA955X_WMAC_SIZE 0x20000
#define QCA955X_EHCI0_BASE 0x1b000000
#define QCA955X_EHCI1_BASE 0x1b400000
#define QCA955X_EHCI_SIZE 0x1000
#define QCA955X_NFC_BASE 0x1b800200
#define QCA955X_NFC_SIZE 0xb8
#define QCA956X_PCI_MEM_BASE1 0x12000000
#define QCA956X_PCI_MEM_SIZE 0x02000000
#define QCA956X_PCI_CFG_BASE1 0x16000000
#define QCA956X_PCI_CFG_SIZE 0x1000
#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
#define QCA956X_PCI_CRP_SIZE 0x1000
#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
#define QCA956X_PCI_CTRL_SIZE 0x100
#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define QCA956X_WMAC_SIZE 0x20000
#define QCA956X_EHCI0_BASE 0x1b000000
#define QCA956X_EHCI1_BASE 0x1b400000
#define QCA956X_EHCI_SIZE 0x200
#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
#define QCA956X_GMAC_SGMII_SIZE 0x64
#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
#define QCA956X_PLL_SIZE 0x50
#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
#define QCA956X_GMAC_SIZE 0x64
/*
* Hidden Registers
*/
#define QCA956X_MAC_CFG_BASE 0xb9000000
#define QCA956X_MAC_CFG_SIZE 0x64
#define QCA956X_MAC_CFG1_REG 0x00
#define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
#define QCA956X_MAC_CFG1_RX_RST BIT(19)
#define QCA956X_MAC_CFG1_TX_RST BIT(18)
#define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
#define QCA956X_MAC_CFG1_RX_EN BIT(2)
#define QCA956X_MAC_CFG1_TX_EN BIT(0)
#define QCA956X_MAC_CFG2_REG 0x04
#define QCA956X_MAC_CFG2_IF_1000 BIT(9)
#define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
#define QCA956X_MAC_CFG2_FDX BIT(0)
#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
#define QCA956X_MAC_FIFO_CFG0_REG 0x48
#define QCA956X_MAC_FIFO_CFG1_REG 0x4c
#define QCA956X_MAC_FIFO_CFG2_REG 0x50
#define QCA956X_MAC_FIFO_CFG3_REG 0x54
#define QCA956X_MAC_FIFO_CFG4_REG 0x58
#define QCA956X_MAC_FIFO_CFG5_REG 0x5c
#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
#define QCA956X_DAM_RESET_SIZE 0x4
#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
/*
* DDR_CTRL block
@ -149,6 +237,12 @@
#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
#define AR934X_DDR_REG_FLUSH_WMAC 0xac
#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
#define QCA953X_DDR_REG_FLUSH_USB 0xa4
#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
/*
* PLL block
*/
@ -166,9 +260,15 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
#define AR71XX_ETH0_PLL_SHIFT 17
#define AR71XX_ETH1_PLL_SHIFT 19
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x10
#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
#define AR724X_PLL_FB_SHIFT 0
#define AR724X_PLL_FB_MASK 0x3ff
#define AR724X_PLL_REF_DIV_SHIFT 10
@ -178,6 +278,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
@ -190,6 +292,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
#define AR913X_ETH0_PLL_SHIFT 20
#define AR913X_ETH1_PLL_SHIFT 22
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
@ -211,6 +316,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
@ -243,9 +350,52 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
#define QCA953X_PLL_CPU_CONFIG_REG 0x00
#define QCA953X_PLL_DDR_CONFIG_REG 0x04
#define QCA953X_PLL_CLK_CTRL_REG 0x08
#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
@ -278,6 +428,81 @@
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
#define QCA956X_PLL_CPU_CONFIG_REG 0x00
#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
#define QCA956X_PLL_DDR_CONFIG_REG 0x08
#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
#define QCA956X_PLL_CLK_CTRL_REG 0x10
#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
#define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28
#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26
#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3
#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
/*
* USB_CONFIG block
*/
@ -317,10 +542,19 @@
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
#define QCA953X_RESET_REG_RESET_MODULE 0x1c
#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
#define QCA955X_RESET_REG_RESET_MODULE 0x1c
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
#define QCA956X_RESET_REG_RESET_MODULE 0x1c
#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
#define MISC_INT_ETHSW BIT(12)
#define MISC_INT_TIMER4 BIT(10)
#define MISC_INT_TIMER3 BIT(9)
@ -370,16 +604,123 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
#define AR933X_RESET_GE1_MDIO BIT(23)
#define AR933X_RESET_GE0_MDIO BIT(22)
#define AR933X_RESET_GE1_MAC BIT(13)
#define AR933X_RESET_WMAC BIT(11)
#define AR933X_RESET_GE0_MAC BIT(9)
#define AR933X_RESET_USB_HOST BIT(5)
#define AR933X_RESET_USB_PHY BIT(4)
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
#define AR934X_RESET_HOST BIT(31)
#define AR934X_RESET_SLIC BIT(30)
#define AR934X_RESET_HDMA BIT(29)
#define AR934X_RESET_EXTERNAL BIT(28)
#define AR934X_RESET_RTC BIT(27)
#define AR934X_RESET_PCIE_EP_INT BIT(26)
#define AR934X_RESET_CHKSUM_ACC BIT(25)
#define AR934X_RESET_FULL_CHIP BIT(24)
#define AR934X_RESET_GE1_MDIO BIT(23)
#define AR934X_RESET_GE0_MDIO BIT(22)
#define AR934X_RESET_CPU_NMI BIT(21)
#define AR934X_RESET_CPU_COLD BIT(20)
#define AR934X_RESET_HOST_RESET_INT BIT(19)
#define AR934X_RESET_PCIE_EP BIT(18)
#define AR934X_RESET_UART1 BIT(17)
#define AR934X_RESET_DDR BIT(16)
#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
#define AR934X_RESET_NANDF BIT(14)
#define AR934X_RESET_GE1_MAC BIT(13)
#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
#define AR934X_RESET_HOST_DMA_INT BIT(10)
#define AR934X_RESET_GE0_MAC BIT(9)
#define AR934X_RESET_ETH_SWITCH BIT(8)
#define AR934X_RESET_PCIE_PHY BIT(7)
#define AR934X_RESET_PCIE BIT(6)
#define AR934X_RESET_USB_HOST BIT(5)
#define AR934X_RESET_USB_PHY BIT(4)
#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
#define AR934X_RESET_LUT BIT(2)
#define AR934X_RESET_MBOX BIT(1)
#define AR934X_RESET_I2S BIT(0)
#define QCA953X_RESET_USB_EXT_PWR BIT(29)
#define QCA953X_RESET_EXTERNAL BIT(28)
#define QCA953X_RESET_RTC BIT(27)
#define QCA953X_RESET_FULL_CHIP BIT(24)
#define QCA953X_RESET_GE1_MDIO BIT(23)
#define QCA953X_RESET_GE0_MDIO BIT(22)
#define QCA953X_RESET_CPU_NMI BIT(21)
#define QCA953X_RESET_CPU_COLD BIT(20)
#define QCA953X_RESET_DDR BIT(16)
#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
#define QCA953X_RESET_GE1_MAC BIT(13)
#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
#define QCA953X_RESET_GE0_MAC BIT(9)
#define QCA953X_RESET_ETH_SWITCH BIT(8)
#define QCA953X_RESET_PCIE_PHY BIT(7)
#define QCA953X_RESET_PCIE BIT(6)
#define QCA953X_RESET_USB_HOST BIT(5)
#define QCA953X_RESET_USB_PHY BIT(4)
#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
#define QCA955X_RESET_HOST BIT(31)
#define QCA955X_RESET_SLIC BIT(30)
#define QCA955X_RESET_HDMA BIT(29)
#define QCA955X_RESET_EXTERNAL BIT(28)
#define QCA955X_RESET_RTC BIT(27)
#define QCA955X_RESET_PCIE_EP_INT BIT(26)
#define QCA955X_RESET_CHKSUM_ACC BIT(25)
#define QCA955X_RESET_FULL_CHIP BIT(24)
#define QCA955X_RESET_GE1_MDIO BIT(23)
#define QCA955X_RESET_GE0_MDIO BIT(22)
#define QCA955X_RESET_CPU_NMI BIT(21)
#define QCA955X_RESET_CPU_COLD BIT(20)
#define QCA955X_RESET_HOST_RESET_INT BIT(19)
#define QCA955X_RESET_PCIE_EP BIT(18)
#define QCA955X_RESET_UART1 BIT(17)
#define QCA955X_RESET_DDR BIT(16)
#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
#define QCA955X_RESET_NANDF BIT(14)
#define QCA955X_RESET_GE1_MAC BIT(13)
#define QCA955X_RESET_SGMII_ANALOG BIT(12)
#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
#define QCA955X_RESET_HOST_DMA_INT BIT(10)
#define QCA955X_RESET_GE0_MAC BIT(9)
#define QCA955X_RESET_SGMII BIT(8)
#define QCA955X_RESET_PCIE_PHY BIT(7)
#define QCA955X_RESET_PCIE BIT(6)
#define QCA955X_RESET_USB_HOST BIT(5)
#define QCA955X_RESET_USB_PHY BIT(4)
#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
#define QCA955X_RESET_LUT BIT(2)
#define QCA955X_RESET_MBOX BIT(1)
#define QCA955X_RESET_I2S BIT(0)
#define QCA956X_RESET_EXTERNAL BIT(28)
#define QCA956X_RESET_FULL_CHIP BIT(24)
#define QCA956X_RESET_GE1_MDIO BIT(23)
#define QCA956X_RESET_GE0_MDIO BIT(22)
#define QCA956X_RESET_CPU_NMI BIT(21)
#define QCA956X_RESET_CPU_COLD BIT(20)
#define QCA956X_RESET_DMA BIT(19)
#define QCA956X_RESET_DDR BIT(16)
#define QCA956X_RESET_GE1_MAC BIT(13)
#define QCA956X_RESET_SGMII_ANALOG BIT(12)
#define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
#define QCA956X_RESET_GE0_MAC BIT(9)
#define QCA956X_RESET_SGMII BIT(8)
#define QCA956X_RESET_USB_HOST BIT(5)
#define QCA956X_RESET_USB_PHY BIT(4)
#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
#define QCA956X_RESET_SWITCH_ANALOG BIT(2)
#define QCA956X_RESET_SWITCH BIT(0)
#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
@ -398,8 +739,17 @@
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
@ -418,6 +768,24 @@
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
AR934X_PCIE_WMAC_INT_PCIE_RC3)
#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
QCA953X_PCIE_WMAC_INT_PCIE_RC3)
#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
#define QCA955X_EXT_INT_WMAC_TX BIT(1)
#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
@ -449,6 +817,37 @@
QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
QCA955X_EXT_INT_PCIE_RC2_INT3)
#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
#define QCA956X_EXT_INT_WMAC_TX BIT(1)
#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
#define QCA956X_EXT_INT_USB1 BIT(24)
#define QCA956X_EXT_INT_USB2 BIT(28)
#define QCA956X_EXT_INT_WMAC_ALL \
(QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
#define QCA956X_EXT_INT_PCIE_RC1_ALL \
(QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
QCA956X_EXT_INT_PCIE_RC1_INT3)
#define QCA956X_EXT_INT_PCIE_RC2_ALL \
(QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
QCA956X_EXT_INT_PCIE_RC2_INT3)
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
@ -460,8 +859,12 @@
#define REV_ID_MAJOR_AR9341 0x0120
#define REV_ID_MAJOR_AR9342 0x1120
#define REV_ID_MAJOR_AR9344 0x2120
#define REV_ID_MAJOR_QCA9533 0x0140
#define REV_ID_MAJOR_QCA9533_V2 0x0160
#define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130
#define REV_ID_MAJOR_TP9343 0x0150
#define REV_ID_MAJOR_QCA956X 0x1150
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
@ -482,8 +885,12 @@
#define AR934X_REV_ID_REVISION_MASK 0xf
#define QCA953X_REV_ID_REVISION_MASK 0xf
#define QCA955X_REV_ID_REVISION_MASK 0xf
#define QCA956X_REV_ID_REVISION_MASK 0xf
/*
* SPI block
*/
@ -521,15 +928,63 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
#define AR934X_GPIO_REG_OUT_FUNC1 0x30
#define AR934X_GPIO_REG_OUT_FUNC2 0x34
#define AR934X_GPIO_REG_OUT_FUNC3 0x38
#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
#define QCA953X_GPIO_REG_FUNC 0x6c
#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
#define QCA955X_GPIO_REG_FUNC 0x6c
#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
#define QCA956X_GPIO_REG_FUNC 0x6c
#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
#define AR913X_GPIO_COUNT 22
#define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23
#define QCA953X_GPIO_COUNT 18
#define QCA955X_GPIO_COUNT 24
#define QCA956X_GPIO_COUNT 23
/*
* SRIF block
@ -552,4 +1007,318 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
#define AR724X_GPIO_FUNC_UART_EN BIT(1)
#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
#define AR913X_GPIO_FUNC_UART_EN BIT(8)
#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
#define AR933X_GPIO_FUNC_UART_EN BIT(1)
#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
#define AR934X_GPIO_OUT_GPIO 0
#define AR934X_GPIO_OUT_SPI_CS1 7
#define AR934X_GPIO_OUT_LED_LINK0 41
#define AR934X_GPIO_OUT_LED_LINK1 42
#define AR934X_GPIO_OUT_LED_LINK2 43
#define AR934X_GPIO_OUT_LED_LINK3 44
#define AR934X_GPIO_OUT_LED_LINK4 45
#define AR934X_GPIO_OUT_EXT_LNA0 46
#define AR934X_GPIO_OUT_EXT_LNA1 47
#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
#define QCA955X_GPIO_OUT_GPIO 0
#define QCA955X_MII_EXT_MDI 1
#define QCA955X_SLIC_DATA_OUT 3
#define QCA955X_SLIC_PCM_FS 4
#define QCA955X_SLIC_PCM_CLK 5
#define QCA955X_SPI_CLK 8
#define QCA955X_SPI_CS_0 9
#define QCA955X_SPI_CS_1 10
#define QCA955X_SPI_CS_2 11
#define QCA955X_SPI_MISO 12
#define QCA955X_I2S_CLK 13
#define QCA955X_I2S_WS 14
#define QCA955X_I2S_SD 15
#define QCA955X_I2S_MCK 16
#define QCA955X_SPDIF_OUT 17
#define QCA955X_UART1_TD 18
#define QCA955X_UART1_RTS 19
#define QCA955X_UART1_RD 20
#define QCA955X_UART1_CTS 21
#define QCA955X_UART0_SOUT 22
#define QCA955X_SPDIF2_OUT 23
#define QCA955X_LED_SGMII_SPEED0 24
#define QCA955X_LED_SGMII_SPEED1 25
#define QCA955X_LED_SGMII_DUPLEX 26
#define QCA955X_LED_SGMII_LINK_UP 27
#define QCA955X_SGMII_SPEED0_INVERT 28
#define QCA955X_SGMII_SPEED1_INVERT 29
#define QCA955X_SGMII_DUPLEX_INVERT 30
#define QCA955X_SGMII_LINK_UP_INVERT 31
#define QCA955X_GE1_MII_MDO 32
#define QCA955X_GE1_MII_MDC 33
#define QCA955X_SWCOM2 38
#define QCA955X_SWCOM3 39
#define QCA955X_MAC2_GPIO 40
#define QCA955X_MAC3_GPIO 41
#define QCA955X_ATT_LED 42
#define QCA955X_PWR_LED 43
#define QCA955X_TX_FRAME 44
#define QCA955X_RX_CLEAR_EXTERNAL 45
#define QCA955X_LED_NETWORK_EN 46
#define QCA955X_LED_POWER_EN 47
#define QCA955X_WMAC_GLUE_WOW 68
#define QCA955X_RX_CLEAR_EXTENSION 70
#define QCA955X_CP_NAND_CS1 73
#define QCA955X_USB_SUSPEND 74
#define QCA955X_ETH_TX_ERR 75
#define QCA955X_DDR_DQ_OE 76
#define QCA955X_CLKREQ_N_EP 77
#define QCA955X_CLKREQ_N_RC 78
#define QCA955X_CLK_OBS0 79
#define QCA955X_CLK_OBS1 80
#define QCA955X_CLK_OBS2 81
#define QCA955X_CLK_OBS3 82
#define QCA955X_CLK_OBS4 83
#define QCA955X_CLK_OBS5 84
/*
* MII_CTRL block
*/
#define AR71XX_MII_REG_MII0_CTRL 0x00
#define AR71XX_MII_REG_MII1_CTRL 0x04
#define AR71XX_MII_CTRL_IF_MASK 3
#define AR71XX_MII_CTRL_SPEED_SHIFT 4
#define AR71XX_MII_CTRL_SPEED_MASK 3
#define AR71XX_MII_CTRL_SPEED_10 0
#define AR71XX_MII_CTRL_SPEED_100 1
#define AR71XX_MII_CTRL_SPEED_1000 2
#define AR71XX_MII0_CTRL_IF_GMII 0
#define AR71XX_MII0_CTRL_IF_MII 1
#define AR71XX_MII0_CTRL_IF_RGMII 2
#define AR71XX_MII0_CTRL_IF_RMII 3
#define AR71XX_MII1_CTRL_IF_RGMII 0
#define AR71XX_MII1_CTRL_IF_RMII 1
/*
* AR933X GMAC interface
*/
#define AR933X_GMAC_REG_ETH_CFG 0x00
#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
#define AR933X_ETH_CFG_MII_GE0 BIT(1)
#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
/*
* AR934X GMAC Interface
*/
#define AR934X_GMAC_REG_ETH_CFG 0x00
#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
/*
* QCA953X GMAC Interface
*/
#define QCA953X_GMAC_REG_ETH_CFG 0x00
#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
/*
* QCA955X GMAC Interface
*/
#define QCA955X_GMAC_REG_ETH_CFG 0x00
#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
/*
* QCA956X GMAC Interface
*/
#define QCA956X_GMAC_REG_ETH_CFG 0x00
#define QCA956X_GMAC_REG_SGMII_RESET 0x14
#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
#define QCA956X_ETH_CFG_RGMII_EN BIT(0)
#define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14
#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16
#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
#define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
#define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1
#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
#define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27
#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)
#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
#endif /* __ASM_MACH_AR71XX_REGS_H */

34
arch/mips/include/asm/mach-ath79/ath79.h
View File

@ -32,8 +32,11 @@ enum ath79_soc_type {
ATH79_SOC_AR9341,
ATH79_SOC_AR9342,
ATH79_SOC_AR9344,
ATH79_SOC_QCA9533,
ATH79_SOC_QCA9556,
ATH79_SOC_QCA9558,
ATH79_SOC_TP9343,
ATH79_SOC_QCA956X,
};
extern enum ath79_soc_type ath79_soc;
@ -100,6 +103,16 @@ static inline int soc_is_ar934x(void)
return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
}
static inline int soc_is_qca9533(void)
{
return ath79_soc == ATH79_SOC_QCA9533;
}
static inline int soc_is_qca953x(void)
{
return soc_is_qca9533();
}
static inline int soc_is_qca9556(void)
{
return ath79_soc == ATH79_SOC_QCA9556;
@ -115,6 +128,26 @@ static inline int soc_is_qca955x(void)
return soc_is_qca9556() || soc_is_qca9558();
}
static inline int soc_is_tp9343(void)
{
return ath79_soc == ATH79_SOC_TP9343;
}
static inline int soc_is_qca9561(void)
{
return ath79_soc == ATH79_SOC_QCA956X;
}
static inline int soc_is_qca9563(void)
{
return ath79_soc == ATH79_SOC_QCA956X;
}
static inline int soc_is_qca956x(void)
{
return soc_is_qca9561() || soc_is_qca9563();
}
void ath79_ddr_wb_flush(unsigned int reg);
void ath79_ddr_set_pci_windows(void);
@ -134,6 +167,7 @@ static inline u32 ath79_pll_rr(unsigned reg)
static inline void ath79_reset_wr(unsigned reg, u32 val)
{
__raw_writel(val, ath79_reset_base + reg);
(void) __raw_readl(ath79_reset_base + reg); /* flush */
}
static inline u32 ath79_reset_rr(unsigned reg)

6
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
View File

@ -36,6 +36,7 @@
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_rixi 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
@ -43,6 +44,7 @@
#define cpu_has_mips64r2 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
@ -51,5 +53,9 @@
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 1
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */

54
arch/mips/include/asm/mach-bmips/dma-coherence.h
View File

@ -1,54 +0,0 @@
/*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) 2009 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_MACH_BMIPS_DMA_COHERENCE_H
#define __ASM_MACH_BMIPS_DMA_COHERENCE_H
#include <asm/bmips.h>
#include <asm/cpu-type.h>
#include <asm/cpu.h>
struct device;
extern dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size);
extern dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page);
extern unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr);
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;
}
#define plat_post_dma_flush bmips_post_dma_flush
#endif /* __ASM_MACH_BMIPS_DMA_COHERENCE_H */

79
arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
View File

@ -1,79 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*
*
* Similar to mach-generic/dma-coherence.h except
* plat_device_is_coherent hard coded to return 1.
*
*/
#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
#include <linux/bug.h>
struct device;
extern void octeon_pci_dma_init(void);
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
BUG();
return 0;
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
BUG();
return 0;
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
BUG();
return 0;
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
BUG();
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
BUG();
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 1;
}
static inline void plat_post_dma_flush(struct device *dev)
{
}
static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
if (!dev->dma_mask)
return false;
return addr + size - 1 <= *dev->dma_mask;
}
dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
struct dma_map_ops;
extern const struct dma_map_ops *octeon_pci_dma_map_ops;
extern char *octeon_swiotlb;
#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */

73
arch/mips/include/asm/mach-generic/dma-coherence.h
View File

@ -1,73 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*
*/
#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
struct device;
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
return virt_to_phys(addr);
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
return page_to_phys(page);
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return dma_addr;
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline int plat_device_is_coherent(struct device *dev)
{
#ifdef CONFIG_DMA_PERDEV_COHERENT
return dev->archdata.dma_coherent;
#else
switch (coherentio) {
default:
case IO_COHERENCE_DEFAULT:
return hw_coherentio;
case IO_COHERENCE_ENABLED:
return 1;
case IO_COHERENCE_DISABLED:
return 0;
}
#endif
}
#ifndef plat_post_dma_flush
static inline void plat_post_dma_flush(struct device *dev)
{
}
#endif
#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */

3
arch/mips/include/asm/mach-generic/kmalloc.h
View File

@ -2,8 +2,7 @@
#ifndef __ASM_MACH_GENERIC_KMALLOC_H
#define __ASM_MACH_GENERIC_KMALLOC_H
#ifndef CONFIG_DMA_COHERENT
#ifdef CONFIG_DMA_NONCOHERENT
/*
* Total overkill for most systems but need as a safe default.
* Set this one if any device in the system might do non-coherent DMA.

10
arch/mips/include/asm/mach-generic/spaces.h
View File

@ -17,9 +17,13 @@
/*
* This gives the physical RAM offset.
*/
#ifndef PHYS_OFFSET
#define PHYS_OFFSET _AC(0, UL)
#endif
#ifndef __ASSEMBLY__
# if defined(CONFIG_MIPS_AUTO_PFN_OFFSET)
# define PHYS_OFFSET ((unsigned long)PFN_PHYS(ARCH_PFN_OFFSET))
# elif !defined(PHYS_OFFSET)
# define PHYS_OFFSET _AC(0, UL)
# endif
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_32BIT
#ifdef CONFIG_KVM_GUEST

70
arch/mips/include/asm/mach-ip27/dma-coherence.h
View File

@ -1,70 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*
*/
#ifndef __ASM_MACH_IP27_DMA_COHERENCE_H
#define __ASM_MACH_IP27_DMA_COHERENCE_H
#include <asm/pci/bridge.h>
#define pdev_to_baddr(pdev, addr) \
(BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr))
#define dev_to_baddr(dev, addr) \
pdev_to_baddr(to_pci_dev(dev), (addr))
struct device;
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr));
return pa;
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
return pa;
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return dma_addr & ~(0xffUL << 56);
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline void plat_post_dma_flush(struct device *dev)
{
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 1; /* IP27 non-coherent mode is unsupported */
}
#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */

92
arch/mips/include/asm/mach-ip32/dma-coherence.h
View File

@ -1,92 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*
*/
#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H
#define __ASM_MACH_IP32_DMA_COHERENCE_H
#include <asm/ip32/crime.h>
struct device;
/*
* Few notes.
* 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
* 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
* native-endian)
* 3. All other devices see memory as one big chunk at 0x40000000
* 4. Non-PCI devices will pass NULL as struct device*
*
* Thus we translate differently, depending on device.
*/
#define RAM_OFFSET_MASK 0x3fffffffUL
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK;
if (dev == NULL)
pa += CRIME_HI_MEM_BASE;
return pa;
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
dma_addr_t pa;
pa = page_to_phys(page) & RAM_OFFSET_MASK;
if (dev == NULL)
pa += CRIME_HI_MEM_BASE;
return pa;
}
/* This is almost certainly wrong but it's what dma-ip32.c used to use */
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
unsigned long addr = dma_addr & RAM_OFFSET_MASK;
if (dma_addr >= 256*1024*1024)
addr += CRIME_HI_MEM_BASE;
return addr;
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline void plat_post_dma_flush(struct device *dev)
{
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0; /* IP32 is non-coherent */
}
#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */

60
arch/mips/include/asm/mach-jazz/dma-coherence.h
View File

@ -1,60 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MACH_JAZZ_DMA_COHERENCE_H
#define __ASM_MACH_JAZZ_DMA_COHERENCE_H
#include <asm/jazzdma.h>
struct device;
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
{
return vdma_alloc(virt_to_phys(addr), size);
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
return vdma_alloc(page_to_phys(page), PAGE_SIZE);
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return vdma_log2phys(dma_addr);
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
vdma_free(dma_addr);
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline void plat_post_dma_flush(struct device *dev)
{
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;
}
#endif /* __ASM_MACH_JAZZ_DMA_COHERENCE_H */

93
arch/mips/include/asm/mach-loongson64/dma-coherence.h
View File

@ -1,93 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
* Author: Fuxin Zhang, zhangfx@lemote.com
*
*/
#ifndef __ASM_MACH_LOONGSON64_DMA_COHERENCE_H
#define __ASM_MACH_LOONGSON64_DMA_COHERENCE_H
#ifdef CONFIG_SWIOTLB
#include <linux/swiotlb.h>
#endif
struct device;
static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
if (!dev->dma_mask)
return false;
return addr + size - 1 <= *dev->dma_mask;
}
extern dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
extern phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
#ifdef CONFIG_CPU_LOONGSON3
return __phys_to_dma(dev, virt_to_phys(addr));
#else
return virt_to_phys(addr) | 0x80000000;
#endif
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
#ifdef CONFIG_CPU_LOONGSON3
return __phys_to_dma(dev, page_to_phys(page));
#else
return page_to_phys(page) | 0x80000000;
#endif
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT)
return __dma_to_phys(dev, dma_addr);
#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
#else
return dma_addr & 0x7fffffff;
#endif
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline int plat_device_is_coherent(struct device *dev)
{
#ifdef CONFIG_DMA_NONCOHERENT
return 0;
#else
return 1;
#endif /* CONFIG_DMA_NONCOHERENT */
}
static inline void plat_post_dma_flush(struct device *dev)
{
}
#endif /* __ASM_MACH_LOONGSON64_DMA_COHERENCE_H */

24
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
View File

@ -19,18 +19,18 @@
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
mfc0 t0, $16, 3
mfc0 t0, CP0_CONFIG3
or t0, (0x1 << 7)
mtc0 t0, $16, 3
mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
mfc0 t0, $5, 1
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
mtc0 t0, $5, 1
mtc0 t0, CP0_PAGEGRAIN
#ifdef CONFIG_LOONGSON3_ENHANCEMENT
/* Enable STFill Buffer */
mfc0 t0, $16, 6
mfc0 t0, CP0_CONFIG6
or t0, 0x100
mtc0 t0, $16, 6
mtc0 t0, CP0_CONFIG6
#endif
_ehb
.set pop
@ -45,18 +45,18 @@
.set push
.set mips64
/* Set LPA on LOONGSON3 config3 */
mfc0 t0, $16, 3
mfc0 t0, CP0_CONFIG3
or t0, (0x1 << 7)
mtc0 t0, $16, 3
mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
mfc0 t0, $5, 1
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
mtc0 t0, $5, 1
mtc0 t0, CP0_PAGEGRAIN
#ifdef CONFIG_LOONGSON3_ENHANCEMENT
/* Enable STFill Buffer */
mfc0 t0, $16, 6
mfc0 t0, CP0_CONFIG6
or t0, 0x100
mtc0 t0, $16, 6
mtc0 t0, CP0_CONFIG6
#endif
_ehb
.set pop

1
arch/mips/include/asm/mach-pic32/spaces.h
View File

@ -16,7 +16,6 @@
#ifdef CONFIG_PIC32MZDA
#define PHYS_OFFSET _AC(0x08000000, UL)
#define UNCAC_BASE _AC(0xa8000000, UL)
#endif
#include <asm/mach-generic/spaces.h>

29
arch/mips/include/asm/mipsregs.h
View File

@ -16,6 +16,7 @@
#include <linux/linkage.h>
#include <linux/types.h>
#include <asm/hazards.h>
#include <asm/isa-rev.h>
#include <asm/war.h>
/*
@ -51,6 +52,7 @@
#define CP0_GLOBALNUMBER $3, 1
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_PAGEGRAIN $5, 1
#define CP0_SEGCTL0 $5, 2
#define CP0_SEGCTL1 $5, 3
#define CP0_SEGCTL2 $5, 4
@ -77,6 +79,7 @@
#define CP0_CONFIG $16
#define CP0_CONFIG3 $16, 3
#define CP0_CONFIG5 $16, 5
#define CP0_CONFIG6 $16, 6
#define CP0_LLADDR $17
#define CP0_WATCHLO $18
#define CP0_WATCHHI $19
@ -1481,32 +1484,38 @@ do { \
#define __write_64bit_c0_split(source, sel, val) \
do { \
unsigned long long __tmp; \
unsigned long long __tmp = (val); \
unsigned long __flags; \
\
local_irq_save(__flags); \
if (sel == 0) \
if (MIPS_ISA_REV >= 2) \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\t" MIPS_ISA_LEVEL "\n\t" \
"dins\t%L0, %M0, 32, 32\n\t" \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tpop" \
: "+r" (__tmp)); \
else if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsll\t%L0, %L1, 32\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M1, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source "\n\t" \
".set\tmips0" \
: "=&r,r" (__tmp) \
: "r,0" (val)); \
: "+r" (__tmp)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsll\t%L0, %L1, 32\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M1, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: "=&r,r" (__tmp) \
: "r,0" (val)); \
: "+r" (__tmp)); \
local_irq_restore(__flags); \
} while (0)

2
arch/mips/include/asm/mmu_context.h
View File

@ -126,8 +126,6 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
for_each_possible_cpu(i)
cpu_context(i, mm) = 0;
atomic_set(&mm->context.fp_mode_switching, 0);
mm->context.bd_emupage_allocmap = NULL;
spin_lock_init(&mm->context.bd_emupage_lock);
init_waitqueue_head(&mm->context.bd_emupage_queue);

2
arch/mips/include/asm/netlogic/xlr/fmn.h
View File

@ -301,8 +301,6 @@ static inline int nlm_fmn_send(unsigned int size, unsigned int code,
for (i = 0; i < 8; i++) {
nlm_msgsnd(dest);
status = nlm_read_c2_status0();
if ((status & 0x2) == 1)
pr_info("Send pending fail!\n");
if ((status & 0x4) == 0)
return 0;
}

4
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -55,6 +55,8 @@
#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
void __cvmx_interrupt_asxx_enable(int block);
union cvmx_asxx_gmii_rx_clk_set {
uint64_t u64;
struct cvmx_asxx_gmii_rx_clk_set_s {

10062
arch/mips/include/asm/octeon/cvmx-ciu-defs.h
View File

File diff suppressed because it is too large Load Diff

4
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -2070,6 +2070,8 @@ static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
}
void __cvmx_interrupt_gmxx_enable(int interface);
union cvmx_gmxx_bad_reg {
uint64_t u64;
struct cvmx_gmxx_bad_reg_s {

4
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -334,6 +334,8 @@ static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsig
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}
void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
union cvmx_pcsx_anx_adv_reg {
uint64_t u64;
struct cvmx_pcsx_anx_adv_reg_s {

4
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -268,6 +268,8 @@ static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
}
void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
union cvmx_pcsxx_10gbx_status_reg {
uint64_t u64;
struct cvmx_pcsxx_10gbx_status_reg_s {

4
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -45,6 +45,8 @@
#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
void __cvmx_interrupt_spxx_int_msk_enable(int index);
union cvmx_spxx_bckprs_cnt {
uint64_t u64;
struct cvmx_spxx_bckprs_cnt_s {

4
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
View File

@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
* Copyright (C) 2003-2018 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@ -45,6 +45,8 @@
#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
void __cvmx_interrupt_stxx_int_msk_enable(int index);
union cvmx_stxx_arb_ctl {
uint64_t u64;
struct cvmx_stxx_arb_ctl_s {

9
arch/mips/include/asm/octeon/octeon.h
View File

@ -279,13 +279,12 @@ union octeon_cvmemctl {
} s;
};
extern void octeon_write_lcd(const char *s);
extern void octeon_check_cpu_bist(void);
extern int octeon_get_boot_uart(void);
struct uart_port;
extern unsigned int octeon_serial_in(struct uart_port *, int);
extern void octeon_serial_out(struct uart_port *, int, int);
int octeon_prune_device_tree(void);
extern const char __appended_dtb;
extern const char __dtb_octeon_3xxx_begin;
extern const char __dtb_octeon_68xx_begin;
/**
* Write a 32bit value to the Octeon NPI register space

3
arch/mips/include/asm/octeon/pci-octeon.h
View File

@ -63,4 +63,7 @@ enum octeon_dma_bar_type {
*/
extern enum octeon_dma_bar_type octeon_dma_bar_type;
void octeon_pci_dma_init(void);
extern char *octeon_swiotlb;
#endif

11
arch/mips/include/asm/page.h
View File

@ -80,7 +80,12 @@ extern void build_copy_page(void);
* used in our early mem init code for all memory models.
* So always define it.
*/
#define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET)
#ifdef CONFIG_MIPS_AUTO_PFN_OFFSET
extern unsigned long ARCH_PFN_OFFSET;
# define ARCH_PFN_OFFSET ARCH_PFN_OFFSET
#else
# define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET)
#endif
extern void clear_page(void * page);
extern void copy_page(void * to, void * from);
@ -252,8 +257,8 @@ extern int __virt_addr_valid(const volatile void *kaddr);
((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr))
#define CAC_ADDR(addr) ((unsigned long)__va((addr) - UNCAC_BASE))
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>

15
arch/mips/include/asm/processor.h
View File

@ -141,7 +141,7 @@ struct mips_fpu_struct {
#define NUM_DSP_REGS 6
typedef __u32 dspreg_t;
typedef unsigned long dspreg_t;
struct mips_dsp_state {
dspreg_t dspr[NUM_DSP_REGS];
@ -386,7 +386,20 @@ unsigned long get_wchan(struct task_struct *p);
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
#ifdef CONFIG_CPU_LOONGSON3
/*
* Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
* tight read loop is executed, because reads take priority over writes & the
* hardware (incorrectly) doesn't ensure that writes will eventually occur.
*
* Since spin loops of any kind should have a cpu_relax() in them, force an SFB
* flush from cpu_relax() such that any pending writes will become visible as
* expected.
*/
#define cpu_relax() smp_mb()
#else
#define cpu_relax() barrier()
#endif
/*
* Return_address is a replacement for __builtin_return_address(count)

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