PCI/ATS: Cache PRI PRG Response PASID Required bit
The PRG Response PASID Required bit in the PRI Capability is read-only. Read it once when we enumerate the device and cache the value so we don't need to read it again. Based-on-patch-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -161,7 +161,16 @@ EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
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#ifdef CONFIG_PCI_PRI
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void pci_pri_init(struct pci_dev *pdev)
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{
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u16 status;
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pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pdev->pri_cap)
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return;
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pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status);
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if (status & PCI_PRI_STATUS_PASID)
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pdev->pasid_required = 1;
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}
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/**
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@ -301,22 +310,10 @@ EXPORT_SYMBOL_GPL(pci_reset_pri);
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*/
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int pci_prg_resp_pasid_required(struct pci_dev *pdev)
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{
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u16 status;
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int pri;
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if (pdev->is_virtfn)
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pdev = pci_physfn(pdev);
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pri = pdev->pri_cap;
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if (!pri)
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return 0;
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pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
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if (status & PCI_PRI_STATUS_PASID)
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return 1;
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return 0;
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return pdev->pasid_required;
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}
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EXPORT_SYMBOL_GPL(pci_prg_resp_pasid_required);
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#endif /* CONFIG_PCI_PRI */
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@ -456,6 +456,7 @@ struct pci_dev {
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#ifdef CONFIG_PCI_PRI
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u16 pri_cap; /* PRI Capability offset */
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u32 pri_reqs_alloc; /* Number of PRI requests allocated */
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unsigned int pasid_required:1; /* PRG Response PASID Required */
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#endif
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#ifdef CONFIG_PCI_PASID
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u16 pasid_cap; /* PASID Capability offset */
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