irqchip: gic: Replace hex numbers with defines.
This is to cleanup some hex numbers used in the code and replace them with defines to make the code cleaner. Signed-off-by: Feng Kan <fkan@apm.com> Reviewed-by: Anup Patel <apatel@apm.com> Link: https://lkml.kernel.org/r/1406757419-18729-2-git-send-email-fkan@apm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>hifive-unleashed-5.1
Feng Kan
Jason Cooper
parent
7d1311b93e
commit
e5f81539f6
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@ -74,20 +74,22 @@ void __init gic_dist_config(void __iomem *base, int gic_irqs,
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < gic_irqs; i += 16)
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writel_relaxed(0, base + GIC_DIST_CONFIG + i / 4);
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writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
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base + GIC_DIST_CONFIG + i / 4);
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/*
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i);
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writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as they are enabled by redistributor registers.
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*/
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for (i = 32; i < gic_irqs; i += 32)
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writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i / 8);
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writel_relaxed(GICD_INT_EN_CLR_X32,
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base + GIC_DIST_ENABLE_CLEAR + i / 8);
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if (sync_access)
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sync_access();
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@ -101,14 +103,15 @@ void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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writel_relaxed(0xffff0000, base + GIC_DIST_ENABLE_CLEAR);
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writel_relaxed(0x0000ffff, base + GIC_DIST_ENABLE_SET);
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writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
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writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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writel_relaxed(GICD_INT_DEF_PRI_X4,
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base + GIC_DIST_PRI + i * 4 / 4);
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if (sync_access)
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sync_access();
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@ -298,8 +298,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
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raw_spin_unlock(&irq_controller_lock);
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gic_irq = (status & 0x3ff);
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if (gic_irq == 1023)
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gic_irq = (status & GICC_IAR_INT_ID_MASK);
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if (gic_irq == GICC_INT_SPURIOUS)
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goto out;
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cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
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@ -360,7 +360,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
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unsigned int gic_irqs = gic->gic_irqs;
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void __iomem *base = gic_data_dist_base(gic);
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writel_relaxed(0, base + GIC_DIST_CTRL);
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writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
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/*
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* Set all global interrupts to this CPU only.
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@ -373,7 +373,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
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gic_dist_config(base, gic_irqs, NULL);
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writel_relaxed(1, base + GIC_DIST_CTRL);
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writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
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}
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static void gic_cpu_init(struct gic_chip_data *gic)
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@ -400,8 +400,8 @@ static void gic_cpu_init(struct gic_chip_data *gic)
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gic_cpu_config(dist_base, NULL);
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writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
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writel_relaxed(1, base + GIC_CPU_CTRL);
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writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
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writel_relaxed(GICC_ENABLE, base + GIC_CPU_CTRL);
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}
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void gic_cpu_if_down(void)
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@ -467,14 +467,14 @@ static void gic_dist_restore(unsigned int gic_nr)
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if (!dist_base)
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return;
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writel_relaxed(0, dist_base + GIC_DIST_CTRL);
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writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
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writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
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dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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writel_relaxed(0xa0a0a0a0,
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writel_relaxed(GICD_INT_DEF_PRI_X4,
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dist_base + GIC_DIST_PRI + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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@ -485,7 +485,7 @@ static void gic_dist_restore(unsigned int gic_nr)
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writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
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dist_base + GIC_DIST_ENABLE_SET + i * 4);
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writel_relaxed(1, dist_base + GIC_DIST_CTRL);
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writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
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}
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static void gic_cpu_save(unsigned int gic_nr)
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@ -539,10 +539,11 @@ static void gic_cpu_restore(unsigned int gic_nr)
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writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
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writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
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writel_relaxed(GICD_INT_DEF_PRI_X4,
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dist_base + GIC_DIST_PRI + i * 4);
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writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
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writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
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writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
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writel_relaxed(GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
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}
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static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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@ -21,7 +21,10 @@
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#define GIC_CPU_ACTIVEPRIO 0xd0
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#define GIC_CPU_IDENT 0xfc
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#define GICC_ENABLE 0x1
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#define GICC_INT_PRI_THRESHOLD 0xf0
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#define GICC_IAR_INT_ID_MASK 0x3ff
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#define GICC_INT_SPURIOUS 1023
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#define GIC_DIST_CTRL 0x000
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#define GIC_DIST_CTR 0x004
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@ -39,6 +42,18 @@
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#define GIC_DIST_SGI_PENDING_CLEAR 0xf10
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#define GIC_DIST_SGI_PENDING_SET 0xf20
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#define GICD_ENABLE 0x1
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#define GICD_DISABLE 0x0
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#define GICD_INT_ACTLOW_LVLTRIG 0x0
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#define GICD_INT_EN_CLR_X32 0xffffffff
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#define GICD_INT_EN_SET_SGI 0x0000ffff
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#define GICD_INT_EN_CLR_PPI 0xffff0000
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#define GICD_INT_DEF_PRI 0xa0
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#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
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(GICD_INT_DEF_PRI << 16) |\
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(GICD_INT_DEF_PRI << 8) |\
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GICD_INT_DEF_PRI)
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#define GICH_HCR 0x0
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#define GICH_VTR 0x4
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#define GICH_VMCR 0x8
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