x64, x2apic/intr-remap: Intel vt-d, IOMMU code reorganization
code reorganization of the generic Intel vt-d parsing related routines and linux iommu routines specific to Intel vt-d. drivers/pci/dmar.c now contains the generic vt-d parsing related routines drivers/pci/intel_iommu.c contains the iommu routines specific to vt-d Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Suresh Siddha
Ingo Molnar
parent
1ba89386db
commit
e61d98d8da
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@ -0,0 +1,155 @@
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#ifndef _DMA_REMAPPING_H
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#define _DMA_REMAPPING_H
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/*
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* We need a fixed PAGE_SIZE of 4K irrespective of
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* arch PAGE_SIZE for IOMMU page tables.
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*/
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#define PAGE_SHIFT_4K (12)
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#define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K)
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#define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K)
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#define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K)
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#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT_4K)
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#define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK)
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#define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK)
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/*
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* 0: Present
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* 1-11: Reserved
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* 12-63: Context Ptr (12 - (haw-1))
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* 64-127: Reserved
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*/
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struct root_entry {
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u64 val;
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u64 rsvd1;
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};
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#define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
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static inline bool root_present(struct root_entry *root)
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{
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return (root->val & 1);
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}
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static inline void set_root_present(struct root_entry *root)
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{
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root->val |= 1;
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}
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static inline void set_root_value(struct root_entry *root, unsigned long value)
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{
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root->val |= value & PAGE_MASK_4K;
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}
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struct context_entry;
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static inline struct context_entry *
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get_context_addr_from_root(struct root_entry *root)
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{
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return (struct context_entry *)
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(root_present(root)?phys_to_virt(
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root->val & PAGE_MASK_4K):
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NULL);
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}
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/*
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* low 64 bits:
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* 0: present
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* 1: fault processing disable
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* 2-3: translation type
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* 12-63: address space root
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* high 64 bits:
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* 0-2: address width
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* 3-6: aval
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* 8-23: domain id
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*/
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struct context_entry {
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u64 lo;
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u64 hi;
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};
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#define context_present(c) ((c).lo & 1)
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#define context_fault_disable(c) (((c).lo >> 1) & 1)
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#define context_translation_type(c) (((c).lo >> 2) & 3)
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#define context_address_root(c) ((c).lo & PAGE_MASK_4K)
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#define context_address_width(c) ((c).hi & 7)
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#define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
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#define context_set_present(c) do {(c).lo |= 1;} while (0)
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#define context_set_fault_enable(c) \
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do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
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#define context_set_translation_type(c, val) \
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do { \
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(c).lo &= (((u64)-1) << 4) | 3; \
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(c).lo |= ((val) & 3) << 2; \
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} while (0)
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#define CONTEXT_TT_MULTI_LEVEL 0
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#define context_set_address_root(c, val) \
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do {(c).lo |= (val) & PAGE_MASK_4K;} while (0)
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#define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
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#define context_set_domain_id(c, val) \
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do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
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#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
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/*
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* 0: readable
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* 1: writable
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* 2-6: reserved
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* 7: super page
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* 8-11: available
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* 12-63: Host physcial address
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*/
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struct dma_pte {
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u64 val;
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};
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#define dma_clear_pte(p) do {(p).val = 0;} while (0)
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#define DMA_PTE_READ (1)
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#define DMA_PTE_WRITE (2)
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#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
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#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
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#define dma_set_pte_prot(p, prot) \
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do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
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#define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
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#define dma_set_pte_addr(p, addr) do {\
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(p).val |= ((addr) & PAGE_MASK_4K); } while (0)
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#define dma_pte_present(p) (((p).val & 3) != 0)
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struct intel_iommu;
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struct dmar_domain {
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int id; /* domain id */
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struct intel_iommu *iommu; /* back pointer to owning iommu */
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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struct dma_pte *pgd; /* virtual address */
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spinlock_t mapping_lock; /* page table lock */
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int gaw; /* max guest address width */
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/* adjusted guest address width, 0 is level 2 30-bit */
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int agaw;
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#define DOMAIN_FLAG_MULTIPLE_DEVICES 1
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int flags;
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};
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/* PCI domain-device relationship */
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struct device_domain_info {
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struct list_head link; /* link to domain siblings */
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struct list_head global; /* link to global list */
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u8 bus; /* PCI bus numer */
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u8 devfn; /* PCI devfn number */
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struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
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struct dmar_domain *domain; /* pointer to domain */
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};
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extern int init_dmars(void);
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extern void free_dmar_iommu(struct intel_iommu *iommu);
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#ifndef CONFIG_DMAR_GFX_WA
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static inline void iommu_prepare_gfx_mapping(void)
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{
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return;
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}
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#endif /* !CONFIG_DMAR_GFX_WA */
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#endif
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@ -19,9 +19,11 @@
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* Author: Shaohua Li <shaohua.li@intel.com>
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* Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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*
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* This file implements early detection/parsing of DMA Remapping Devices
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* This file implements early detection/parsing of Remapping Devices
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* reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
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* tables.
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*
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* These routines are used by both DMA-remapping and Interrupt-remapping
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*/
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#include <linux/pci.h>
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@ -300,6 +302,37 @@ parse_dmar_table(void)
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return ret;
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}
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int dmar_pci_device_match(struct pci_dev *devices[], int cnt,
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struct pci_dev *dev)
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{
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int index;
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while (dev) {
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for (index = 0; index < cnt; index++)
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if (dev == devices[index])
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return 1;
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/* Check our parent */
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dev = dev->bus->self;
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}
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return 0;
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}
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struct dmar_drhd_unit *
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dmar_find_matched_drhd_unit(struct pci_dev *dev)
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{
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struct dmar_drhd_unit *drhd = NULL;
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list_for_each_entry(drhd, &dmar_drhd_units, list) {
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if (drhd->include_all || dmar_pci_device_match(drhd->devices,
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drhd->devices_cnt, dev))
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return drhd;
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}
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return NULL;
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}
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int __init dmar_table_init(void)
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{
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@ -343,3 +376,58 @@ int __init early_dmar_detect(void)
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return (ACPI_SUCCESS(status) ? 1 : 0);
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}
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struct intel_iommu *alloc_iommu(struct intel_iommu *iommu,
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struct dmar_drhd_unit *drhd)
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{
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int map_size;
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u32 ver;
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iommu->reg = ioremap(drhd->reg_base_addr, PAGE_SIZE_4K);
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if (!iommu->reg) {
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printk(KERN_ERR "IOMMU: can't map the region\n");
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goto error;
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}
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iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
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iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
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/* the registers might be more than one page */
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map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
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cap_max_fault_reg_offset(iommu->cap));
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map_size = PAGE_ALIGN_4K(map_size);
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if (map_size > PAGE_SIZE_4K) {
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iounmap(iommu->reg);
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iommu->reg = ioremap(drhd->reg_base_addr, map_size);
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if (!iommu->reg) {
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printk(KERN_ERR "IOMMU: can't map the region\n");
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goto error;
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}
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}
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ver = readl(iommu->reg + DMAR_VER_REG);
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pr_debug("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
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drhd->reg_base_addr, DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
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iommu->cap, iommu->ecap);
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spin_lock_init(&iommu->register_lock);
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drhd->iommu = iommu;
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return iommu;
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error:
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kfree(iommu);
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return NULL;
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}
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void free_iommu(struct intel_iommu *iommu)
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{
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if (!iommu)
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return;
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#ifdef CONFIG_DMAR
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free_dmar_iommu(iommu);
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#endif
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if (iommu->reg)
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iounmap(iommu->reg);
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kfree(iommu);
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}
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@ -990,6 +990,8 @@ static int iommu_init_domains(struct intel_iommu *iommu)
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return -ENOMEM;
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}
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spin_lock_init(&iommu->lock);
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/*
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* if Caching mode is set, then invalid translations are tagged
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* with domainid 0. Hence we need to pre-allocate it.
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@ -998,62 +1000,15 @@ static int iommu_init_domains(struct intel_iommu *iommu)
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set_bit(0, iommu->domain_ids);
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return 0;
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}
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static struct intel_iommu *alloc_iommu(struct intel_iommu *iommu,
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struct dmar_drhd_unit *drhd)
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{
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int ret;
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int map_size;
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u32 ver;
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iommu->reg = ioremap(drhd->reg_base_addr, PAGE_SIZE_4K);
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if (!iommu->reg) {
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printk(KERN_ERR "IOMMU: can't map the region\n");
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goto error;
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}
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iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
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iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
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/* the registers might be more than one page */
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map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
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cap_max_fault_reg_offset(iommu->cap));
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map_size = PAGE_ALIGN_4K(map_size);
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if (map_size > PAGE_SIZE_4K) {
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iounmap(iommu->reg);
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iommu->reg = ioremap(drhd->reg_base_addr, map_size);
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if (!iommu->reg) {
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printk(KERN_ERR "IOMMU: can't map the region\n");
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goto error;
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}
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}
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ver = readl(iommu->reg + DMAR_VER_REG);
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pr_debug("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
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drhd->reg_base_addr, DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
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iommu->cap, iommu->ecap);
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ret = iommu_init_domains(iommu);
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if (ret)
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goto error_unmap;
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spin_lock_init(&iommu->lock);
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spin_lock_init(&iommu->register_lock);
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drhd->iommu = iommu;
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return iommu;
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error_unmap:
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iounmap(iommu->reg);
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error:
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kfree(iommu);
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return NULL;
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}
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static void domain_exit(struct dmar_domain *domain);
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static void free_iommu(struct intel_iommu *iommu)
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void free_dmar_iommu(struct intel_iommu *iommu)
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{
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struct dmar_domain *domain;
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int i;
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if (!iommu)
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return;
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i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
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for (; i < cap_ndoms(iommu->cap); ) {
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domain = iommu->domains[i];
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@ -1078,10 +1033,6 @@ static void free_iommu(struct intel_iommu *iommu)
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/* free context mapping */
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free_context_table(iommu);
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if (iommu->reg)
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iounmap(iommu->reg);
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kfree(iommu);
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}
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static struct dmar_domain * iommu_alloc_domain(struct intel_iommu *iommu)
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@ -1426,37 +1377,6 @@ find_domain(struct pci_dev *pdev)
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return NULL;
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}
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static int dmar_pci_device_match(struct pci_dev *devices[], int cnt,
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struct pci_dev *dev)
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{
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int index;
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while (dev) {
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for (index = 0; index < cnt; index++)
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if (dev == devices[index])
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return 1;
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/* Check our parent */
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dev = dev->bus->self;
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}
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return 0;
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}
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static struct dmar_drhd_unit *
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dmar_find_matched_drhd_unit(struct pci_dev *dev)
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{
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struct dmar_drhd_unit *drhd = NULL;
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list_for_each_entry(drhd, &dmar_drhd_units, list) {
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if (drhd->include_all || dmar_pci_device_match(drhd->devices,
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drhd->devices_cnt, dev))
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return drhd;
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}
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return NULL;
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}
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/* domain is initialized */
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static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
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{
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@ -1764,6 +1684,10 @@ int __init init_dmars(void)
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goto error;
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}
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ret = iommu_init_domains(iommu);
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if (ret)
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goto error;
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/*
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* TBD:
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* we could share the same root & context tables
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@ -27,19 +27,7 @@
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#include <linux/sysdev.h>
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#include "iova.h"
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#include <linux/io.h>
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/*
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* We need a fixed PAGE_SIZE of 4K irrespective of
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* arch PAGE_SIZE for IOMMU page tables.
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*/
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#define PAGE_SHIFT_4K (12)
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#define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K)
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#define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K)
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#define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K)
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#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT_4K)
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#define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK)
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#define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK)
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#include "dma_remapping.h"
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/*
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* Intel IOMMU register specification per version 1.0 public spec.
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@ -187,158 +175,31 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
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#define dma_frcd_source_id(c) (c & 0xffff)
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#define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
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/*
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* 0: Present
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* 1-11: Reserved
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* 12-63: Context Ptr (12 - (haw-1))
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* 64-127: Reserved
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*/
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struct root_entry {
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u64 val;
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u64 rsvd1;
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};
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#define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
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static inline bool root_present(struct root_entry *root)
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{
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return (root->val & 1);
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}
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static inline void set_root_present(struct root_entry *root)
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{
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root->val |= 1;
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}
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static inline void set_root_value(struct root_entry *root, unsigned long value)
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{
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root->val |= value & PAGE_MASK_4K;
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}
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|
||||
struct context_entry;
|
||||
static inline struct context_entry *
|
||||
get_context_addr_from_root(struct root_entry *root)
|
||||
{
|
||||
return (struct context_entry *)
|
||||
(root_present(root)?phys_to_virt(
|
||||
root->val & PAGE_MASK_4K):
|
||||
NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* low 64 bits:
|
||||
* 0: present
|
||||
* 1: fault processing disable
|
||||
* 2-3: translation type
|
||||
* 12-63: address space root
|
||||
* high 64 bits:
|
||||
* 0-2: address width
|
||||
* 3-6: aval
|
||||
* 8-23: domain id
|
||||
*/
|
||||
struct context_entry {
|
||||
u64 lo;
|
||||
u64 hi;
|
||||
};
|
||||
#define context_present(c) ((c).lo & 1)
|
||||
#define context_fault_disable(c) (((c).lo >> 1) & 1)
|
||||
#define context_translation_type(c) (((c).lo >> 2) & 3)
|
||||
#define context_address_root(c) ((c).lo & PAGE_MASK_4K)
|
||||
#define context_address_width(c) ((c).hi & 7)
|
||||
#define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
|
||||
|
||||
#define context_set_present(c) do {(c).lo |= 1;} while (0)
|
||||
#define context_set_fault_enable(c) \
|
||||
do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
|
||||
#define context_set_translation_type(c, val) \
|
||||
do { \
|
||||
(c).lo &= (((u64)-1) << 4) | 3; \
|
||||
(c).lo |= ((val) & 3) << 2; \
|
||||
} while (0)
|
||||
#define CONTEXT_TT_MULTI_LEVEL 0
|
||||
#define context_set_address_root(c, val) \
|
||||
do {(c).lo |= (val) & PAGE_MASK_4K;} while (0)
|
||||
#define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
|
||||
#define context_set_domain_id(c, val) \
|
||||
do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
|
||||
#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
|
||||
|
||||
/*
|
||||
* 0: readable
|
||||
* 1: writable
|
||||
* 2-6: reserved
|
||||
* 7: super page
|
||||
* 8-11: available
|
||||
* 12-63: Host physcial address
|
||||
*/
|
||||
struct dma_pte {
|
||||
u64 val;
|
||||
};
|
||||
#define dma_clear_pte(p) do {(p).val = 0;} while (0)
|
||||
|
||||
#define DMA_PTE_READ (1)
|
||||
#define DMA_PTE_WRITE (2)
|
||||
|
||||
#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
|
||||
#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
|
||||
#define dma_set_pte_prot(p, prot) \
|
||||
do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
|
||||
#define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
|
||||
#define dma_set_pte_addr(p, addr) do {\
|
||||
(p).val |= ((addr) & PAGE_MASK_4K); } while (0)
|
||||
#define dma_pte_present(p) (((p).val & 3) != 0)
|
||||
|
||||
struct intel_iommu;
|
||||
|
||||
struct dmar_domain {
|
||||
int id; /* domain id */
|
||||
struct intel_iommu *iommu; /* back pointer to owning iommu */
|
||||
|
||||
struct list_head devices; /* all devices' list */
|
||||
struct iova_domain iovad; /* iova's that belong to this domain */
|
||||
|
||||
struct dma_pte *pgd; /* virtual address */
|
||||
spinlock_t mapping_lock; /* page table lock */
|
||||
int gaw; /* max guest address width */
|
||||
|
||||
/* adjusted guest address width, 0 is level 2 30-bit */
|
||||
int agaw;
|
||||
|
||||
#define DOMAIN_FLAG_MULTIPLE_DEVICES 1
|
||||
int flags;
|
||||
};
|
||||
|
||||
/* PCI domain-device relationship */
|
||||
struct device_domain_info {
|
||||
struct list_head link; /* link to domain siblings */
|
||||
struct list_head global; /* link to global list */
|
||||
u8 bus; /* PCI bus numer */
|
||||
u8 devfn; /* PCI devfn number */
|
||||
struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
|
||||
struct dmar_domain *domain; /* pointer to domain */
|
||||
};
|
||||
|
||||
extern int init_dmars(void);
|
||||
|
||||
struct intel_iommu {
|
||||
void __iomem *reg; /* Pointer to hardware regs, virtual addr */
|
||||
u64 cap;
|
||||
u64 ecap;
|
||||
unsigned long *domain_ids; /* bitmap of domains */
|
||||
struct dmar_domain **domains; /* ptr to domains */
|
||||
int seg;
|
||||
u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
|
||||
spinlock_t lock; /* protect context, domain ids */
|
||||
spinlock_t register_lock; /* protect register handling */
|
||||
|
||||
#ifdef CONFIG_DMAR
|
||||
unsigned long *domain_ids; /* bitmap of domains */
|
||||
struct dmar_domain **domains; /* ptr to domains */
|
||||
spinlock_t lock; /* protect context, domain ids */
|
||||
struct root_entry *root_entry; /* virtual address */
|
||||
|
||||
unsigned int irq;
|
||||
unsigned char name[7]; /* Device Name */
|
||||
struct msi_msg saved_msg;
|
||||
struct sys_device sysdev;
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifndef CONFIG_DMAR_GFX_WA
|
||||
static inline void iommu_prepare_gfx_mapping(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* !CONFIG_DMAR_GFX_WA */
|
||||
extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
|
||||
|
||||
extern struct intel_iommu *alloc_iommu(struct intel_iommu *iommu,
|
||||
struct dmar_drhd_unit *drhd);
|
||||
extern void free_iommu(struct intel_iommu *iommu);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue