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ARM: dts: dra7: fix DSS PLL clock mux registers 

The clock nodes for DSS VIDEO1/2 and HDMI have wrong register addresses.
This patch fixes the addresses so that they point to
CM_CLKSEL_VIDEO1_PLL_SYS, CM_CLKSEL_VIDEO2_PLL_SYS and
CM_CLKSEL_HDMI_PLL_SYS.

Reported-by: Somnath Mukherjee <somnath@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
hifive-unleashed-5.1
Tomi Valkeinen 2014-10-13 11:50:41 +03:00 committed by Tony Lindgren
parent be6688350a
commit e671538d51
1 changed files with 3 additions and 3 deletions
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6
arch/arm/boot/dts/dra7xx-clocks.dtsi
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@ -1042,7 +1042,7 @@
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x01a4>;
reg = <0x0164>;
};
mlb_clk: mlb_clk {
@ -1084,14 +1084,14 @@
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x01d0>;
reg = <0x0168>;
};
video2_dpll_clk_mux: video2_dpll_clk_mux {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x01d4>;
reg = <0x016c>;
};
wkupaon_iclk_mux: wkupaon_iclk_mux {