[ARM] pxa/balloon3: Add NAND driver
The NAND support is implemented through the gen_nand driver. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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@ -27,6 +27,8 @@
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#include <linux/mtd/partitions.h>
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#include <linux/types.h>
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#include <linux/i2c/pcf857x.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/physmap.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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@ -529,6 +531,154 @@ static void __init balloon3_i2c_init(void)
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static inline void balloon3_i2c_init(void) {}
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#endif
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/******************************************************************************
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* NAND
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******************************************************************************/
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#if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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static uint16_t balloon3_ctl =
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BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
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BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
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BALLOON3_NAND_CONTROL_FLWP;
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static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_CLE)
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balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE;
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else
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balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE;
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if (ctrl & NAND_ALE)
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balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE;
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else
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balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE;
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__raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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if (chip < 0 || chip > 3)
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return;
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balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 |
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BALLOON3_NAND_CONTROL_FLCE1 |
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BALLOON3_NAND_CONTROL_FLCE2 |
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BALLOON3_NAND_CONTROL_FLCE3;
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/* Deassert correct nCE line */
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balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip);
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__raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
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}
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static int balloon3_nand_probe(struct platform_device *pdev)
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{
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void __iomem *temp_map;
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uint16_t ver;
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int ret;
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__raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG);
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ver = __raw_readw(BALLOON3_FPGA_VER);
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if (ver > 0x0201)
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pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. "
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"NAND support might be broken in this version!", ver);
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/* Power up the NAND chips */
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ret = gpio_request(BALLOON3_GPIO_RUN_NAND, "NAND");
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if (ret)
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goto err1;
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ret = gpio_direction_output(BALLOON3_GPIO_RUN_NAND, 1);
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if (ret)
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goto err2;
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gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1);
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/* Deassert all nCE lines and write protect line */
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__raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
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return 0;
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err2:
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gpio_free(BALLOON3_GPIO_RUN_NAND);
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err1:
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return ret;
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}
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static void balloon3_nand_remove(struct platform_device *pdev)
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{
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/* Power down the NAND chips */
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gpio_set_value(BALLOON3_GPIO_RUN_NAND, 0);
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gpio_free(BALLOON3_GPIO_RUN_NAND);
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}
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static struct mtd_partition balloon3_partition_info[] = {
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[0] = {
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.name = "Boot",
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.offset = 0,
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.size = SZ_4M,
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},
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[1] = {
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.name = "RootFS",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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},
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};
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static const char *balloon3_part_probes[] = { "cmdlinepart", NULL };
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struct platform_nand_data balloon3_nand_pdata = {
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.chip = {
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.nr_chips = 4,
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.chip_offset = 0,
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.nr_partitions = ARRAY_SIZE(balloon3_partition_info),
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.partitions = balloon3_partition_info,
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.chip_delay = 50,
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.part_probe_types = balloon3_part_probes,
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},
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.ctrl = {
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.hwcontrol = 0,
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.dev_ready = 0,
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.select_chip = balloon3_nand_select_chip,
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.cmd_ctrl = balloon3_nand_cmd_ctl,
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.probe = balloon3_nand_probe,
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.remove = balloon3_nand_remove,
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},
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};
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static struct resource balloon3_nand_resource[] = {
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[0] = {
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.start = BALLOON3_NAND_BASE,
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.end = BALLOON3_NAND_BASE + 0x4,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device balloon3_nand = {
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.name = "gen_nand",
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.num_resources = ARRAY_SIZE(balloon3_nand_resource),
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.resource = balloon3_nand_resource,
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.id = -1,
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.dev = {
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.platform_data = &balloon3_nand_pdata,
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}
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};
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static void __init balloon3_nand_init(void)
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{
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platform_device_register(&balloon3_nand);
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}
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#else
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static inline void balloon3_nand_init(void) {}
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#endif
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/******************************************************************************
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* Machine init
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******************************************************************************/
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@ -547,6 +697,7 @@ static void __init balloon3_init(void)
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balloon3_lcd_init();
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balloon3_leds_init();
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balloon3_mmc_init();
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balloon3_nand_init();
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balloon3_nor_init();
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balloon3_ts_init();
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balloon3_udc_init();
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@ -31,12 +31,15 @@ enum balloon3_features {
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#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
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/* FPGA / CPLD version register */
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#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c)
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/* FPGA / CPLD registers for NAND flash */
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#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000)
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#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
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#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
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#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
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#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
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#define BALLOON3_NANDIO_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
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/* fpga/cpld interrupt control register */
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#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C)
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#define BALLOON3_NANDIO_CTL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
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#define BALLOON3_NANDIO_CTL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
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#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c)
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#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000)
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@ -56,6 +59,22 @@ enum balloon3_features {
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#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
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#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
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/* NAND Control register */
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#define BALLOON3_NAND_CONTROL_FLWP (1 << 7)
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#define BALLOON3_NAND_CONTROL_FLSE (1 << 6)
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#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5)
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#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4)
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#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3)
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#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2)
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#define BALLOON3_NAND_CONTROL_FLALE (1 << 1)
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#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0)
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/* NAND Status register */
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#define BALLOON3_NAND_STAT_RNB (1 << 0)
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/* NAND Control2 register */
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#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0)
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/* GPIOs for irqs */
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#define BALLOON3_GPIO_AUX_NIRQ (94)
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#define BALLOON3_GPIO_CODEC_IRQ (95)
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@ -69,6 +88,9 @@ enum balloon3_features {
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#define BALLOON3_GPIO_S0_CD (105)
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/* NAND */
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#define BALLOON3_GPIO_RUN_NAND (102)
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/* PCF8574A Leds */
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#define BALLOON3_PCF_GPIO_BASE 160
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#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0)
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