intel_idle: Use ACPI _CST on server systems
In many cases, especially on server systems, it is desirable to avoid enabling C-states that have been disabled in the platform firmware (BIOS) setup, except for C1E. As a rule, the C-states disabled this way are not listed by ACPI _CST, so if that is used by intel_idle along with the specific table of C-states that it has for the given processor, the C-states disabled through the platform firmware will not be enabled by default by intel_idle. Accordingly, set the use_acpi flag (introduced previously) in all server processor profiles defined in intel_idle (so as to make it use ACPI _CST to decide which C-states to enable by default) and set the CPUIDLE_FLAG_ALWAYS_ENABLE flag (also introduced previously) for C1E in all C-states tables in intel_idle that contain C1 too (so that C1E is enabled regardless of whether or not it is listed by ACPI _CST). Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
parent
4ec32d9e8e
commit
e6d4f08a67
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@ -131,7 +131,7 @@ static struct cpuidle_state nehalem_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -168,7 +168,7 @@ static struct cpuidle_state snb_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -303,7 +303,7 @@ static struct cpuidle_state ivb_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -348,7 +348,7 @@ static struct cpuidle_state ivt_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 80,
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.target_residency = 80,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -385,7 +385,7 @@ static struct cpuidle_state ivt_cstates_4s[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 250,
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.target_residency = 250,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -422,7 +422,7 @@ static struct cpuidle_state ivt_cstates_8s[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 500,
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.target_residency = 500,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -459,7 +459,7 @@ static struct cpuidle_state hsw_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -527,7 +527,7 @@ static struct cpuidle_state bdw_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -596,7 +596,7 @@ static struct cpuidle_state skl_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -665,7 +665,7 @@ static struct cpuidle_state skx_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -815,7 +815,7 @@ static struct cpuidle_state bxt_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -876,7 +876,7 @@ static struct cpuidle_state dnv_cstates[] = {
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{
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{
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.name = "C1E",
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 10,
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.exit_latency = 10,
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.target_residency = 20,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter = &intel_idle,
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@ -998,6 +998,13 @@ static const struct idle_cpu idle_cpu_nehalem = {
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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};
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};
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static const struct idle_cpu idle_cpu_nhx = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_atom = {
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static const struct idle_cpu idle_cpu_atom = {
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.state_table = atom_cstates,
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.state_table = atom_cstates,
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};
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};
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@ -1016,6 +1023,12 @@ static const struct idle_cpu idle_cpu_snb = {
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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};
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};
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static const struct idle_cpu idle_cpu_snx = {
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.state_table = snb_cstates,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_byt = {
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static const struct idle_cpu idle_cpu_byt = {
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.state_table = byt_cstates,
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.state_table = byt_cstates,
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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@ -1036,6 +1049,7 @@ static const struct idle_cpu idle_cpu_ivb = {
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static const struct idle_cpu idle_cpu_ivt = {
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static const struct idle_cpu idle_cpu_ivt = {
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.state_table = ivt_cstates,
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.state_table = ivt_cstates,
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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};
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static const struct idle_cpu idle_cpu_hsw = {
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static const struct idle_cpu idle_cpu_hsw = {
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@ -1043,11 +1057,23 @@ static const struct idle_cpu idle_cpu_hsw = {
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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};
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};
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static const struct idle_cpu idle_cpu_hsx = {
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.state_table = hsw_cstates,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_bdw = {
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static const struct idle_cpu idle_cpu_bdw = {
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.state_table = bdw_cstates,
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.state_table = bdw_cstates,
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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};
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};
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static const struct idle_cpu idle_cpu_bdx = {
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.state_table = bdw_cstates,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_skl = {
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static const struct idle_cpu idle_cpu_skl = {
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.state_table = skl_cstates,
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.state_table = skl_cstates,
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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@ -1056,15 +1082,18 @@ static const struct idle_cpu idle_cpu_skl = {
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static const struct idle_cpu idle_cpu_skx = {
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static const struct idle_cpu idle_cpu_skx = {
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.state_table = skx_cstates,
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.state_table = skx_cstates,
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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};
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static const struct idle_cpu idle_cpu_avn = {
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static const struct idle_cpu idle_cpu_avn = {
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.state_table = avn_cstates,
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.state_table = avn_cstates,
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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};
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static const struct idle_cpu idle_cpu_knl = {
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static const struct idle_cpu idle_cpu_knl = {
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.state_table = knl_cstates,
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.state_table = knl_cstates,
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.use_acpi = true,
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};
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};
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static const struct idle_cpu idle_cpu_bxt = {
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static const struct idle_cpu idle_cpu_bxt = {
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@ -1075,20 +1104,21 @@ static const struct idle_cpu idle_cpu_bxt = {
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static const struct idle_cpu idle_cpu_dnv = {
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static const struct idle_cpu idle_cpu_dnv = {
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.state_table = dnv_cstates,
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.state_table = dnv_cstates,
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.disable_promotion_to_c1e = true,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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};
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static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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INTEL_CPU_FAM6(NEHALEM_EP, idle_cpu_nehalem),
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INTEL_CPU_FAM6(NEHALEM_EP, idle_cpu_nhx),
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INTEL_CPU_FAM6(NEHALEM, idle_cpu_nehalem),
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INTEL_CPU_FAM6(NEHALEM, idle_cpu_nehalem),
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INTEL_CPU_FAM6(NEHALEM_G, idle_cpu_nehalem),
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INTEL_CPU_FAM6(NEHALEM_G, idle_cpu_nehalem),
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INTEL_CPU_FAM6(WESTMERE, idle_cpu_nehalem),
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INTEL_CPU_FAM6(WESTMERE, idle_cpu_nehalem),
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INTEL_CPU_FAM6(WESTMERE_EP, idle_cpu_nehalem),
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INTEL_CPU_FAM6(WESTMERE_EP, idle_cpu_nhx),
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INTEL_CPU_FAM6(NEHALEM_EX, idle_cpu_nehalem),
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INTEL_CPU_FAM6(NEHALEM_EX, idle_cpu_nhx),
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INTEL_CPU_FAM6(ATOM_BONNELL, idle_cpu_atom),
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INTEL_CPU_FAM6(ATOM_BONNELL, idle_cpu_atom),
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INTEL_CPU_FAM6(ATOM_BONNELL_MID, idle_cpu_lincroft),
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INTEL_CPU_FAM6(ATOM_BONNELL_MID, idle_cpu_lincroft),
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INTEL_CPU_FAM6(WESTMERE_EX, idle_cpu_nehalem),
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INTEL_CPU_FAM6(WESTMERE_EX, idle_cpu_nhx),
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INTEL_CPU_FAM6(SANDYBRIDGE, idle_cpu_snb),
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INTEL_CPU_FAM6(SANDYBRIDGE, idle_cpu_snb),
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INTEL_CPU_FAM6(SANDYBRIDGE_X, idle_cpu_snb),
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INTEL_CPU_FAM6(SANDYBRIDGE_X, idle_cpu_snx),
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INTEL_CPU_FAM6(ATOM_SALTWELL, idle_cpu_atom),
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INTEL_CPU_FAM6(ATOM_SALTWELL, idle_cpu_atom),
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INTEL_CPU_FAM6(ATOM_SILVERMONT, idle_cpu_byt),
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INTEL_CPU_FAM6(ATOM_SILVERMONT, idle_cpu_byt),
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INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, idle_cpu_tangier),
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INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, idle_cpu_tangier),
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@ -1096,14 +1126,14 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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INTEL_CPU_FAM6(IVYBRIDGE, idle_cpu_ivb),
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INTEL_CPU_FAM6(IVYBRIDGE, idle_cpu_ivb),
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INTEL_CPU_FAM6(IVYBRIDGE_X, idle_cpu_ivt),
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INTEL_CPU_FAM6(IVYBRIDGE_X, idle_cpu_ivt),
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INTEL_CPU_FAM6(HASWELL, idle_cpu_hsw),
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INTEL_CPU_FAM6(HASWELL, idle_cpu_hsw),
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INTEL_CPU_FAM6(HASWELL_X, idle_cpu_hsw),
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INTEL_CPU_FAM6(HASWELL_X, idle_cpu_hsx),
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INTEL_CPU_FAM6(HASWELL_L, idle_cpu_hsw),
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INTEL_CPU_FAM6(HASWELL_L, idle_cpu_hsw),
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INTEL_CPU_FAM6(HASWELL_G, idle_cpu_hsw),
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INTEL_CPU_FAM6(HASWELL_G, idle_cpu_hsw),
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INTEL_CPU_FAM6(ATOM_SILVERMONT_D, idle_cpu_avn),
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INTEL_CPU_FAM6(ATOM_SILVERMONT_D, idle_cpu_avn),
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INTEL_CPU_FAM6(BROADWELL, idle_cpu_bdw),
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INTEL_CPU_FAM6(BROADWELL, idle_cpu_bdw),
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INTEL_CPU_FAM6(BROADWELL_G, idle_cpu_bdw),
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INTEL_CPU_FAM6(BROADWELL_G, idle_cpu_bdw),
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INTEL_CPU_FAM6(BROADWELL_X, idle_cpu_bdw),
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INTEL_CPU_FAM6(BROADWELL_X, idle_cpu_bdx),
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INTEL_CPU_FAM6(BROADWELL_D, idle_cpu_bdw),
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INTEL_CPU_FAM6(BROADWELL_D, idle_cpu_bdx),
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INTEL_CPU_FAM6(SKYLAKE_L, idle_cpu_skl),
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INTEL_CPU_FAM6(SKYLAKE_L, idle_cpu_skl),
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INTEL_CPU_FAM6(SKYLAKE, idle_cpu_skl),
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INTEL_CPU_FAM6(SKYLAKE, idle_cpu_skl),
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INTEL_CPU_FAM6(KABYLAKE_L, idle_cpu_skl),
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INTEL_CPU_FAM6(KABYLAKE_L, idle_cpu_skl),
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