drm/i915: split display functions by chip type
This patch splits out several of the display functions into a separate display function table to avoid tons of chipset specific if..else if..else if blocks all over. There are more opportunities for this (some noted in the structure defintition); so more cleanup patches will follow. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jesse Barnes
Eric Anholt
parent
8542a0bbbb
commit
e70236a8d3
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@ -153,6 +153,23 @@ struct drm_i915_error_state {
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struct timeval time;
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};
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struct drm_i915_display_funcs {
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void (*dpms)(struct drm_crtc *crtc, int mode);
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bool (*fbc_enabled)(struct drm_crtc *crtc);
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void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
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void (*disable_fbc)(struct drm_device *dev);
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int (*get_display_clock_speed)(struct drm_device *dev);
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int (*get_fifo_size)(struct drm_device *dev, int plane);
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void (*update_wm)(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int pixel_size);
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/* clock updates for mode set */
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/* cursor updates */
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/* render clock increase/decrease */
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/* display clock increase/decrease */
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/* pll clock increase/decrease */
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/* clock gating init */
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};
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typedef struct drm_i915_private {
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struct drm_device *dev;
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@ -252,6 +269,9 @@ typedef struct drm_i915_private {
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struct work_struct error_work;
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struct workqueue_struct *wq;
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/* Display functions */
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struct drm_i915_display_funcs display;
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/* Register state */
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bool suspended;
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u8 saveLBB;
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@ -1064,6 +1064,11 @@ static void intel_update_fbc(struct drm_crtc *crtc,
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if (!i915_powersave)
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return;
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if (!dev_priv->display.fbc_enabled ||
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!dev_priv->display.enable_fbc ||
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!dev_priv->display.disable_fbc)
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return;
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if (!crtc->fb)
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return;
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@ -1101,19 +1106,19 @@ static void intel_update_fbc(struct drm_crtc *crtc,
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goto out_disable;
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}
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if (i8xx_fbc_enabled(crtc)) {
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if (dev_priv->display.fbc_enabled(crtc)) {
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/* We can re-enable it in this case, but need to update pitch */
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if (fb->pitch > dev_priv->cfb_pitch)
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i8xx_disable_fbc(dev);
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dev_priv->display.disable_fbc(dev);
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if (obj_priv->fence_reg != dev_priv->cfb_fence)
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i8xx_disable_fbc(dev);
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dev_priv->display.disable_fbc(dev);
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if (plane != dev_priv->cfb_plane)
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i8xx_disable_fbc(dev);
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dev_priv->display.disable_fbc(dev);
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}
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if (!i8xx_fbc_enabled(crtc)) {
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if (!dev_priv->display.fbc_enabled(crtc)) {
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/* Now try to turn it back on if possible */
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i8xx_enable_fbc(crtc, 500);
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dev_priv->display.enable_fbc(crtc, 500);
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}
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return;
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@ -1121,8 +1126,8 @@ static void intel_update_fbc(struct drm_crtc *crtc,
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out_disable:
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DRM_DEBUG("unsupported config, disabling FBC\n");
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/* Multiple disables should be harmless */
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if (i8xx_fbc_enabled(crtc))
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i8xx_disable_fbc(dev);
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if (dev_priv->display.fbc_enabled(crtc))
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dev_priv->display.disable_fbc(dev);
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}
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static int
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@ -1769,8 +1774,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
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intel_crtc_load_lut(crtc);
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if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
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intel_update_fbc(crtc, &crtc->mode);
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intel_update_fbc(crtc, &crtc->mode);
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/* Give the overlay scaler a chance to enable if it's on this pipe */
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//intel_crtc_dpms_video(crtc, true); TODO
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@ -1781,8 +1785,9 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
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/* Give the overlay scaler a chance to disable if it's on this pipe */
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//intel_crtc_dpms_video(crtc, FALSE); TODO
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if (dev_priv->cfb_plane == plane)
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i8xx_disable_fbc(dev);
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if (dev_priv->cfb_plane == plane &&
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dev_priv->display.disable_fbc)
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dev_priv->display.disable_fbc(dev);
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/* Disable the VGA plane that we never use */
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i915_disable_vga(dev);
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@ -1832,15 +1837,13 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
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static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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bool enabled;
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if (IS_IGDNG(dev))
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igdng_crtc_dpms(crtc, mode);
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else
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i9xx_crtc_dpms(crtc, mode);
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dev_priv->display.dpms(crtc, mode);
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intel_crtc->dpms_mode = mode;
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@ -1907,56 +1910,68 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
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return true;
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}
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/** Returns the core display clock speed for i830 - i945 */
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static int intel_get_core_clock_speed(struct drm_device *dev)
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static int i945_get_display_clock_speed(struct drm_device *dev)
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{
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return 400000;
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}
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/* Core clock values taken from the published datasheets.
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* The 830 may go up to 166 Mhz, which we should check.
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*/
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if (IS_I945G(dev))
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return 400000;
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else if (IS_I915G(dev))
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return 333000;
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else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
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return 200000;
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else if (IS_I915GM(dev)) {
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u16 gcfgc = 0;
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static int i915_get_display_clock_speed(struct drm_device *dev)
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{
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return 333000;
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}
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pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
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static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
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{
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return 200000;
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}
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if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
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return 133000;
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else {
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switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
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case GC_DISPLAY_CLOCK_333_MHZ:
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return 333000;
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default:
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case GC_DISPLAY_CLOCK_190_200_MHZ:
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return 190000;
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}
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}
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} else if (IS_I865G(dev))
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return 266000;
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else if (IS_I855(dev)) {
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u16 hpllcc = 0;
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/* Assume that the hardware is in the high speed state. This
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* should be the default.
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*/
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switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
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case GC_CLOCK_133_200:
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case GC_CLOCK_100_200:
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return 200000;
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case GC_CLOCK_166_250:
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return 250000;
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case GC_CLOCK_100_133:
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return 133000;
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}
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} else /* 852, 830 */
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static int i915gm_get_display_clock_speed(struct drm_device *dev)
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{
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u16 gcfgc = 0;
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pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
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if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
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return 133000;
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else {
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switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
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case GC_DISPLAY_CLOCK_333_MHZ:
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return 333000;
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default:
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case GC_DISPLAY_CLOCK_190_200_MHZ:
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return 190000;
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}
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}
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}
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return 0; /* Silence gcc warning */
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static int i865_get_display_clock_speed(struct drm_device *dev)
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{
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return 266000;
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}
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static int i855_get_display_clock_speed(struct drm_device *dev)
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{
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u16 hpllcc = 0;
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/* Assume that the hardware is in the high speed state. This
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* should be the default.
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*/
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switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
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case GC_CLOCK_133_200:
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case GC_CLOCK_100_200:
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return 200000;
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case GC_CLOCK_166_250:
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return 250000;
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case GC_CLOCK_100_133:
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return 133000;
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}
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/* Shouldn't happen */
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return 0;
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}
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static int i830_get_display_clock_speed(struct drm_device *dev)
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{
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return 133000;
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}
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/**
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@ -2288,32 +2303,17 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
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*/
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const static int latency_ns = 5000;
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static int intel_get_fifo_size(struct drm_device *dev, int plane)
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static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dsparb = I915_READ(DSPARB);
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int size;
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if (IS_I9XX(dev)) {
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if (plane == 0)
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size = dsparb & 0x7f;
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else
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size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
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(dsparb & 0x7f);
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} else if (IS_I85X(dev)) {
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if (plane == 0)
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size = dsparb & 0x1ff;
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else
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size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
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(dsparb & 0x1ff);
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size >>= 1; /* Convert to cachelines */
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} else if (IS_845G(dev)) {
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if (plane == 0)
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size = dsparb & 0x7f;
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size >>= 2; /* Convert to cachelines */
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} else {
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size = dsparb & 0x7f;
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size >>= 1; /* Convert to cachelines */
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}
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else
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size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
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(dsparb & 0x7f);
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DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
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size);
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@ -2321,7 +2321,57 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane)
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return size;
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}
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static void g4x_update_wm(struct drm_device *dev)
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static int i85x_get_fifo_size(struct drm_device *dev, int plane)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dsparb = I915_READ(DSPARB);
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int size;
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if (plane == 0)
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size = dsparb & 0x1ff;
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else
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size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
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(dsparb & 0x1ff);
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size >>= 1; /* Convert to cachelines */
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DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
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size);
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return size;
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}
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static int i845_get_fifo_size(struct drm_device *dev, int plane)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dsparb = I915_READ(DSPARB);
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int size;
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size = dsparb & 0x7f;
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size >>= 2; /* Convert to cachelines */
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DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
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size);
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return size;
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}
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static int i830_get_fifo_size(struct drm_device *dev, int plane)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t dsparb = I915_READ(DSPARB);
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int size;
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size = dsparb & 0x7f;
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size >>= 1; /* Convert to cachelines */
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DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
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size);
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return size;
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}
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static void g4x_update_wm(struct drm_device *dev, int unused, int unused2,
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int unused3, int unused4)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 fw_blc_self = I915_READ(FW_BLC_SELF);
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@ -2333,7 +2383,8 @@ static void g4x_update_wm(struct drm_device *dev)
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I915_WRITE(FW_BLC_SELF, fw_blc_self);
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}
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static void i965_update_wm(struct drm_device *dev)
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static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
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int unused3, int unused4)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -2369,8 +2420,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
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cacheline_size = planea_params.cacheline_size;
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/* Update per-plane FIFO sizes */
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planea_params.fifo_size = intel_get_fifo_size(dev, 0);
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planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
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planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
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planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
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planea_wm = intel_calculate_wm(planea_clock, &planea_params,
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pixel_size, latency_ns);
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@ -2417,14 +2468,14 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
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I915_WRITE(FW_BLC2, fwater_hi);
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}
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static void i830_update_wm(struct drm_device *dev, int planea_clock,
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int pixel_size)
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static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
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int unused2, int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
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int planea_wm;
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i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
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i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
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planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
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pixel_size, latency_ns);
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@ -2468,6 +2519,7 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock,
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*/
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static void intel_update_watermarks(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc;
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struct intel_crtc *intel_crtc;
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int sr_hdisplay = 0;
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@ -2506,15 +2558,8 @@ static void intel_update_watermarks(struct drm_device *dev)
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else if (IS_IGD(dev))
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igd_disable_cxsr(dev);
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if (IS_G4X(dev))
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g4x_update_wm(dev);
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else if (IS_I965G(dev))
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i965_update_wm(dev);
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else if (IS_I9XX(dev) || IS_MOBILE(dev))
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i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
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pixel_size);
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else
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i830_update_wm(dev, planea_clock, pixel_size);
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dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
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sr_hdisplay, pixel_size);
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}
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static int intel_crtc_mode_set(struct drm_crtc *crtc,
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@ -2785,7 +2830,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
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* pipe == 0 check?
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*/
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if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
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if (mode->clock >
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dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
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pipeconf |= PIPEACONF_DOUBLE_WIDE;
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else
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pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
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@ -2942,8 +2988,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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/* Flush the plane changes */
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ret = intel_pipe_set_base(crtc, x, y, old_fb);
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if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
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intel_update_fbc(crtc, &crtc->mode);
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intel_update_fbc(crtc, &crtc->mode);
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intel_update_watermarks(dev);
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drm_vblank_post_modeset(dev, pipe);
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@ -4049,6 +4095,69 @@ void intel_init_clock_gating(struct drm_device *dev)
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}
|
||||
}
|
||||
|
||||
/* Set up chip specific display functions */
|
||||
static void intel_init_display(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
/* We always want a DPMS function */
|
||||
if (IS_IGDNG(dev))
|
||||
dev_priv->display.dpms = igdng_crtc_dpms;
|
||||
else
|
||||
dev_priv->display.dpms = i9xx_crtc_dpms;
|
||||
|
||||
/* Only mobile has FBC, leave pointers NULL for other chips */
|
||||
if (IS_MOBILE(dev)) {
|
||||
/* 855GM needs testing */
|
||||
if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
|
||||
dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
|
||||
dev_priv->display.enable_fbc = i8xx_enable_fbc;
|
||||
dev_priv->display.disable_fbc = i8xx_disable_fbc;
|
||||
}
|
||||
}
|
||||
|
||||
/* Returns the core display clock speed */
|
||||
if (IS_I945G(dev))
|
||||
dev_priv->display.get_display_clock_speed =
|
||||
i945_get_display_clock_speed;
|
||||
else if (IS_I915G(dev))
|
||||
dev_priv->display.get_display_clock_speed =
|
||||
i915_get_display_clock_speed;
|
||||
else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
|
||||
dev_priv->display.get_display_clock_speed =
|
||||
i9xx_misc_get_display_clock_speed;
|
||||
else if (IS_I915GM(dev))
|
||||
dev_priv->display.get_display_clock_speed =
|
||||
i915gm_get_display_clock_speed;
|
||||
else if (IS_I865G(dev))
|
||||
dev_priv->display.get_display_clock_speed =
|
||||
i865_get_display_clock_speed;
|
||||
else if (IS_I855(dev))
|
||||
dev_priv->display.get_display_clock_speed =
|
||||
i855_get_display_clock_speed;
|
||||
else /* 852, 830 */
|
||||
dev_priv->display.get_display_clock_speed =
|
||||
i830_get_display_clock_speed;
|
||||
|
||||
/* For FIFO watermark updates */
|
||||
if (IS_G4X(dev))
|
||||
dev_priv->display.update_wm = g4x_update_wm;
|
||||
else if (IS_I965G(dev))
|
||||
dev_priv->display.update_wm = i965_update_wm;
|
||||
else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
|
||||
dev_priv->display.update_wm = i9xx_update_wm;
|
||||
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
|
||||
} else {
|
||||
if (IS_I85X(dev))
|
||||
dev_priv->display.get_fifo_size = i85x_get_fifo_size;
|
||||
else if (IS_845G(dev))
|
||||
dev_priv->display.get_fifo_size = i845_get_fifo_size;
|
||||
else
|
||||
dev_priv->display.get_fifo_size = i830_get_fifo_size;
|
||||
dev_priv->display.update_wm = i830_update_wm;
|
||||
}
|
||||
}
|
||||
|
||||
void intel_modeset_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
|
@ -4062,6 +4171,8 @@ void intel_modeset_init(struct drm_device *dev)
|
|||
|
||||
dev->mode_config.funcs = (void *)&intel_mode_funcs;
|
||||
|
||||
intel_init_display(dev);
|
||||
|
||||
if (IS_I965G(dev)) {
|
||||
dev->mode_config.max_width = 8192;
|
||||
dev->mode_config.max_height = 8192;
|
||||
|
|
@ -4127,7 +4238,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
|
|||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
i8xx_disable_fbc(dev);
|
||||
if (dev_priv->display.disable_fbc)
|
||||
dev_priv->display.disable_fbc(dev);
|
||||
|
||||
drm_mode_config_cleanup(dev);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue