Merge branch 'x86-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 clockevent update from Thomas Gleixner: "A single commit, which converts HPET clockevents driver to the new callbacks" * 'x86-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/hpet: Migrate to new set_state interfacehifive-unleashed-5.1
Linus Torvalds
commit
e713c80a4e
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@ -226,22 +226,7 @@ static void hpet_reserve_platform_timers(unsigned int id) { }
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*/
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static unsigned long hpet_freq;
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static void hpet_legacy_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt);
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static int hpet_legacy_next_event(unsigned long delta,
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struct clock_event_device *evt);
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/*
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* The hpet clock event device
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*/
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static struct clock_event_device hpet_clockevent = {
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.name = "hpet",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = hpet_legacy_set_mode,
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.set_next_event = hpet_legacy_next_event,
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.irq = 0,
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.rating = 50,
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};
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static struct clock_event_device hpet_clockevent;
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static void hpet_stop_counter(void)
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{
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@ -306,64 +291,74 @@ static void hpet_legacy_clockevent_register(void)
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printk(KERN_DEBUG "hpet clockevent registered\n");
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}
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static void hpet_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt, int timer)
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static int hpet_set_periodic(struct clock_event_device *evt, int timer)
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{
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unsigned int cfg, cmp, now;
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uint64_t delta;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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hpet_stop_counter();
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delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
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delta >>= evt->shift;
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now = hpet_readl(HPET_COUNTER);
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cmp = now + (unsigned int) delta;
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
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HPET_TN_SETVAL | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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hpet_writel(cmp, HPET_Tn_CMP(timer));
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udelay(1);
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/*
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* HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
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* cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
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* bit is automatically cleared after the first write.
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* (See AMD-8111 HyperTransport I/O Hub Data Sheet,
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* Publication # 24674)
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*/
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hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
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hpet_start_counter();
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hpet_print_config();
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break;
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hpet_stop_counter();
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delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
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delta >>= evt->shift;
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now = hpet_readl(HPET_COUNTER);
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cmp = now + (unsigned int)delta;
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
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HPET_TN_32BIT;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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hpet_writel(cmp, HPET_Tn_CMP(timer));
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udelay(1);
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/*
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* HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
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* cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
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* bit is automatically cleared after the first write.
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* (See AMD-8111 HyperTransport I/O Hub Data Sheet,
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* Publication # 24674)
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*/
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hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
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hpet_start_counter();
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hpet_print_config();
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case CLOCK_EVT_MODE_ONESHOT:
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg &= ~HPET_TN_PERIODIC;
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cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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break;
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return 0;
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}
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg &= ~HPET_TN_ENABLE;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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break;
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static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
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{
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unsigned int cfg;
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case CLOCK_EVT_MODE_RESUME:
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if (timer == 0) {
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hpet_enable_legacy_int();
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} else {
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
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disable_irq(hdev->irq);
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irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
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enable_irq(hdev->irq);
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}
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hpet_print_config();
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break;
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg &= ~HPET_TN_PERIODIC;
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cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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return 0;
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}
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static int hpet_shutdown(struct clock_event_device *evt, int timer)
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{
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unsigned int cfg;
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg &= ~HPET_TN_ENABLE;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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return 0;
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}
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static int hpet_resume(struct clock_event_device *evt, int timer)
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{
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if (!timer) {
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hpet_enable_legacy_int();
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} else {
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
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disable_irq(hdev->irq);
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irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
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enable_irq(hdev->irq);
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}
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hpet_print_config();
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return 0;
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}
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static int hpet_next_event(unsigned long delta,
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@ -403,10 +398,24 @@ static int hpet_next_event(unsigned long delta,
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return res < HPET_MIN_CYCLES ? -ETIME : 0;
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}
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static void hpet_legacy_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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static int hpet_legacy_shutdown(struct clock_event_device *evt)
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{
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hpet_set_mode(mode, evt, 0);
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return hpet_shutdown(evt, 0);
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}
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static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
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{
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return hpet_set_oneshot(evt, 0);
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}
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static int hpet_legacy_set_periodic(struct clock_event_device *evt)
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{
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return hpet_set_periodic(evt, 0);
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}
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static int hpet_legacy_resume(struct clock_event_device *evt)
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{
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return hpet_resume(evt, 0);
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}
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static int hpet_legacy_next_event(unsigned long delta,
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@ -415,6 +424,22 @@ static int hpet_legacy_next_event(unsigned long delta,
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return hpet_next_event(delta, evt, 0);
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}
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/*
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* The hpet clock event device
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*/
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static struct clock_event_device hpet_clockevent = {
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.name = "hpet",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_state_periodic = hpet_legacy_set_periodic,
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.set_state_oneshot = hpet_legacy_set_oneshot,
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.set_state_shutdown = hpet_legacy_shutdown,
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.tick_resume = hpet_legacy_resume,
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.set_next_event = hpet_legacy_next_event,
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.irq = 0,
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.rating = 50,
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};
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/*
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* HPET MSI Support
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*/
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@ -459,11 +484,32 @@ void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
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msg->address_hi = 0;
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}
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static void hpet_msi_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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static int hpet_msi_shutdown(struct clock_event_device *evt)
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{
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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hpet_set_mode(mode, evt, hdev->num);
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return hpet_shutdown(evt, hdev->num);
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}
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static int hpet_msi_set_oneshot(struct clock_event_device *evt)
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{
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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return hpet_set_oneshot(evt, hdev->num);
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}
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static int hpet_msi_set_periodic(struct clock_event_device *evt)
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{
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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return hpet_set_periodic(evt, hdev->num);
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}
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static int hpet_msi_resume(struct clock_event_device *evt)
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{
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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return hpet_resume(evt, hdev->num);
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}
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static int hpet_msi_next_event(unsigned long delta,
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@ -523,10 +569,14 @@ static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
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evt->rating = 110;
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evt->features = CLOCK_EVT_FEAT_ONESHOT;
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if (hdev->flags & HPET_DEV_PERI_CAP)
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if (hdev->flags & HPET_DEV_PERI_CAP) {
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evt->features |= CLOCK_EVT_FEAT_PERIODIC;
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evt->set_state_periodic = hpet_msi_set_periodic;
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}
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evt->set_mode = hpet_msi_set_mode;
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evt->set_state_shutdown = hpet_msi_shutdown;
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evt->set_state_oneshot = hpet_msi_set_oneshot;
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evt->tick_resume = hpet_msi_resume;
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evt->set_next_event = hpet_msi_next_event;
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evt->cpumask = cpumask_of(hdev->cpu);
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