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clk: meson: meson8b: make the CCF use the glitch-free mali mux 

[ Upstream commit 8daeaea99c ]

The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.

This fixes a potential hang when changing the GPU frequency at runtime.

Fixes: 74e1f2521f ("clk: meson: meson8b: add the GPU clock tree")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
5.4-rM2-2.2.x-imx-squashed
Martin Blumenstingl 2019-12-26 20:12:23 +01:00 committed by Greg Kroah-Hartman
parent 271b18405e
commit e715aa99c5
1 changed files with 7 additions and 4 deletions
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11
drivers/clk/meson/meson8b.c
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@ -1764,8 +1764,11 @@ static struct clk_regmap meson8b_hdmi_sys = {
/*
* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
* muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
* has mali_0 and no glitch-free mux.
* muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
* actually manage this glitch-free mux because it does top-to-bottom
* updates the each clock tree and switches to the "inactive" one when
* CLK_SET_RATE_GATE is set.
* Meson8 only has mali_0 and no glitch-free mux.
*/
static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
&meson8b_xtal.hw,
@ -1830,7 +1833,7 @@ static struct clk_regmap meson8b_mali_0 = {
&meson8b_mali_0_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
},
};
@ -1885,7 +1888,7 @@ static struct clk_regmap meson8b_mali_1 = {
&meson8b_mali_1_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
},
};