drm/radeon/kms: add bo blit support for Ontario fusion APUs
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -147,7 +147,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
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if (rdev->family == CHIP_CEDAR)
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if ((rdev->family == CHIP_CEDAR) ||
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(rdev->family == CHIP_PALM))
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, 48, gpu_addr);
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else
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@ -331,9 +332,31 @@ set_default_state(struct radeon_device *rdev)
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num_hs_stack_entries = 85;
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num_ls_stack_entries = 85;
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break;
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case CHIP_PALM:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 96;
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num_vs_threads = 16;
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num_gs_threads = 16;
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num_es_threads = 16;
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num_hs_threads = 16;
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num_ls_threads = 16;
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num_ps_stack_entries = 42;
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num_vs_stack_entries = 42;
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num_gs_stack_entries = 42;
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num_es_stack_entries = 42;
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num_hs_stack_entries = 42;
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num_ls_stack_entries = 42;
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break;
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}
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if (rdev->family == CHIP_CEDAR)
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if ((rdev->family == CHIP_CEDAR) ||
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(rdev->family == CHIP_PALM))
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sq_config = 0;
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else
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sq_config = VC_ENABLE;
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@ -769,9 +769,9 @@ static struct radeon_asic sumo_asic = {
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.get_vblank_counter = &evergreen_get_vblank_counter,
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.fence_ring_emit = &r600_fence_ring_emit,
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.cs_parse = &evergreen_cs_parse,
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.copy_blit = NULL,
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.copy_dma = NULL,
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.copy = NULL,
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.copy_blit = &evergreen_copy_blit,
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.copy_dma = &evergreen_copy_blit,
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.copy = &evergreen_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = NULL,
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