rt2x00: Don't treat ATIM queue as second beacon queue.
Current code for the atim queue is strange, as it is considered in the rt2x00_dev structure as a second beacon queue. Normalize this by letting the atim queue have its own struct data_queue pointer in the rt2x00_dev structure. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
3736fe5808
commit
e74df4a756
|
@ -779,7 +779,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
||||||
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
|
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
|
||||||
rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
|
rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
|
||||||
rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
|
rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
|
||||||
rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
|
rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
|
||||||
rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
|
rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
|
||||||
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
|
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
|
||||||
|
|
||||||
|
@ -795,13 +795,13 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
||||||
entry_priv->desc_dma);
|
entry_priv->desc_dma);
|
||||||
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
|
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
|
||||||
|
|
||||||
entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
|
entry_priv = rt2x00dev->atim->entries[0].priv_data;
|
||||||
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
|
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
|
||||||
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
|
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
|
||||||
entry_priv->desc_dma);
|
entry_priv->desc_dma);
|
||||||
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
|
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
|
||||||
|
|
||||||
entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
|
entry_priv = rt2x00dev->bcn->entries[0].priv_data;
|
||||||
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
|
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
|
||||||
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
|
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
|
||||||
entry_priv->desc_dma);
|
entry_priv->desc_dma);
|
||||||
|
|
|
@ -865,7 +865,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
||||||
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
|
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
|
||||||
rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
|
rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
|
||||||
rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
|
rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
|
||||||
rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
|
rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
|
||||||
rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
|
rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
|
||||||
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
|
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
|
||||||
|
|
||||||
|
@ -881,13 +881,13 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
||||||
entry_priv->desc_dma);
|
entry_priv->desc_dma);
|
||||||
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
|
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
|
||||||
|
|
||||||
entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
|
entry_priv = rt2x00dev->atim->entries[0].priv_data;
|
||||||
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
|
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
|
||||||
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
|
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
|
||||||
entry_priv->desc_dma);
|
entry_priv->desc_dma);
|
||||||
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
|
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
|
||||||
|
|
||||||
entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
|
entry_priv = rt2x00dev->bcn->entries[0].priv_data;
|
||||||
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
|
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
|
||||||
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
|
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
|
||||||
entry_priv->desc_dma);
|
entry_priv->desc_dma);
|
||||||
|
|
|
@ -887,14 +887,13 @@ struct rt2x00_dev {
|
||||||
struct work_struct txdone_work;
|
struct work_struct txdone_work;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Data queue arrays for RX, TX and Beacon.
|
* Data queue arrays for RX, TX, Beacon and ATIM.
|
||||||
* The Beacon array also contains the Atim queue
|
|
||||||
* if that is supported by the device.
|
|
||||||
*/
|
*/
|
||||||
unsigned int data_queues;
|
unsigned int data_queues;
|
||||||
struct data_queue *rx;
|
struct data_queue *rx;
|
||||||
struct data_queue *tx;
|
struct data_queue *tx;
|
||||||
struct data_queue *bcn;
|
struct data_queue *bcn;
|
||||||
|
struct data_queue *atim;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Firmware image.
|
* Firmware image.
|
||||||
|
|
|
@ -708,21 +708,17 @@ EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
|
||||||
struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
|
struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
|
||||||
const enum data_queue_qid queue)
|
const enum data_queue_qid queue)
|
||||||
{
|
{
|
||||||
int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
|
|
||||||
|
|
||||||
if (queue == QID_RX)
|
if (queue == QID_RX)
|
||||||
return rt2x00dev->rx;
|
return rt2x00dev->rx;
|
||||||
|
|
||||||
if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
|
if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
|
||||||
return &rt2x00dev->tx[queue];
|
return &rt2x00dev->tx[queue];
|
||||||
|
|
||||||
if (!rt2x00dev->bcn)
|
|
||||||
return NULL;
|
|
||||||
|
|
||||||
if (queue == QID_BEACON)
|
if (queue == QID_BEACON)
|
||||||
return &rt2x00dev->bcn[0];
|
return rt2x00dev->bcn;
|
||||||
else if (queue == QID_ATIM && atim)
|
|
||||||
return &rt2x00dev->bcn[1];
|
if (queue == QID_ATIM)
|
||||||
|
return rt2x00dev->atim;
|
||||||
|
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
@ -1103,7 +1099,7 @@ int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
|
||||||
goto exit;
|
goto exit;
|
||||||
|
|
||||||
if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
|
if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
|
||||||
status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
|
status = rt2x00queue_alloc_entries(rt2x00dev->atim,
|
||||||
rt2x00dev->ops->atim);
|
rt2x00dev->ops->atim);
|
||||||
if (status)
|
if (status)
|
||||||
goto exit;
|
goto exit;
|
||||||
|
@ -1177,6 +1173,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
|
||||||
rt2x00dev->rx = queue;
|
rt2x00dev->rx = queue;
|
||||||
rt2x00dev->tx = &queue[1];
|
rt2x00dev->tx = &queue[1];
|
||||||
rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
|
rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
|
||||||
|
rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Initialize queue parameters.
|
* Initialize queue parameters.
|
||||||
|
@ -1193,9 +1190,9 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
|
||||||
tx_queue_for_each(rt2x00dev, queue)
|
tx_queue_for_each(rt2x00dev, queue)
|
||||||
rt2x00queue_init(rt2x00dev, queue, qid++);
|
rt2x00queue_init(rt2x00dev, queue, qid++);
|
||||||
|
|
||||||
rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
|
rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
|
||||||
if (req_atim)
|
if (req_atim)
|
||||||
rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
|
rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue