rt2x00: Don't treat ATIM queue as second beacon queue.
Current code for the atim queue is strange, as it is considered in the rt2x00_dev structure as a second beacon queue. Normalize this by letting the atim queue have its own struct data_queue pointer in the rt2x00_dev structure. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -779,7 +779,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
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rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
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rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
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rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
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rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
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rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
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rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
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rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
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@ -795,13 +795,13 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
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entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
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entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
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entry_priv = rt2x00dev->atim->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
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entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
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entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
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entry_priv = rt2x00dev->bcn->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
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entry_priv->desc_dma);
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@ -865,7 +865,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
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rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
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rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
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rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
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rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
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rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
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rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
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rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
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@ -881,13 +881,13 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
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entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
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entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
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entry_priv = rt2x00dev->atim->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
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rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
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entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
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entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
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entry_priv = rt2x00dev->bcn->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
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rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
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entry_priv->desc_dma);
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@ -887,14 +887,13 @@ struct rt2x00_dev {
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struct work_struct txdone_work;
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/*
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* Data queue arrays for RX, TX and Beacon.
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* The Beacon array also contains the Atim queue
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* if that is supported by the device.
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* Data queue arrays for RX, TX, Beacon and ATIM.
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*/
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unsigned int data_queues;
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struct data_queue *rx;
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struct data_queue *tx;
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struct data_queue *bcn;
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struct data_queue *atim;
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/*
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* Firmware image.
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@ -708,21 +708,17 @@ EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
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struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
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const enum data_queue_qid queue)
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{
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int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
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if (queue == QID_RX)
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return rt2x00dev->rx;
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if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
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return &rt2x00dev->tx[queue];
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if (!rt2x00dev->bcn)
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return NULL;
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if (queue == QID_BEACON)
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return &rt2x00dev->bcn[0];
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else if (queue == QID_ATIM && atim)
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return &rt2x00dev->bcn[1];
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return rt2x00dev->bcn;
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if (queue == QID_ATIM)
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return rt2x00dev->atim;
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return NULL;
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}
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@ -1103,7 +1099,7 @@ int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
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goto exit;
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if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
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status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
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status = rt2x00queue_alloc_entries(rt2x00dev->atim,
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rt2x00dev->ops->atim);
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if (status)
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goto exit;
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@ -1177,6 +1173,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
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rt2x00dev->rx = queue;
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rt2x00dev->tx = &queue[1];
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rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
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rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
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/*
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* Initialize queue parameters.
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@ -1193,9 +1190,9 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
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tx_queue_for_each(rt2x00dev, queue)
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rt2x00queue_init(rt2x00dev, queue, qid++);
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rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
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rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
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if (req_atim)
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rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
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rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
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return 0;
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}
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