PCI: keystone: Cleanup outbound window configuration
Outbound translation window is configured in order to access the PCIe card's MEM space. Cleanup outbound translation configuration here by using BIT() macros, adding a macro for window size and using lower_32_bits/upper_32_bits macros for configuring the 64 bit offset in the outbound translation region. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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@ -41,7 +41,7 @@
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#define LTSSM_STATE_MASK 0x1f
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#define LTSSM_STATE_L0 0x11
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#define DBI_CS2_EN_VAL 0x20
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#define OB_XLAT_EN_VAL 2
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#define OB_XLAT_EN_VAL BIT(1)
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/* Application registers */
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#define CMD_STATUS 0x004
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@ -53,10 +53,11 @@
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#define CFG_TYPE1 BIT(24)
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#define OB_SIZE 0x030
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#define CFG_PCIM_WIN_SZ_IDX 3
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#define SPACE0_REMOTE_CFG_OFFSET 0x1000
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#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
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#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
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#define OB_ENABLEN BIT(0)
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#define OB_WIN_SIZE 8 /* 8MB */
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/* IRQ register defines */
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#define IRQ_EOI 0x050
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@ -341,12 +342,13 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
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static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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u32 num_viewport = ks_pcie->num_viewport;
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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u32 start = pp->mem->start, end = pp->mem->end;
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int i, tr_size;
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u32 val;
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u64 start = pp->mem->start;
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u64 end = pp->mem->end;
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int i;
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/* Disable BARs for inbound access */
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ks_pcie_set_dbi_mode(ks_pcie);
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@ -354,21 +356,21 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
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ks_pcie_clear_dbi_mode(ks_pcie);
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/* Set outbound translation size per window division */
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ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
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tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
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val = ilog2(OB_WIN_SIZE);
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ks_pcie_app_writel(ks_pcie, OB_SIZE, val);
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/* Using Direct 1:1 mapping of RC <-> PCI memory space */
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for (i = 0; (i < num_viewport) && (start < end); i++) {
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ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
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ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
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start += tr_size;
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for (i = 0; i < num_viewport && (start < end); i++) {
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ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i),
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lower_32_bits(start) | OB_ENABLEN);
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ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i),
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upper_32_bits(start));
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start += OB_WIN_SIZE;
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}
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/* Enable OB translation */
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val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
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val |= OB_XLAT_EN_VAL;
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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}
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static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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