serial: 8250_pci: all known Braswell ports are 1 channel
There is no need to have channel offset defined since all BayTrail and Braswell ports are 1 channel. Remove unneeded definition. While here, remove comment which has no value. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -3698,15 +3698,10 @@ static struct pciserial_board pci_boards[] = {
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.base_baud = 921600,
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.base_baud = 921600,
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.reg_shift = 2,
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.reg_shift = 2,
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},
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},
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/*
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* Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
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* but is overridden by byt_set_termios.
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*/
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[pbn_byt] = {
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[pbn_byt] = {
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.flags = FL_BASE0,
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.flags = FL_BASE0,
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.num_ports = 1,
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.num_ports = 1,
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.base_baud = 2764800,
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.base_baud = 2764800,
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.uart_offset = 0x80,
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.reg_shift = 2,
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.reg_shift = 2,
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},
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},
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[pbn_qrk] = {
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[pbn_qrk] = {
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