Merge remote-tracking branch 'asoc/topic/cs4271' into asoc-next
This commit is contained in:
commit
e790245eb3
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@ -20,6 +20,18 @@ Optional properties:
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!RESET pin
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- cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
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is enabled.
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- cirrus,enable-soft-reset:
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The CS4271 requires its LRCLK and MCLK to be stable before its RESET
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line is de-asserted. That also means that clocks cannot be changed
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without putting the chip back into hardware reset, which also requires
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a complete re-initialization of all registers.
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One (undocumented) workaround is to assert and de-assert the PDN bit
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in the MODE2 register. This workaround can be enabled with this DT
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property.
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Note that this is not needed in case the clocks are stable
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throughout the entire runtime of the codec.
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Examples:
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@ -20,6 +20,21 @@
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struct cs4271_platform_data {
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int gpio_nreset; /* GPIO driving Reset pin, if any */
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bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */
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/*
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* The CS4271 requires its LRCLK and MCLK to be stable before its RESET
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* line is de-asserted. That also means that clocks cannot be changed
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* without putting the chip back into hardware reset, which also requires
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* a complete re-initialization of all registers.
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*
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* One (undocumented) workaround is to assert and de-assert the PDN bit
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* in the MODE2 register. This workaround can be enabled with the
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* following flag.
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*
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* Note that this is not needed in case the clocks are stable
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* throughout the entire runtime of the codec.
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*/
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bool enable_soft_reset;
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};
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#endif /* __CS4271_H */
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@ -167,6 +167,8 @@ struct cs4271_private {
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int gpio_nreset;
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/* GPIO that disable serial bus, if any */
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int gpio_disable;
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/* enable soft reset workaround */
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bool enable_soft_reset;
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};
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/*
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@ -325,6 +327,33 @@ static int cs4271_hw_params(struct snd_pcm_substream *substream,
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int i, ret;
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unsigned int ratio, val;
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if (cs4271->enable_soft_reset) {
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/*
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* Put the codec in soft reset and back again in case it's not
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* currently streaming data. This way of bringing the codec in
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* sync to the current clocks is not explicitly documented in
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* the data sheet, but it seems to work fine, and in contrast
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* to a read hardware reset, we don't have to sync back all
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* registers every time.
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*/
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if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
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!dai->capture_active) ||
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(substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
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!dai->playback_active)) {
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ret = snd_soc_update_bits(codec, CS4271_MODE2,
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CS4271_MODE2_PDN,
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CS4271_MODE2_PDN);
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if (ret < 0)
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return ret;
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ret = snd_soc_update_bits(codec, CS4271_MODE2,
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CS4271_MODE2_PDN, 0);
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if (ret < 0)
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return ret;
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}
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}
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cs4271->rate = params_rate(params);
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/* Configure DAC */
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@ -484,6 +513,10 @@ static int cs4271_probe(struct snd_soc_codec *codec)
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if (of_get_property(codec->dev->of_node,
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"cirrus,amutec-eq-bmutec", NULL))
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amutec_eq_bmutec = true;
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if (of_get_property(codec->dev->of_node,
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"cirrus,enable-soft-reset", NULL))
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cs4271->enable_soft_reset = true;
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}
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#endif
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@ -492,6 +525,7 @@ static int cs4271_probe(struct snd_soc_codec *codec)
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gpio_nreset = cs4271plat->gpio_nreset;
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amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
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cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
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}
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if (gpio_nreset >= 0)
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