drm/nouveau/clk/gk20a: rename enable/disable functions
gk20a_pllg_disable() is only used in the context of gk20a_clk_fini(). Move its body there and rename _gk20a_pllg_enable() and _gk20a_pllg_disable() to non-underscored versions. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -329,17 +329,19 @@ gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
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}
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static void
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_gk20a_pllg_enable(struct gk20a_clk *clk)
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gk20a_pllg_enable(struct gk20a_clk *clk)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
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nvkm_rd32(device, GPCPLL_CFG);
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}
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static void
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_gk20a_pllg_disable(struct gk20a_clk *clk)
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gk20a_pllg_disable(struct gk20a_clk *clk)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
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nvkm_rd32(device, GPCPLL_CFG);
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}
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@ -393,7 +395,7 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
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udelay(2);
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}
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_gk20a_pllg_disable(clk);
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gk20a_pllg_disable(clk);
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nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__,
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clk->m, clk->n, clk->pl);
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@ -405,7 +407,7 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
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val |= clk->pl << GPCPLL_COEFF_P_SHIFT;
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nvkm_wr32(device, GPCPLL_COEFF, val);
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_gk20a_pllg_enable(clk);
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gk20a_pllg_enable(clk);
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val = nvkm_rd32(device, GPCPLL_CFG);
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if (val & GPCPLL_CFG_LOCK_DET_OFF) {
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@ -444,30 +446,6 @@ gk20a_pllg_program_mnp(struct gk20a_clk *clk)
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return err;
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}
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static void
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gk20a_pllg_disable(struct gk20a_clk *clk)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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u32 val;
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/* slide to VCO min */
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val = nvkm_rd32(device, GPCPLL_CFG);
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if (val & GPCPLL_CFG_ENABLE) {
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u32 coeff, m, n_lo;
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coeff = nvkm_rd32(device, GPCPLL_COEFF);
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m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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n_lo = DIV_ROUND_UP(m * clk->params->min_vco,
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clk->parent_rate / KHZ);
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gk20a_pllg_slide(clk, n_lo);
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}
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/* put PLL in bypass before disabling it */
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nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
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_gk20a_pllg_disable(clk);
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}
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#define GK20A_CLK_GPC_MDIV 1000
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static struct nvkm_pstate
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@ -608,7 +586,25 @@ gk20a_clk_tidy(struct nvkm_clk *base)
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static void
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gk20a_clk_fini(struct nvkm_clk *base)
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{
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struct nvkm_device *device = base->subdev.device;
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struct gk20a_clk *clk = gk20a_clk(base);
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u32 val;
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/* slide to VCO min */
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val = nvkm_rd32(device, GPCPLL_CFG);
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if (val & GPCPLL_CFG_ENABLE) {
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u32 coef, m, n_lo;
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coef = nvkm_rd32(device, GPCPLL_COEFF);
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m = (coef >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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n_lo = DIV_ROUND_UP(m * clk->params->min_vco,
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clk->parent_rate / KHZ);
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gk20a_pllg_slide(clk, n_lo);
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}
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/* put PLL in bypass before disabling it */
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nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
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gk20a_pllg_disable(clk);
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}
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