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ARM: SoC platform updates for v4.10 

These are updates for platform specific code on 32-bit ARM machines,
 essentially anything that can not (yet) be expressed using DT files.
 
 Noteworthy changes include:
 
 - Added support for the TI DRA71x family of SoCs in mach-omap2,
   this is an new variant of the the DRA72x/DRA74x automotive
   infotainment chips we already supported for a while.
 
 - Added support for the ST STM32F746 SoC, the first Cortex-M7
   based microcontroller we support, related to the smaller
   STM32F4 family.
 
 - Renesas adds support for r8a7743 and r8a7745 in mach-shmobile,
   see http://elinux.org/RZ-G
 
 - SMP is now supported on the OX820 platform
 
 - A lot of code in mach-omap2 gets removed as a follow-up to
   removing support for board files in the previous release
 
 - Davinci has some new work to improve USB support
 
 - For i.MX, the performance monitor now supports profiling the
   memory controller using 'perf'
 
 Conflicts:
 arch/arm/mach-shmobile/setup-rcar-gen2.c: rcar_gen2_clocks_init()
 is gone, calling of_clk_init(NULL) is sufficient now.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "These are updates for platform specific code on 32-bit ARM machines,
  essentially anything that can not (yet) be expressed using DT files.

  Noteworthy changes include:

   - Added support for the TI DRA71x family of SoCs in mach-omap2, this
     is an new variant of the the DRA72x/DRA74x automotive infotainment
     chips we already supported for a while.

   - Added support for the ST STM32F746 SoC, the first Cortex-M7 based
     microcontroller we support, related to the smaller STM32F4 family.

   - Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see
     http://elinux.org/RZ-G

   - SMP is now supported on the OX820 platform

   - A lot of code in mach-omap2 gets removed as a follow-up to removing
     support for board files in the previous release

   - Davinci has some new work to improve USB support

   - For i.MX, the performance monitor now supports profiling the memory
     controller using 'perf'"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits)
  ARM: davinci: da830-evm: use gpio descriptor for mmc pins
  ARM: davinci: da850-evm: use gpio descriptor for mmc pins
  ARM: davinci: hawk: use gpio descriptor for mmc pins
  ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6
  ARM: davinci: da8xx: Fix ohci device name
  ARM: oxnas: Add OX820 config and makefile entry
  ARM: oxnas: Add OX820 SMP support
  ARM: davinci: PM: fix build when da850 not compiled in
  ARM: orion5x: remove legacy support of ls-chl
  ARM: integrator: drop EBI access use syscon
  ARM: BCM5301X: Add back handler ignoring external imprecise aborts
  ARM: davinci: PM: support da8xx DT platforms
  ARM: davinci: PM: cleanup: remove references to pdata
  ARM: davinci: PM: rework init, remove platform device
  ARM: Kconfig: Introduce MACH_STM32F746 flag
  ARM: mach-stm32: Add a new SOC - STM32F746
  ARM: shmobile: document SK-RZG1E board
  ARM: shmobile: r8a7745: basic SoC support
  ARM: imx: mach-imx6ul: add imx6ull support
  ARM: zynq: Reserve correct amount of non-DMA RAM
  ...
hifive-unleashed-5.1
Linus Torvalds 2016-12-15 15:39:02 -08:00
parent 3ec5e8d82b 44c29b83de
commit e79ab194d1
126 changed files with 2146 additions and 9599 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/arm/stm32/overview.txt
View File

@ -5,7 +5,8 @@ Introduction
------------
The STMicroelectronics family of Cortex-M based MCUs are supported by the
'STM32' platform of ARM Linux. Currently only the STM32F429 is supported.
'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
and STM32F746 (Cortex-M7) are supported.
Configuration

34
Documentation/arm/stm32/stm32f746-overview.txt 100644
View File

@ -0,0 +1,34 @@
STM32F746 Overview
==================
Introduction
------------
The STM32F746 is a Cortex-M7 MCU aimed at various applications.
It features:
- Cortex-M7 core running up to @216MHz
- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- FMC controller to connect SDRAM, NOR and NAND memories
- Dual mode QSPI
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C, SPI, CAN busses support
- Several 16 & 32 bits general purpose timers
- Serial Audio interface
- LCD controller
- HDMI-CEC
- SPDIFRX
Resources
---------
Datasheet and reference manual are publicly available on ST website:
- http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
Document Author
---------------
Alexandre Torgue <alexandre.torgue@st.com>

6
Documentation/devicetree/bindings/arm/omap/omap.txt
View File

@ -86,6 +86,9 @@ SoCs:
- DRA722
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
- DRA718
compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
- AM5728
compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
@ -181,6 +184,9 @@ Boards:
- DRA722 EVM: Software Development Board for DRA722
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"
- DRA718 EVM: Software Development Board for DRA718
compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"

14
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -13,6 +13,10 @@ SoCs:
compatible = "renesas,r8a73a4"
- R-Mobile A1 (R8A77400)
compatible = "renesas,r8a7740"
- RZ/G1M (R8A77430)
compatible = "renesas,r8a7743"
- RZ/G1E (R8A77450)
compatible = "renesas,r8a7745"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
@ -35,7 +39,7 @@ SoCs:
Boards:
- Alt
- Alt (RTP0RC7794SEB00010S)
compatible = "renesas,alt", "renesas,r8a7794"
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
@ -47,7 +51,7 @@ Boards:
compatible = "renesas,bockw", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- Gose
- Gose (RTP0RC7793SEB00010S)
compatible = "renesas,gose", "renesas,r8a7793"
- H3ULCB (RTP0RC7795SKB00010S)
compatible = "renesas,h3ulcb", "renesas,r8a7795";
@ -61,7 +65,7 @@ Boards:
compatible = "renesas,kzm9g", "renesas,sh73a0"
- Lager (RTP0RC7790SEB00010S)
compatible = "renesas,lager", "renesas,r8a7790"
- Marzen
- Marzen (R0P7779A00010S)
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
compatible = "renesas,porter", "renesas,r8a7791"
@ -73,5 +77,9 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- Wheat
compatible = "renesas,wheat", "renesas,r8a7792"

5
arch/arm/Kconfig
View File

@ -888,6 +888,11 @@ config MACH_STM32F429
depends on ARCH_STM32
default y
config MACH_STM32F746
bool "STMicrolectronics STM32F746"
depends on ARCH_STM32
default y
config ARCH_MPS2
bool "ARM MPS2 platform"
depends on ARM_SINGLE_ARMV7M

1
arch/arm/Makefile
View File

@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX) += netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
machine-$(CONFIG_ARCH_NSPIRE) += nspire
machine-$(CONFIG_ARCH_OXNAS) += oxnas
machine-$(CONFIG_ARCH_OMAP1) += omap1
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x

1
arch/arm/mach-artpec/Kconfig
View File

@ -14,6 +14,7 @@ config MACH_ARTPEC6
select HAVE_ARM_ARCH_TIMER
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select MFD_SYSCON
help
Support for Axis ARTPEC-6 ARM Cortex A9 Platform

28
arch/arm/mach-bcm/bcm_5301x.c
View File

@ -9,14 +9,42 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/siginfo.h>
#include <asm/signal.h>
#define FSR_EXTERNAL (1 << 12)
#define FSR_READ (0 << 10)
#define FSR_IMPRECISE 0x0406
static const char *const bcm5301x_dt_compat[] __initconst = {
"brcm,bcm4708",
NULL,
};
static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
struct pt_regs *regs)
{
/*
* We want to ignore aborts forwarded from the PCIe bus that are
* expected and shouldn't really be passed by the PCIe controller.
* The biggest disadvantage is the same FSR code may be reported when
* reading non-existing APB register and we shouldn't ignore that.
*/
if (fsr == (FSR_EXTERNAL | FSR_READ | FSR_IMPRECISE))
return 0;
return 1;
}
static void __init bcm5301x_init_early(void)
{
hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
"imprecise external abort");
}
DT_MACHINE_START(BCM5301X, "BCM5301X")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.dt_compat = bcm5301x_dt_compat,
.init_early = bcm5301x_init_early,
MACHINE_END

4
arch/arm/mach-davinci/Makefile
View File

@ -36,5 +36,7 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
# Power Management
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_HAVE_CLK) += pm_domain.o
ifeq ($(CONFIG_SUSPEND),y)
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pm.o sleep.o
endif

97
arch/arm/mach-davinci/board-da830-evm.c
View File

@ -14,6 +14,7 @@
#include <linux/console.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c/pcf857x.h>
@ -27,6 +28,7 @@
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/spi-davinci.h>
#include <linux/platform_data/usb-davinci.h>
#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -106,43 +108,24 @@ static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id)
static __init void da830_evm_usb_init(void)
{
u32 cfgchip2;
int ret;
/*
* Set up USB clock/mode in the CFGCHIP2 register.
* FYI: CFGCHIP2 is 0x0000ef00 initially.
*/
cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
/* USB2.0 PHY reference clock is 24 MHz */
cfgchip2 &= ~CFGCHIP2_REFFREQ;
cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
/*
* Select internal reference clock for USB 2.0 PHY
* and use it as a clock source for USB 1.1 PHY
* (this is the default setting anyway).
*/
cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX;
/*
* We have to override VBUS/ID signals when MUSB is configured into the
* host-only mode -- ID pin will float if no cable is connected, so the
* controller won't be able to drive VBUS thinking that it's a B-device.
* Otherwise, we want to use the OTG mode and enable VBUS comparators.
*/
cfgchip2 &= ~CFGCHIP2_OTGMODE;
#ifdef CONFIG_USB_MUSB_HOST
cfgchip2 |= CFGCHIP2_FORCE_HOST;
#else
cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
#endif
__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
/* USB_REFCLKIN is not used. */
ret = da8xx_register_usb20_phy_clk(false);
if (ret)
pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
__func__, ret);
ret = da8xx_register_usb11_phy_clk(false);
if (ret)
pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
__func__, ret);
ret = da8xx_register_usb_phy();
if (ret)
pr_warn("%s: USB PHY registration failed: %d\n",
__func__, ret);
ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
if (ret)
pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret);
@ -222,22 +205,16 @@ static const short da830_evm_mmc_sd_pins[] = {
-1
};
#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
static int da830_evm_mmc_get_ro(int index)
{
return gpio_get_value(DA830_MMCSD_WP_PIN);
}
static int da830_evm_mmc_get_cd(int index)
{
return !gpio_get_value(DA830_MMCSD_CD_PIN);
}
static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* gpio chip 1 contains gpio range 32-63 */
GPIO_LOOKUP("davinci_gpio.1", 2, "cd", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.1", 1, "wp", GPIO_ACTIVE_LOW),
},
};
static struct davinci_mmc_config da830_evm_mmc_config = {
.get_ro = da830_evm_mmc_get_ro,
.get_cd = da830_evm_mmc_get_cd,
.wires = 8,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
@ -253,26 +230,12 @@ static inline void da830_evm_init_mmc(void)
return;
}
ret = gpio_request(DA830_MMCSD_WP_PIN, "MMC WP");
if (ret) {
pr_warn("%s: can not open GPIO %d\n",
__func__, DA830_MMCSD_WP_PIN);
return;
}
gpio_direction_input(DA830_MMCSD_WP_PIN);
ret = gpio_request(DA830_MMCSD_CD_PIN, "MMC CD\n");
if (ret) {
pr_warn("%s: can not open GPIO %d\n",
__func__, DA830_MMCSD_CD_PIN);
return;
}
gpio_direction_input(DA830_MMCSD_CD_PIN);
gpiod_add_lookup_table(&mmc_gpios_table);
ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
if (ret) {
pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret);
gpio_free(DA830_MMCSD_WP_PIN);
gpiod_remove_lookup_table(&mmc_gpios_table);
}
}
@ -588,6 +551,10 @@ static __init void da830_evm_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
ret = da830_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@ -647,6 +614,8 @@ static __init void da830_evm_init(void)
ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
if (ret)
pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret);
regulator_has_full_constraints();
}
#ifdef CONFIG_SERIAL_8250_CONSOLE

56
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/gpio/machine.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/i2c.h>
@ -56,9 +57,6 @@
#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
static struct mtd_partition da850evm_spiflash_part[] = {
@ -196,18 +194,6 @@ static struct platform_device da850_evm_norflash_device = {
.resource = da850_evm_norflash_resource,
};
static struct davinci_pm_config da850_pm_pdata = {
.sleepcount = 128,
};
static struct platform_device da850_pm_device = {
.name = "pm-davinci",
.dev = {
.platform_data = &da850_pm_pdata,
},
.id = -1,
};
/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
* (128K blocks). It may be used instead of the (default) SPI flash
* to boot, using TI's tools to install the secondary boot loader
@ -776,19 +762,16 @@ static const short da850_evm_mcasp_pins[] __initconst = {
-1
};
static int da850_evm_mmc_get_ro(int index)
{
return gpio_get_value(DA850_MMCSD_WP_PIN);
}
static int da850_evm_mmc_get_cd(int index)
{
return !gpio_get_value(DA850_MMCSD_CD_PIN);
}
static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* gpio chip 2 contains gpio range 64-95 */
GPIO_LOOKUP("davinci_gpio.2", 0, "cd", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.2", 1, "wp", GPIO_ACTIVE_LOW),
},
};
static struct davinci_mmc_config da850_mmc_config = {
.get_ro = da850_evm_mmc_get_ro,
.get_cd = da850_evm_mmc_get_cd,
.wires = 4,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
@ -1345,6 +1328,10 @@ static __init void da850_evm_init(void)
{
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@ -1379,17 +1366,7 @@ static __init void da850_evm_init(void)
pr_warn("%s: MMCSD0 mux setup failed: %d\n",
__func__, ret);
ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
if (ret)
pr_warn("%s: can not open GPIO %d\n",
__func__, DA850_MMCSD_CD_PIN);
gpio_direction_input(DA850_MMCSD_CD_PIN);
ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
if (ret)
pr_warn("%s: can not open GPIO %d\n",
__func__, DA850_MMCSD_WP_PIN);
gpio_direction_input(DA850_MMCSD_WP_PIN);
gpiod_add_lookup_table(&mmc_gpios_table);
ret = da8xx_register_mmcsd0(&da850_mmc_config);
if (ret)
@ -1453,10 +1430,7 @@ static __init void da850_evm_init(void)
if (ret)
pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
ret = da850_register_pm(&da850_pm_device);
if (ret)
pr_warn("%s: suspend registration failed: %d\n", __func__, ret);
davinci_pm_init();
da850_vpif_init();
ret = spi_register_board_info(da850evm_spi_info,

20
arch/arm/mach-davinci/board-mityomapl138.c
View File

@ -498,22 +498,14 @@ static void __init mityomapl138_config_emac(void)
pr_warn("emac registration failed: %d\n", ret);
}
static struct davinci_pm_config da850_pm_pdata = {
.sleepcount = 128,
};
static struct platform_device da850_pm_device = {
.name = "pm-davinci",
.dev = {
.platform_data = &da850_pm_pdata,
},
.id = -1,
};
static void __init mityomapl138_init(void)
{
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
/* for now, no special EDMA channels are reserved */
ret = da850_register_edma(NULL);
if (ret)
@ -555,9 +547,7 @@ static void __init mityomapl138_init(void)
if (ret)
pr_warn("cpuidle registration failed: %d\n", ret);
ret = da850_register_pm(&da850_pm_device);
if (ret)
pr_warn("suspend registration failed: %d\n", ret);
davinci_pm_init();
}
#ifdef CONFIG_SERIAL_8250_CONSOLE

68
arch/arm/mach-davinci/board-omapl138-hawk.c
View File

@ -13,7 +13,9 @@
#include <linux/init.h>
#include <linux/console.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -24,8 +26,6 @@
#include <mach/mux.h>
#define HAWKBOARD_PHY_ID "davinci_mdio-0:07"
#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4)
#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13)
@ -122,19 +122,16 @@ static const short hawk_mmcsd0_pins[] = {
-1
};
static int da850_hawk_mmc_get_ro(int index)
{
return gpio_get_value(DA850_HAWK_MMCSD_WP_PIN);
}
static int da850_hawk_mmc_get_cd(int index)
{
return !gpio_get_value(DA850_HAWK_MMCSD_CD_PIN);
}
static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/
GPIO_LOOKUP("davinci_gpio.1", 28, "cd", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.1", 29, "wp", GPIO_ACTIVE_LOW),
},
};
static struct davinci_mmc_config da850_mmc_config = {
.get_ro = da850_hawk_mmc_get_ro,
.get_cd = da850_hawk_mmc_get_cd,
.wires = 4,
.max_freq = 50000000,
.caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
@ -150,21 +147,7 @@ static __init void omapl138_hawk_mmc_init(void)
return;
}
ret = gpio_request_one(DA850_HAWK_MMCSD_CD_PIN,
GPIOF_DIR_IN, "MMC CD");
if (ret < 0) {
pr_warn("%s: can not open GPIO %d\n",
__func__, DA850_HAWK_MMCSD_CD_PIN);
return;
}
ret = gpio_request_one(DA850_HAWK_MMCSD_WP_PIN,
GPIOF_DIR_IN, "MMC WP");
if (ret < 0) {
pr_warn("%s: can not open GPIO %d\n",
__func__, DA850_HAWK_MMCSD_WP_PIN);
goto mmc_setup_wp_fail;
}
gpiod_add_lookup_table(&mmc_gpios_table);
ret = da8xx_register_mmcsd0(&da850_mmc_config);
if (ret) {
@ -175,9 +158,7 @@ static __init void omapl138_hawk_mmc_init(void)
return;
mmc_setup_mmcsd_fail:
gpio_free(DA850_HAWK_MMCSD_WP_PIN);
mmc_setup_wp_fail:
gpio_free(DA850_HAWK_MMCSD_CD_PIN);
gpiod_remove_lookup_table(&mmc_gpios_table);
}
static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id);
@ -243,7 +224,6 @@ static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
static __init void omapl138_hawk_usb_init(void)
{
int ret;
u32 cfgchip2;
ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
if (ret) {
@ -251,12 +231,20 @@ static __init void omapl138_hawk_usb_init(void)
return;
}
/* Setup the Ref. clock frequency for the HAWK at 24 MHz. */
ret = da8xx_register_usb20_phy_clk(false);
if (ret)
pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
__func__, ret);
cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
cfgchip2 &= ~CFGCHIP2_REFFREQ;
cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
ret = da8xx_register_usb11_phy_clk(false);
if (ret)
pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
__func__, ret);
ret = da8xx_register_usb_phy();
if (ret)
pr_warn("%s: USB PHY registration failed: %d\n",
__func__, ret);
ret = gpio_request_one(DA850_USB1_VBUS_PIN,
GPIOF_DIR_OUT, "USB1 VBUS");
@ -292,6 +280,10 @@ static __init void omapl138_hawk_init(void)
{
int ret;
ret = da8xx_register_cfgchip();
if (ret)
pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@ -317,6 +309,8 @@ static __init void omapl138_hawk_init(void)
if (ret)
pr_warn("%s: dsp/rproc registration failed: %d\n",
__func__, ret);
regulator_has_full_constraints();
}
#ifdef CONFIG_SERIAL_8250_CONSOLE

1
arch/arm/mach-davinci/common.c
View File

@ -118,6 +118,5 @@ err:
void __init davinci_init_late(void)
{
davinci_cpufreq_init();
davinci_pm_init();
davinci_clk_disable_unused();
}

4
arch/arm/mach-davinci/da830.c
View File

@ -412,7 +412,7 @@ static struct clk_lookup da830_clks[] = {
CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
CLK("davinci-mcasp.2", NULL, &mcasp2_clk),
CLK(NULL, "usb20", &usb20_clk),
CLK("musb-da8xx", "usb20", &usb20_clk),
CLK(NULL, "aemif", &aemif_clk),
CLK(NULL, "aintc", &aintc_clk),
CLK(NULL, "secu_mgr", &secu_mgr_clk),
@ -420,7 +420,7 @@ static struct clk_lookup da830_clks[] = {
CLK("davinci_mdio.0", "fck", &emac_clk),
CLK(NULL, "gpio", &gpio_clk),
CLK("i2c_davinci.2", NULL, &i2c1_clk),
CLK(NULL, "usb11", &usb11_clk),
CLK("ohci-da8xx", "usb11", &usb11_clk),
CLK(NULL, "emif3", &emif3_clk),
CLK(NULL, "arm", &arm_clk),
CLK(NULL, "rmii", &rmii_clk),

42
arch/arm/mach-davinci/da850.c
View File

@ -538,8 +538,8 @@ static struct clk_lookup da850_clks[] = {
CLK("da830-mmc.1", NULL, &mmcsd1_clk),
CLK("ti-aemif", NULL, &aemif_clk),
CLK(NULL, "aemif", &aemif_clk),
CLK(NULL, "usb11", &usb11_clk),
CLK(NULL, "usb20", &usb20_clk),
CLK("ohci-da8xx", "usb11", &usb11_clk),
CLK("musb-da8xx", "usb20", &usb20_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK("vpif", NULL, &vpif_clk),
@ -1214,44 +1214,6 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
}
#endif
int __init da850_register_pm(struct platform_device *pdev)
{
int ret;
struct davinci_pm_config *pdata = pdev->dev.platform_data;
ret = davinci_cfg_reg(DA850_RTC_ALARM);
if (ret)
return ret;
pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
if (!pdata->cpupll_reg_base)
return -ENOMEM;
pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
if (!pdata->ddrpll_reg_base) {
ret = -ENOMEM;
goto no_ddrpll_mem;
}
pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
if (!pdata->ddrpsc_reg_base) {
ret = -ENOMEM;
goto no_ddrpsc_mem;
}
return platform_device_register(pdev);
no_ddrpsc_mem:
iounmap(pdata->ddrpll_reg_base);
no_ddrpll_mem:
iounmap(pdata->cpupll_reg_base);
return ret;
}
/* VPIF resource, platform data */
static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);

16
arch/arm/mach-davinci/da8xx-dt.c
View File

@ -38,6 +38,10 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
NULL),
OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL),
OF_DEV_AUXDATA("ti,da850-tilcdc", 0x01e13000, "da8xx_lcdc.0", NULL),
OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL),
{}
};
@ -45,7 +49,19 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
static void __init da850_init_machine(void)
{
int ret;
ret = da8xx_register_usb20_phy_clk(false);
if (ret)
pr_warn("%s: registering USB 2.0 PHY clock failed: %d",
__func__, ret);
ret = da8xx_register_usb11_phy_clk(false);
if (ret)
pr_warn("%s: registering USB 1.1 PHY clock failed: %d",
__func__, ret);
of_platform_default_populate(NULL, da850_auxdata_lookup, NULL);
davinci_pm_init();
}
static const char *const da850_boards_compat[] __initconst = {

57
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -11,6 +11,7 @@
* (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/platform_data/syscon.h>
#include <linux/platform_device.h>
#include <linux/dma-contiguous.h>
#include <linux/serial_8250.h>
@ -57,15 +58,6 @@
#define DA8XX_EMAC_RAM_OFFSET 0x0000
#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
void __iomem *da8xx_syscfg0_base;
void __iomem *da8xx_syscfg1_base;
@ -964,16 +956,6 @@ static struct resource da8xx_spi0_resources[] = {
.end = IRQ_DA8XX_SPINT0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DA8XX_DMA_SPI0_RX,
.end = DA8XX_DMA_SPI0_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DA8XX_DMA_SPI0_TX,
.end = DA8XX_DMA_SPI0_TX,
.flags = IORESOURCE_DMA,
},
};
static struct resource da8xx_spi1_resources[] = {
@ -987,16 +969,6 @@ static struct resource da8xx_spi1_resources[] = {
.end = IRQ_DA8XX_SPINT1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = DA8XX_DMA_SPI1_RX,
.end = DA8XX_DMA_SPI1_RX,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DA8XX_DMA_SPI1_TX,
.end = DA8XX_DMA_SPI1_TX,
.flags = IORESOURCE_DMA,
},
};
static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
@ -1089,3 +1061,30 @@ int __init da850_register_sata(unsigned long refclkpn)
return platform_device_register(&da850_sata_device);
}
#endif
static struct syscon_platform_data da8xx_cfgchip_platform_data = {
.label = "cfgchip",
};
static struct resource da8xx_cfgchip_resources[] = {
{
.start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG,
.end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device da8xx_cfgchip_device = {
.name = "syscon",
.id = -1,
.dev = {
.platform_data = &da8xx_cfgchip_platform_data,
},
.num_resources = ARRAY_SIZE(da8xx_cfgchip_resources),
.resource = da8xx_cfgchip_resources,
};
int __init da8xx_register_cfgchip(void)
{
return platform_device_register(&da8xx_cfgchip_device);
}

3
arch/arm/mach-davinci/devices.c
View File

@ -36,9 +36,6 @@
#define DM365_MMCSD0_BASE 0x01D11000
#define DM365_MMCSD1_BASE 0x01D00000
#define DAVINCI_DMA_MMCRXEVT 26
#define DAVINCI_DMA_MMCTXEVT 27
void __iomem *davinci_sysmod_base;
void davinci_map_sysmod(void)

8
arch/arm/mach-davinci/dm355.c
View File

@ -397,14 +397,6 @@ static struct resource dm355_spi0_resources[] = {
.start = IRQ_DM355_SPINT0_0,
.flags = IORESOURCE_IRQ,
},
{
.start = 17,
.flags = IORESOURCE_DMA,
},
{
.start = 16,
.flags = IORESOURCE_DMA,
},
};
static struct davinci_spi_platform_data dm355_spi0_pdata = {

8
arch/arm/mach-davinci/dm365.c
View File

@ -660,14 +660,6 @@ static struct resource dm365_spi0_resources[] = {
.start = IRQ_DM365_SPIINT0_0,
.flags = IORESOURCE_IRQ,
},
{
.start = 17,
.flags = IORESOURCE_DMA,
},
{
.start = 16,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device dm365_spi0_device = {

7
arch/arm/mach-davinci/include/mach/da8xx.h
View File

@ -61,6 +61,7 @@ extern unsigned int da850_max_speed;
#define DA8XX_CFGCHIP1_REG 0x180
#define DA8XX_CFGCHIP2_REG 0x184
#define DA8XX_CFGCHIP3_REG 0x188
#define DA8XX_CFGCHIP4_REG 0x18c
#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
@ -88,8 +89,12 @@ int da850_register_edma(struct edma_rsv_info *rsv[2]);
int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
int da8xx_register_spi_bus(int instance, unsigned num_chipselect);
int da8xx_register_watchdog(void);
int da8xx_register_usb_phy(void);
int da8xx_register_usb20(unsigned mA, unsigned potpgt);
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
int da8xx_register_usb_refclkin(int rate);
int da8xx_register_usb20_phy_clk(bool use_usb_refclkin);
int da8xx_register_usb11_phy_clk(bool use_usb_refclkin);
int da8xx_register_emac(void);
int da8xx_register_uio_pruss(void);
int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
@ -101,7 +106,6 @@ int da8xx_register_gpio(void *pdata);
int da850_register_cpufreq(char *async_clk);
int da8xx_register_cpuidle(void);
void __iomem *da8xx_get_mem_ctlr(void);
int da850_register_pm(struct platform_device *pdev);
int da850_register_sata(unsigned long refclkpn);
int da850_register_vpif(void);
int da850_register_vpif_display
@ -113,6 +117,7 @@ void da8xx_rproc_reserve_cma(void);
int da8xx_register_rproc(void);
int da850_register_gpio(void);
int da830_register_gpio(void);
int da8xx_register_cfgchip(void);
extern struct platform_device da8xx_serial_device[];
extern struct emac_platform_data da8xx_emac_pdata;

102
arch/arm/mach-davinci/pm.c
View File

@ -21,15 +21,22 @@
#include <mach/common.h>
#include <mach/da8xx.h>
#include "sram.h"
#include <mach/mux.h>
#include <mach/pm.h>
#include "clock.h"
#include "psc.h"
#include "sram.h"
#define DA850_PLL1_BASE 0x01e1a000
#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
#define DEEPSLEEP_SLEEPCOUNT 128
static void (*davinci_sram_suspend) (struct davinci_pm_config *);
static struct davinci_pm_config *pdata;
static struct davinci_pm_config pm_config = {
.sleepcount = DEEPSLEEP_SLEEPCOUNT,
.ddrpsc_num = DA8XX_LPSC1_EMIF3C,
};
static void davinci_sram_push(void *dest, void *src, unsigned int size)
{
@ -41,58 +48,58 @@ static void davinci_pm_suspend(void)
{
unsigned val;
if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
/* Switch CPU PLL to bypass mode */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
udelay(PLL_BYPASS_TIME);
/* Powerdown CPU PLL */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val |= PLLCTL_PLLPWRDN;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
}
/* Configure sleep count in deep sleep register */
val = __raw_readl(pdata->deepsleep_reg);
val = __raw_readl(pm_config.deepsleep_reg);
val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
val |= pdata->sleepcount;
__raw_writel(val, pdata->deepsleep_reg);
val |= pm_config.sleepcount;
__raw_writel(val, pm_config.deepsleep_reg);
/* System goes to sleep in this call */
davinci_sram_suspend(pdata);
davinci_sram_suspend(&pm_config);
if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
/* put CPU PLL in reset */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLRST;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* put CPU PLL in power down */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLPWRDN;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* wait for CPU PLL reset */
udelay(PLL_RESET_TIME);
/* bring CPU PLL out of reset */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val |= PLLCTL_PLLRST;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
/* Wait for CPU PLL to lock */
udelay(PLL_LOCK_TIME);
/* Remove CPU PLL from bypass mode */
val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
val &= ~PLLCTL_PLLENSRC;
val |= PLLCTL_PLLEN;
__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
}
}
@ -117,17 +124,36 @@ static const struct platform_suspend_ops davinci_pm_ops = {
.valid = suspend_valid_only_mem,
};
static int __init davinci_pm_probe(struct platform_device *pdev)
int __init davinci_pm_init(void)
{
pdata = pdev->dev.platform_data;
if (!pdata) {
dev_err(&pdev->dev, "cannot get platform data\n");
return -ENOENT;
int ret;
ret = davinci_cfg_reg(DA850_RTC_ALARM);
if (ret)
return ret;
pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
if (!pm_config.cpupll_reg_base)
return -ENOMEM;
pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
if (!pm_config.ddrpll_reg_base) {
ret = -ENOMEM;
goto no_ddrpll_mem;
}
pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
if (!pm_config.ddrpsc_reg_base) {
ret = -ENOMEM;
goto no_ddrpsc_mem;
}
davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
if (!davinci_sram_suspend) {
dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
pr_err("PM: cannot allocate SRAM memory\n");
return -ENOMEM;
}
@ -136,23 +162,9 @@ static int __init davinci_pm_probe(struct platform_device *pdev)
suspend_set_ops(&davinci_pm_ops);
return 0;
}
static int __exit davinci_pm_remove(struct platform_device *pdev)
{
sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
return 0;
}
static struct platform_driver davinci_pm_driver = {
.driver = {
.name = "pm-davinci",
},
.remove = __exit_p(davinci_pm_remove),
};
int __init davinci_pm_init(void)
{
return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
no_ddrpsc_mem:
iounmap(pm_config.ddrpll_reg_base);
no_ddrpll_mem:
iounmap(pm_config.cpupll_reg_base);
return ret;
}

280
arch/arm/mach-davinci/usb-da8xx.c
View File

@ -1,21 +1,44 @@
/*
* DA8xx USB
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/mfd/da8xx-cfgchip.h>
#include <linux/phy/phy.h>
#include <linux/platform_data/usb-davinci.h>
#include <linux/platform_device.h>
#include <linux/usb/musb.h>
#include <mach/clock.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/irqs.h>
#include "clock.h"
#define DA8XX_USB0_BASE 0x01e00000
#define DA8XX_USB1_BASE 0x01e25000
#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
static struct platform_device da8xx_usb_phy = {
.name = "da8xx-usb-phy",
.id = -1,
.dev = {
/*
* Setting init_name so that clock lookup will work in
* da8xx_register_usb11_phy_clk() even if this device is not
* registered yet.
*/
.init_name = "da8xx-usb-phy",
},
};
int __init da8xx_register_usb_phy(void)
{
return platform_device_register(&da8xx_usb_phy);
}
static struct musb_hdrc_config musb_config = {
.multipoint = true,
@ -45,10 +68,15 @@ static struct resource da8xx_usb20_resources[] = {
static u64 usb_dmamask = DMA_BIT_MASK(32);
static struct platform_device usb_dev = {
static struct platform_device da8xx_usb20_dev = {
.name = "musb-da8xx",
.id = -1,
.dev = {
/*
* Setting init_name so that clock lookup will work in
* usb20_phy_clk_enable() even if this device is not registered.
*/
.init_name = "musb-da8xx",
.platform_data = &usb_data,
.dma_mask = &usb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
@ -62,18 +90,9 @@ int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
usb_data.power = mA > 510 ? 255 : mA / 2;
usb_data.potpgt = (potpgt + 1) / 2;
return platform_device_register(&usb_dev);
return platform_device_register(&da8xx_usb20_dev);
}
#else
int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
{
return 0;
}
#endif /* CONFIG_USB_MUSB_HDRC */
static struct resource da8xx_usb11_resources[] = {
[0] = {
.start = DA8XX_USB1_BASE,
@ -90,8 +109,8 @@ static struct resource da8xx_usb11_resources[] = {
static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32);
static struct platform_device da8xx_usb11_device = {
.name = "ohci",
.id = 0,
.name = "ohci-da8xx",
.id = -1,
.dev = {
.dma_mask = &da8xx_usb11_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
@ -105,3 +124,236 @@ int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
da8xx_usb11_device.dev.platform_data = pdata;
return platform_device_register(&da8xx_usb11_device);
}
static struct clk usb_refclkin = {
.name = "usb_refclkin",
.set_rate = davinci_simple_set_rate,
};
static struct clk_lookup usb_refclkin_lookup =
CLK(NULL, "usb_refclkin", &usb_refclkin);
/**
* da8xx_register_usb_refclkin - register USB_REFCLKIN clock
*
* @rate: The clock rate in Hz
*
* This clock is only needed if the board provides an external USB_REFCLKIN
* signal, in which case it will be used as the parent of usb20_phy_clk and/or
* usb11_phy_clk.
*/
int __init da8xx_register_usb_refclkin(int rate)
{
int ret;
usb_refclkin.rate = rate;
ret = clk_register(&usb_refclkin);
if (ret)
return ret;
clkdev_add(&usb_refclkin_lookup);
return 0;
}
static void usb20_phy_clk_enable(struct clk *clk)
{
struct clk *usb20_clk;
int err;
u32 val;
u32 timeout = 500000; /* 500 msec */
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
if (IS_ERR(usb20_clk)) {
pr_err("could not get usb20 clk: %ld\n", PTR_ERR(usb20_clk));
return;
}
/* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
err = clk_prepare_enable(usb20_clk);
if (err) {
pr_err("failed to enable usb20 clk: %d\n", err);
clk_put(usb20_clk);
return;
}
/*
* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
* host may use the PLL clock without USB 2.0 OTG being used.
*/
val &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN);
val |= CFGCHIP2_PHY_PLLON;
writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
while (--timeout) {
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
if (val & CFGCHIP2_PHYCLKGD)
goto done;
udelay(1);
}
pr_err("Timeout waiting for USB 2.0 PHY clock good\n");
done:
clk_disable_unprepare(usb20_clk);
clk_put(usb20_clk);
}
static void usb20_phy_clk_disable(struct clk *clk)
{
u32 val;
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
val |= CFGCHIP2_PHYPWRDN;
writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
}
static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent)
{
u32 val;
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
/* Set the mux depending on the parent clock. */
if (parent == &usb_refclkin) {
val &= ~CFGCHIP2_USB2PHYCLKMUX;
} else if (strcmp(parent->name, "pll0_aux_clk") == 0) {
val |= CFGCHIP2_USB2PHYCLKMUX;
} else {
pr_err("Bad parent on USB 2.0 PHY clock\n");
return -EINVAL;
}
/* reference frequency also comes from parent clock */
val &= ~CFGCHIP2_REFFREQ_MASK;
switch (clk_get_rate(parent)) {
case 12000000:
val |= CFGCHIP2_REFFREQ_12MHZ;
break;
case 13000000:
val |= CFGCHIP2_REFFREQ_13MHZ;
break;
case 19200000:
val |= CFGCHIP2_REFFREQ_19_2MHZ;
break;
case 20000000:
val |= CFGCHIP2_REFFREQ_20MHZ;
break;
case 24000000:
val |= CFGCHIP2_REFFREQ_24MHZ;
break;
case 26000000:
val |= CFGCHIP2_REFFREQ_26MHZ;
break;
case 38400000:
val |= CFGCHIP2_REFFREQ_38_4MHZ;
break;
case 40000000:
val |= CFGCHIP2_REFFREQ_40MHZ;
break;
case 48000000:
val |= CFGCHIP2_REFFREQ_48MHZ;
break;
default:
pr_err("Bad parent clock rate on USB 2.0 PHY clock\n");
return -EINVAL;
}
writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
return 0;
}
static struct clk usb20_phy_clk = {
.name = "usb20_phy",
.clk_enable = usb20_phy_clk_enable,
.clk_disable = usb20_phy_clk_disable,
.set_parent = usb20_phy_clk_set_parent,
};
static struct clk_lookup usb20_phy_clk_lookup =
CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk);
/**
* da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock
*
* @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
* or "pll0_aux" if false.
*/
int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
{
struct clk *parent;
int ret = 0;
parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux");
if (IS_ERR(parent))
return PTR_ERR(parent);
usb20_phy_clk.parent = parent;
ret = clk_register(&usb20_phy_clk);
if (!ret)
clkdev_add(&usb20_phy_clk_lookup);
clk_put(parent);
return ret;
}
static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent)
{
u32 val;
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
/* Set the USB 1.1 PHY clock mux based on the parent clock. */
if (parent == &usb20_phy_clk) {
val &= ~CFGCHIP2_USB1PHYCLKMUX;
} else if (parent == &usb_refclkin) {
val |= CFGCHIP2_USB1PHYCLKMUX;
} else {
pr_err("Bad parent on USB 1.1 PHY clock\n");
return -EINVAL;
}
writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
return 0;
}
static struct clk usb11_phy_clk = {
.name = "usb11_phy",
.set_parent = usb11_phy_clk_set_parent,
};
static struct clk_lookup usb11_phy_clk_lookup =
CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk);
/**
* da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock
*
* @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
* or "usb20_phy" if false.
*/
int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
{
struct clk *parent;
int ret = 0;
if (use_usb_refclkin)
parent = clk_get(NULL, "usb_refclkin");
else
parent = clk_get(&da8xx_usb_phy.dev, "usb20_phy");
if (IS_ERR(parent))
return PTR_ERR(parent);
usb11_phy_clk.parent = parent;
ret = clk_register(&usb11_phy_clk);
if (!ret)
clkdev_add(&usb11_phy_clk_lookup);
clk_put(parent);
return ret;
}

1
arch/arm/mach-imx/Kconfig
View File

@ -557,7 +557,6 @@ config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
select PINCTRL_VF610
select PL310_ERRATA_769419 if CACHE_L2X0
help
This enables support for Freescale Vybrid VF610 processor.

1
arch/arm/mach-imx/mach-imx6ul.c
View File

@ -89,6 +89,7 @@ static void __init imx6ul_init_late(void)
static const char * const imx6ul_dt_compat[] __initconst = {
"fsl,imx6ul",
"fsl,imx6ull",
NULL,
};

495
arch/arm/mach-imx/mmdc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011,2016 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@ -10,12 +10,16 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/hrtimer.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/perf_event.h>
#include <linux/slab.h>
#include "common.h"
@ -27,8 +31,489 @@
#define BM_MMDC_MDMISC_DDR_TYPE 0x18
#define BP_MMDC_MDMISC_DDR_TYPE 0x3
#define TOTAL_CYCLES 0x0
#define BUSY_CYCLES 0x1
#define READ_ACCESSES 0x2
#define WRITE_ACCESSES 0x3
#define READ_BYTES 0x4
#define WRITE_BYTES 0x5
/* Enables, resets, freezes, overflow profiling*/
#define DBG_DIS 0x0
#define DBG_EN 0x1
#define DBG_RST 0x2
#define PRF_FRZ 0x4
#define CYC_OVF 0x8
#define PROFILE_SEL 0x10
#define MMDC_MADPCR0 0x410
#define MMDC_MADPSR0 0x418
#define MMDC_MADPSR1 0x41C
#define MMDC_MADPSR2 0x420
#define MMDC_MADPSR3 0x424
#define MMDC_MADPSR4 0x428
#define MMDC_MADPSR5 0x42C
#define MMDC_NUM_COUNTERS 6
#define MMDC_FLAG_PROFILE_SEL 0x1
#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
static int ddr_type;
struct fsl_mmdc_devtype_data {
unsigned int flags;
};
static const struct fsl_mmdc_devtype_data imx6q_data = {
};
static const struct fsl_mmdc_devtype_data imx6qp_data = {
.flags = MMDC_FLAG_PROFILE_SEL,
};
static const struct of_device_id imx_mmdc_dt_ids[] = {
{ .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
{ .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
{ /* sentinel */ }
};
#ifdef CONFIG_PERF_EVENTS
static DEFINE_IDA(mmdc_ida);
PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "config=0x03")
PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05")
PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB");
PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001");
struct mmdc_pmu {
struct pmu pmu;
void __iomem *mmdc_base;
cpumask_t cpu;
struct hrtimer hrtimer;
unsigned int active_events;
struct device *dev;
struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
struct hlist_node node;
struct fsl_mmdc_devtype_data *devtype_data;
};
/*
* Polling period is set to one second, overflow of total-cycles (the fastest
* increasing counter) takes ten seconds so one second is safe
*/
static unsigned int mmdc_pmu_poll_period_us = 1000000;
module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint,
S_IRUGO | S_IWUSR);
static ktime_t mmdc_pmu_timer_period(void)
{
return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000);
}
static ssize_t mmdc_pmu_cpumask_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev);
return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu);
}
static struct device_attribute mmdc_pmu_cpumask_attr =
__ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL);
static struct attribute *mmdc_pmu_cpumask_attrs[] = {
&mmdc_pmu_cpumask_attr.attr,
NULL,
};
static struct attribute_group mmdc_pmu_cpumask_attr_group = {
.attrs = mmdc_pmu_cpumask_attrs,
};
static struct attribute *mmdc_pmu_events_attrs[] = {
&mmdc_pmu_total_cycles.attr.attr,
&mmdc_pmu_busy_cycles.attr.attr,
&mmdc_pmu_read_accesses.attr.attr,
&mmdc_pmu_write_accesses.attr.attr,
&mmdc_pmu_read_bytes.attr.attr,
&mmdc_pmu_read_bytes_unit.attr.attr,
&mmdc_pmu_read_bytes_scale.attr.attr,
&mmdc_pmu_write_bytes.attr.attr,
&mmdc_pmu_write_bytes_unit.attr.attr,
&mmdc_pmu_write_bytes_scale.attr.attr,
NULL,
};
static struct attribute_group mmdc_pmu_events_attr_group = {
.name = "events",
.attrs = mmdc_pmu_events_attrs,
};
PMU_FORMAT_ATTR(event, "config:0-63");
static struct attribute *mmdc_pmu_format_attrs[] = {
&format_attr_event.attr,
NULL,
};
static struct attribute_group mmdc_pmu_format_attr_group = {
.name = "format",
.attrs = mmdc_pmu_format_attrs,
};
static const struct attribute_group *attr_groups[] = {
&mmdc_pmu_events_attr_group,
&mmdc_pmu_format_attr_group,
&mmdc_pmu_cpumask_attr_group,
NULL,
};
static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg)
{
void __iomem *mmdc_base, *reg;
mmdc_base = pmu_mmdc->mmdc_base;
switch (cfg) {
case TOTAL_CYCLES:
reg = mmdc_base + MMDC_MADPSR0;
break;
case BUSY_CYCLES:
reg = mmdc_base + MMDC_MADPSR1;
break;
case READ_ACCESSES:
reg = mmdc_base + MMDC_MADPSR2;
break;
case WRITE_ACCESSES:
reg = mmdc_base + MMDC_MADPSR3;
break;
case READ_BYTES:
reg = mmdc_base + MMDC_MADPSR4;
break;
case WRITE_BYTES:
reg = mmdc_base + MMDC_MADPSR5;
break;
default:
return WARN_ONCE(1,
"invalid configuration %d for mmdc counter", cfg);
}
return readl(reg);
}
static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
{
struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node);
int target;
if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu))
return 0;
target = cpumask_any_but(cpu_online_mask, cpu);
if (target >= nr_cpu_ids)
return 0;
perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target);
cpumask_set_cpu(target, &pmu_mmdc->cpu);
return 0;
}
static bool mmdc_pmu_group_event_is_valid(struct perf_event *event,
struct pmu *pmu,
unsigned long *used_counters)
{
int cfg = event->attr.config;
if (is_software_event(event))
return true;
if (event->pmu != pmu)
return false;
return !test_and_set_bit(cfg, used_counters);
}
/*
* Each event has a single fixed-purpose counter, so we can only have a
* single active event for each at any point in time. Here we just check
* for duplicates, and rely on mmdc_pmu_event_init to verify that the HW
* event numbers are valid.
*/
static bool mmdc_pmu_group_is_valid(struct perf_event *event)
{
struct pmu *pmu = event->pmu;
struct perf_event *leader = event->group_leader;
struct perf_event *sibling;
unsigned long counter_mask = 0;
set_bit(leader->attr.config, &counter_mask);
if (event != leader) {
if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask))
return false;
}
list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))
return false;
}
return true;
}
static int mmdc_pmu_event_init(struct perf_event *event)
{
struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
int cfg = event->attr.config;
if (event->attr.type != event->pmu->type)
return -ENOENT;
if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
return -EOPNOTSUPP;
if (event->cpu < 0) {
dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n");
return -EOPNOTSUPP;
}
if (event->attr.exclude_user ||
event->attr.exclude_kernel ||
event->attr.exclude_hv ||
event->attr.exclude_idle ||
event->attr.exclude_host ||
event->attr.exclude_guest ||
event->attr.sample_period)
return -EINVAL;
if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS)
return -EINVAL;
if (!mmdc_pmu_group_is_valid(event))
return -EINVAL;
event->cpu = cpumask_first(&pmu_mmdc->cpu);
return 0;
}
static void mmdc_pmu_event_update(struct perf_event *event)
{
struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw;
u64 delta, prev_raw_count, new_raw_count;
do {
prev_raw_count = local64_read(&hwc->prev_count);
new_raw_count = mmdc_pmu_read_counter(pmu_mmdc,
event->attr.config);
} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
new_raw_count) != prev_raw_count);
delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
local64_add(delta, &event->count);
}
static void mmdc_pmu_event_start(struct perf_event *event, int flags)
{
struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw;
void __iomem *mmdc_base, *reg;
u32 val;
mmdc_base = pmu_mmdc->mmdc_base;
reg = mmdc_base + MMDC_MADPCR0;
/*
* hrtimer is required because mmdc does not provide an interrupt so
* polling is necessary
*/
hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(),
HRTIMER_MODE_REL_PINNED);
local64_set(&hwc->prev_count, 0);
writel(DBG_RST, reg);
val = DBG_EN;
if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)
val |= PROFILE_SEL;
writel(val, reg);
}
static int mmdc_pmu_event_add(struct perf_event *event, int flags)
{
struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw;
int cfg = event->attr.config;
if (flags & PERF_EF_START)
mmdc_pmu_event_start(event, flags);
if (pmu_mmdc->mmdc_events[cfg] != NULL)
return -EAGAIN;
pmu_mmdc->mmdc_events[cfg] = event;
pmu_mmdc->active_events++;
local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg));
return 0;
}
static void mmdc_pmu_event_stop(struct perf_event *event, int flags)
{
struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
void __iomem *mmdc_base, *reg;
mmdc_base = pmu_mmdc->mmdc_base;
reg = mmdc_base + MMDC_MADPCR0;
writel(PRF_FRZ, reg);
mmdc_pmu_event_update(event);
}
static void mmdc_pmu_event_del(struct perf_event *event, int flags)
{
struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
int cfg = event->attr.config;
pmu_mmdc->mmdc_events[cfg] = NULL;
pmu_mmdc->active_events--;
if (pmu_mmdc->active_events == 0)
hrtimer_cancel(&pmu_mmdc->hrtimer);
mmdc_pmu_event_stop(event, PERF_EF_UPDATE);
}
static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc)
{
int i;
for (i = 0; i < MMDC_NUM_COUNTERS; i++) {
struct perf_event *event = pmu_mmdc->mmdc_events[i];
if (event)
mmdc_pmu_event_update(event);
}
}
static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
{
struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu,
hrtimer);
mmdc_pmu_overflow_handler(pmu_mmdc);
hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period());
return HRTIMER_RESTART;
}
static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
void __iomem *mmdc_base, struct device *dev)
{
int mmdc_num;
*pmu_mmdc = (struct mmdc_pmu) {
.pmu = (struct pmu) {
.task_ctx_nr = perf_invalid_context,
.attr_groups = attr_groups,
.event_init = mmdc_pmu_event_init,
.add = mmdc_pmu_event_add,
.del = mmdc_pmu_event_del,
.start = mmdc_pmu_event_start,
.stop = mmdc_pmu_event_stop,
.read = mmdc_pmu_event_update,
},
.mmdc_base = mmdc_base,
.dev = dev,
.active_events = 0,
};
mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
return mmdc_num;
}
static int imx_mmdc_remove(struct platform_device *pdev)
{
struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
perf_pmu_unregister(&pmu_mmdc->pmu);
cpuhp_remove_state_nocalls(CPUHP_ONLINE);
kfree(pmu_mmdc);
return 0;
}
static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base)
{
struct mmdc_pmu *pmu_mmdc;
char *name;
int mmdc_num;
int ret;
const struct of_device_id *of_id =
of_match_device(imx_mmdc_dt_ids, &pdev->dev);
pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL);
if (!pmu_mmdc) {
pr_err("failed to allocate PMU device!\n");
return -ENOMEM;
}
mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
if (mmdc_num == 0)
name = "mmdc";
else
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", mmdc_num);
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler;
cpuhp_state_add_instance_nocalls(CPUHP_ONLINE,
&pmu_mmdc->node);
cpumask_set_cpu(smp_processor_id(), &pmu_mmdc->cpu);
ret = cpuhp_setup_state_multi(CPUHP_AP_NOTIFY_ONLINE,
"MMDC_ONLINE", NULL,
mmdc_pmu_offline_cpu);
if (ret) {
pr_err("cpuhp_setup_state_multi failure\n");
goto pmu_register_err;
}
ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1);
platform_set_drvdata(pdev, pmu_mmdc);
if (ret)
goto pmu_register_err;
return 0;
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
hrtimer_cancel(&pmu_mmdc->hrtimer);
kfree(pmu_mmdc);
return ret;
}
#else
#define imx_mmdc_remove NULL
#define imx_mmdc_perf_init(pdev, mmdc_base) 0
#endif
static int imx_mmdc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@ -62,7 +547,7 @@ static int imx_mmdc_probe(struct platform_device *pdev)
return -EBUSY;
}
return 0;
return imx_mmdc_perf_init(pdev, mmdc_base);
}
int imx_mmdc_get_ddr_type(void)
@ -70,17 +555,13 @@ int imx_mmdc_get_ddr_type(void)
return ddr_type;
}
static const struct of_device_id imx_mmdc_dt_ids[] = {
{ .compatible = "fsl,imx6q-mmdc", },
{ /* sentinel */ }
};
static struct platform_driver imx_mmdc_driver = {
.driver = {
.name = "imx-mmdc",
.of_match_table = imx_mmdc_dt_ids,
},
.probe = imx_mmdc_probe,
.remove = imx_mmdc_remove,
};
static int __init imx_mmdc_init(void)

54
arch/arm/mach-integrator/integrator_ap.c
View File

@ -27,6 +27,8 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/termios.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -37,11 +39,8 @@
#include "pci_v3.h"
#include "lm.h"
/* Base address to the AP system controller */
void __iomem *ap_syscon_base;
/* Base address to the external bus interface */
static void __iomem *ebi_base;
/* Regmap to the AP system controller */
static struct regmap *ap_syscon_map;
/*
* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
@ -125,6 +124,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev,
{
unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
u32 phybase = dev->res.start;
int ret;
if (phybase == INTEGRATOR_UART0_BASE) {
/* UART0 */
@ -146,8 +146,17 @@ static void integrator_uart_set_mctrl(struct amba_device *dev,
else
ctrls |= dtr_mask;
__raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
__raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
ret = regmap_write(ap_syscon_map,
INTEGRATOR_SC_CTRLS_OFFSET,
ctrls);
if (ret)
pr_err("MODEM: unable to write PL010 UART CTRLS\n");
ret = regmap_write(ap_syscon_map,
INTEGRATOR_SC_CTRLC_OFFSET,
ctrlc);
if (ret)
pr_err("MODEM: unable to write PL010 UART CRTLC\n");
}
struct amba_pl010_data ap_uart_data = {
@ -178,35 +187,32 @@ static const struct of_device_id ap_syscon_match[] = {
{ },
};
static const struct of_device_id ebi_match[] = {
{ .compatible = "arm,external-bus-interface"},
{ },
};
static void __init ap_init_of(void)
{
unsigned long sc_dec;
u32 sc_dec;
struct device_node *syscon;
struct device_node *ebi;
int ret;
int i;
of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
syscon = of_find_matching_node(NULL, ap_syscon_match);
if (!syscon)
return;
ebi = of_find_matching_node(NULL, ebi_match);
if (!ebi)
ap_syscon_map = syscon_node_to_regmap(syscon);
if (IS_ERR(ap_syscon_map)) {
pr_crit("could not find Integrator/AP system controller\n");
return;
}
ap_syscon_base = of_iomap(syscon, 0);
if (!ap_syscon_base)
return;
ebi_base = of_iomap(ebi, 0);
if (!ebi_base)
ret = regmap_read(ap_syscon_map,
INTEGRATOR_SC_DEC_OFFSET,
&sc_dec);
if (ret) {
pr_crit("could not read from Integrator/AP syscon\n");
return;
}
of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
for (i = 0; i < 4; i++) {
struct lm_device *lmdev;

38
arch/arm/mach-lpc32xx/clock.h
View File

@ -1,38 +0,0 @@
/*
* arch/arm/mach-lpc32xx/clock.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LPC32XX_CLOCK_H
#define __LPC32XX_CLOCK_H
struct clk {
struct list_head node;
struct clk *parent;
u32 rate;
u32 usecount;
int (*set_rate) (struct clk *, unsigned long);
unsigned long (*round_rate) (struct clk *, unsigned long);
unsigned long (*get_rate) (struct clk *clk);
int (*enable) (struct clk *, int);
/* Register address and bit mask for simple clocks */
void __iomem *enable_reg;
u32 enable_mask;
};
#endif

1
arch/arm/mach-lpc32xx/common.h
View File

@ -24,7 +24,6 @@
/*
* Other arch specific structures and functions
*/
extern void __init lpc32xx_init_irq(void);
extern void __init lpc32xx_map_io(void);
extern void __init lpc32xx_serial_init(void);

117
arch/arm/mach-lpc32xx/include/mach/irqs.h
View File

@ -1,117 +0,0 @@
/*
* arch/arm/mach-lpc32xx/include/mach/irqs.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARM_ARCH_IRQS_H
#define __ASM_ARM_ARCH_IRQS_H
#define LPC32XX_SIC1_IRQ(n) (32 + (n))
#define LPC32XX_SIC2_IRQ(n) (64 + (n))
/*
* MIC interrupts
*/
#define IRQ_LPC32XX_SUB1IRQ 0
#define IRQ_LPC32XX_SUB2IRQ 1
#define IRQ_LPC32XX_PWM3 3
#define IRQ_LPC32XX_PWM4 4
#define IRQ_LPC32XX_HSTIMER 5
#define IRQ_LPC32XX_WATCH 6
#define IRQ_LPC32XX_UART_IIR3 7
#define IRQ_LPC32XX_UART_IIR4 8
#define IRQ_LPC32XX_UART_IIR5 9
#define IRQ_LPC32XX_UART_IIR6 10
#define IRQ_LPC32XX_FLASH 11
#define IRQ_LPC32XX_SD1 13
#define IRQ_LPC32XX_LCD 14
#define IRQ_LPC32XX_SD0 15
#define IRQ_LPC32XX_TIMER0 16
#define IRQ_LPC32XX_TIMER1 17
#define IRQ_LPC32XX_TIMER2 18
#define IRQ_LPC32XX_TIMER3 19
#define IRQ_LPC32XX_SSP0 20
#define IRQ_LPC32XX_SSP1 21
#define IRQ_LPC32XX_I2S0 22
#define IRQ_LPC32XX_I2S1 23
#define IRQ_LPC32XX_UART_IIR7 24
#define IRQ_LPC32XX_UART_IIR2 25
#define IRQ_LPC32XX_UART_IIR1 26
#define IRQ_LPC32XX_MSTIMER 27
#define IRQ_LPC32XX_DMA 28
#define IRQ_LPC32XX_ETHERNET 29
#define IRQ_LPC32XX_SUB1FIQ 30
#define IRQ_LPC32XX_SUB2FIQ 31
/*
* SIC1 interrupts start at offset 32
*/
#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12)
#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13)
#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14)
#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17)
#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18)
#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19)
#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20)
#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22)
#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23)
#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24)
#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25)
#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26)
#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27)
#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28)
#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29)
#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30)
#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31)
/*
* SIC2 interrupts start at offset 64
*/
#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0)
#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1)
#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2)
#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3)
#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4)
#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5)
#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6)
#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7)
#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8)
#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9)
#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10)
#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11)
#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12)
#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15)
#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18)
#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19)
#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20)
#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22)
#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23)
#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24)
#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25)
#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26)
#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27)
#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)
#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31)
#define LPC32XX_NR_IRQS 96
#endif

1
arch/arm/mach-lpc32xx/pm.c
View File

@ -73,7 +73,6 @@
#include <mach/hardware.h>
#include <mach/platform.h>
#include "common.h"
#include "clock.h"
#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)

6
arch/arm/mach-mediatek/Makefile
View File

@ -1,4 +1,2 @@
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
endif
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
obj-$(CONFIG_SMP) += platsmp.o
obj-y += mediatek.o

26
arch/arm/mach-omap1/Kconfig
View File

@ -31,6 +31,32 @@ config ARCH_OMAP16XX
select ARCH_OMAP_OTG
select CPU_ARM926T
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
sets the multiplexing correctly, say N. Otherwise, or if unsure,
say Y.
config OMAP_MUX_DEBUG
bool "Multiplexing debug output"
depends on OMAP_MUX
help
Makes the multiplexing functions print out a lot of debug info.
This is useful if you want to find out the correct values of the
multiplexing registers.
config OMAP_MUX_WARNINGS
bool "Warn about pins the bootloader didn't set up"
depends on OMAP_MUX
default y
help
Choose Y here to warn whenever driver initialization logic needs
to change the pin multiplexing setup. When there are no warnings
printed, it's safe to deselect OMAP_MUX for your product.
comment "OMAP Board Type"
depends on ARCH_OMAP1

83
arch/arm/mach-omap1/i2c.c
View File

@ -19,6 +19,7 @@
*
*/
#include <linux/i2c.h>
#include <linux/i2c-omap.h>
#include <mach/mux.h>
#include "soc.h"
@ -91,6 +92,88 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
return platform_device_register(pdev);
}
#define OMAP_I2C_MAX_CONTROLLERS 4
static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
/**
* omap_i2c_bus_setup - Process command line options for the I2C bus speed
* @str: String of options
*
* This function allow to override the default I2C bus speed for given I2C
* bus with a command line option.
*
* Format: i2c_bus=bus_id,clkrate (in kHz)
*
* Returns 1 on success, 0 otherwise.
*/
static int __init omap_i2c_bus_setup(char *str)
{
int ints[3];
get_options(str, 3, ints);
if (ints[0] < 2 || ints[1] < 1 ||
ints[1] > OMAP_I2C_MAX_CONTROLLERS)
return 0;
i2c_pdata[ints[1] - 1].clkrate = ints[2];
i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
return 1;
}
__setup("i2c_bus=", omap_i2c_bus_setup);
/*
* Register busses defined in command line but that are not registered with
* omap_register_i2c_bus from board initialization code.
*/
int __init omap_register_i2c_bus_cmdline(void)
{
int i, err = 0;
for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
if (err)
goto out;
}
out:
return err;
}
/**
* omap_register_i2c_bus - register I2C bus with device descriptors
* @bus_id: bus id counting from number 1
* @clkrate: clock rate of the bus in kHz
* @info: pointer into I2C device descriptor table or NULL
* @len: number of descriptors in the table
*
* Returns 0 on success or an error code.
*/
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
int err;
BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
if (info) {
err = i2c_register_board_info(bus_id, info, len);
if (err)
return err;
}
if (!i2c_pdata[bus_id - 1].clkrate)
i2c_pdata[bus_id - 1].clkrate = clkrate;
i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
}
static int __init omap_i2c_cmdline(void)
{
return omap_register_i2c_bus_cmdline();

18
arch/arm/mach-omap2/Makefile
View File

@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-omap/include
# Common support
obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \
obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o omap-headsmp.o sram.o drm.o
@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# Pin multiplexing
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
@ -80,7 +77,7 @@ endif
# Power Management
omap-4-5-pm-common = omap-mpuss-lowpower.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
ifeq ($(CONFIG_PM),y)
@ -235,26 +232,15 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
# Platform specific device init code
omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o
omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o
obj-y += $(omap-flash-y) $(omap-flash-m)
omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
obj-y += usb-musb.o
obj-y += omap_phy_internal.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
obj-y += usb-host.o
onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
obj-y += $(onenand-m) $(onenand-y)
nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
obj-y += $(nand-m) $(nand-y)
smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
obj-y += $(smsc911x-m) $(smsc911x-y)
obj-y += common-board-devices.o twl-common.o dss-common.o

242
arch/arm/mach-omap2/board-flash.c
View File

@ -1,242 +0,0 @@
/*
* board-flash.c
* Modified from mach-omap2/board-3430sdp-flash.c
*
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2009 Texas Instruments
*
* Vimal Singh <vimalsingh@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include "soc.h"
#include "common.h"
#include "board-flash.h"
#define REG_FPGA_REV 0x10
#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
#define MAX_SUPPORTED_GPMC_CONFIG 3
#define DEBUG_BASE 0x08000000 /* debug board */
/* various memory sizes */
#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
static struct physmap_flash_data board_nor_data = {
.width = 2,
};
static struct resource board_nor_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device board_nor_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &board_nor_data,
},
.num_resources = 1,
.resource = &board_nor_resource,
};
static void
__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
{
int err;
board_nor_data.parts = nor_parts;
board_nor_data.nr_parts = nr_parts;
/* Configure start address and size of NOR device */
if (omap_rev() >= OMAP3430_REV_ES1_0) {
err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
(unsigned long *)&board_nor_resource.start);
board_nor_resource.end = board_nor_resource.start
+ FLASH_SIZE_SDPV2 - 1;
} else {
err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
(unsigned long *)&board_nor_resource.start);
board_nor_resource.end = board_nor_resource.start
+ FLASH_SIZE_SDPV1 - 1;
}
if (err < 0) {
pr_err("NOR: Can't request GPMC CS\n");
return;
}
if (platform_device_register(&board_nor_device) < 0)
pr_err("Unable to register NOR device\n");
}
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
static struct omap_onenand_platform_data board_onenand_data = {
.dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
};
void
__init board_onenand_init(struct mtd_partition *onenand_parts,
u8 nr_parts, u8 cs)
{
board_onenand_data.cs = cs;
board_onenand_data.parts = onenand_parts;
board_onenand_data.nr_parts = nr_parts;
gpmc_onenand_init(&board_onenand_data);
}
#endif /* IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) */
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
/* Note that all values in this struct are in nanoseconds */
struct gpmc_timings nand_default_timings[1] = {
{
.sync_clk = 0,
.cs_on = 0,
.cs_rd_off = 36,
.cs_wr_off = 36,
.we_on = 6,
.oe_on = 6,
.adv_on = 6,
.adv_rd_off = 24,
.adv_wr_off = 36,
.we_off = 30,
.oe_off = 48,
.access = 54,
.rd_cycle = 72,
.wr_cycle = 72,
.wr_access = 30,
.wr_data_mux_bus = 0,
},
};
static struct omap_nand_platform_data board_nand_data;
void
__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
int nand_type, struct gpmc_timings *gpmc_t)
{
board_nand_data.cs = cs;
board_nand_data.parts = nand_parts;
board_nand_data.nr_parts = nr_parts;
board_nand_data.devsize = nand_type;
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
gpmc_nand_init(&board_nand_data, gpmc_t);
}
#endif /* IS_ENABLED(CONFIG_MTD_NAND_OMAP2) */
/**
* get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
* the various cs values.
*/
static u8 get_gpmc0_type(void)
{
u8 cs = 0;
void __iomem *fpga_map_addr;
fpga_map_addr = ioremap(DEBUG_BASE, 4096);
if (!fpga_map_addr)
return -ENOMEM;
if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
/* we dont have an DEBUG FPGA??? */
/* Depend on #defines!! default to strata boot return param */
goto unmap;
/* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
/* ES2.0 SDP's onwards 4 dip switches are provided for CS */
if (omap_rev() >= OMAP3430_REV_ES1_0)
/* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
((cs & 2) << 1) | ((cs & 1) << 3);
else
/* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
unmap:
iounmap(fpga_map_addr);
return cs;
}
/**
* board_flash_init - Identify devices connected to GPMC and register.
*
* @return - void.
*/
void __init board_flash_init(struct flash_partitions partition_info[],
char chip_sel_board[][GPMC_CS_NUM], int nand_type)
{
u8 cs = 0;
u8 norcs = GPMC_CS_NUM + 1;
u8 nandcs = GPMC_CS_NUM + 1;
u8 onenandcs = GPMC_CS_NUM + 1;
u8 idx;
unsigned char *config_sel = NULL;
/* REVISIT: Is this return correct idx for 2430 SDP?
* for which cs configuration matches for 2430 SDP?
*/
idx = get_gpmc0_type();
if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
pr_err("%s: Invalid chip select: %d\n", __func__, cs);
return;
}
config_sel = (unsigned char *)(chip_sel_board[idx]);
while (cs < GPMC_CS_NUM) {
switch (config_sel[cs]) {
case PDC_NOR:
if (norcs > GPMC_CS_NUM)
norcs = cs;
break;
case PDC_NAND:
if (nandcs > GPMC_CS_NUM)
nandcs = cs;
break;
case PDC_ONENAND:
if (onenandcs > GPMC_CS_NUM)
onenandcs = cs;
break;
}
cs++;
}
if (norcs > GPMC_CS_NUM)
pr_err("NOR: Unable to find configuration in GPMC\n");
else
board_nor_init(partition_info[0].parts,
partition_info[0].nr_parts, norcs);
if (onenandcs > GPMC_CS_NUM)
pr_err("OneNAND: Unable to find configuration in GPMC\n");
else
board_onenand_init(partition_info[1].parts,
partition_info[1].nr_parts, onenandcs);
if (nandcs > GPMC_CS_NUM)
pr_err("NAND: Unable to find configuration in GPMC\n");
else
board_nand_init(partition_info[2].parts,
partition_info[2].nr_parts, nandcs,
nand_type, nand_default_timings);
}

56
arch/arm/mach-omap2/board-flash.h
View File

@ -1,56 +0,0 @@
/*
* board-sdp.h
*
* Information structures for SDP-specific board config data
*
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#define PDC_NOR 1
#define PDC_NAND 2
#define PDC_ONENAND 3
#define DBG_MPDB 4
struct flash_partitions {
struct mtd_partition *parts;
int nr_parts;
};
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) || IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void board_flash_init(struct flash_partitions [],
char chip_sel[][GPMC_CS_NUM], int nand_type);
#else
static inline void board_flash_init(struct flash_partitions part[],
char chip_sel[][GPMC_CS_NUM], int nand_type)
{
}
#endif
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
extern void board_nand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
extern struct gpmc_timings nand_default_timings[];
#else
static inline void board_nand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
{
}
#define nand_default_timings NULL
#endif
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
extern void board_onenand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs);
#else
static inline void board_onenand_init(struct mtd_partition *nand_parts,
u8 nr_parts, u8 cs)
{
}
#endif

1
arch/arm/mach-omap2/board-generic.c
View File

@ -339,6 +339,7 @@ static const char *const dra72x_boards_compat[] __initconst = {
"ti,am5718",
"ti,am5716",
"ti,dra722",
"ti,dra718",
NULL,
};

2
arch/arm/mach-omap2/clockdomains7xx_data.c
View File

@ -409,7 +409,7 @@ static struct clockdomain l4sec_7xx_clkdm = {
.dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4sec_wkup_sleep_deps,
.sleepdep_srcs = l4sec_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l3main1_7xx_clkdm = {

102
arch/arm/mach-omap2/common-board-devices.c
View File

@ -1,102 +0,0 @@
/*
* common-board-devices.c
*
* Copyright (C) 2011 CompuLab, Ltd.
* Author: Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "common.h"
#include "common-board-devices.h"
#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
.turbo_mode = 0,
};
static struct ads7846_platform_data ads7846_config = {
.x_max = 0x0fff,
.y_max = 0x0fff,
.x_plate_ohms = 180,
.pressure_max = 255,
.debounce_max = 10,
.debounce_tol = 3,
.debounce_rep = 1,
.gpio_pendown = -EINVAL,
.keep_vref_on = 1,
};
static struct spi_board_info ads7846_spi_board_info __initdata = {
.modalias = "ads7846",
.bus_num = -EINVAL,
.chip_select = 0,
.max_speed_hz = 1500000,
.controller_data = &ads7846_mcspi_config,
.irq = -EINVAL,
.platform_data = &ads7846_config,
};
void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata)
{
struct spi_board_info *spi_bi = &ads7846_spi_board_info;
int err;
/*
* If a board defines get_pendown_state() function, request the pendown
* GPIO and set the GPIO debounce time.
* If a board does not define the get_pendown_state() function, then
* the ads7846 driver will setup the pendown GPIO itself.
*/
if (board_pdata && board_pdata->get_pendown_state) {
err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
if (err) {
pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
return;
}
if (gpio_debounce)
gpio_set_debounce(gpio_pendown, gpio_debounce);
gpio_export(gpio_pendown, 0);
}
spi_bi->bus_num = bus_num;
spi_bi->irq = gpio_to_irq(gpio_pendown);
ads7846_config.gpio_pendown = gpio_pendown;
if (board_pdata) {
board_pdata->gpio_pendown = gpio_pendown;
board_pdata->gpio_pendown_debounce = gpio_debounce;
spi_bi->platform_data = board_pdata;
}
spi_register_board_info(&ads7846_spi_board_info, 1);
}
#else
void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata)
{
}
#endif

8
arch/arm/mach-omap2/common-board-devices.h
View File

@ -3,15 +3,7 @@
#include <sound/tlv320aic3x.h>
#include <linux/mfd/menelaus.h>
#include "twl-common.h"
#define NAND_BLOCK_SIZE SZ_128K
struct mtd_partition;
struct ads7846_platform_data;
void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct ads7846_platform_data *board_pdata);
void *n8x0_legacy_init(void);
extern struct menelaus_platform_data n8x0_menelaus_platform_data;

47
arch/arm/mach-omap2/common.h
View File

@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void)
}
#endif
#ifdef CONFIG_OMAP_MUX
int omap_mux_late_init(void);
#else
static inline int omap_mux_late_init(void)
{
return 0;
}
#endif
extern void omap2_init_common_infrastructure(void);
extern void omap_init_time(void);
@ -262,8 +253,6 @@ extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap4_mpuss_early_init(void);
extern void omap_do_wfi(void);
extern void omap4_secondary_startup(void);
extern void omap4460_secondary_startup(void);
#ifdef CONFIG_SMP
/* Needed for secondary core boot */
@ -275,16 +264,11 @@ extern void omap4_cpu_die(unsigned int cpu);
extern int omap4_cpu_kill(unsigned int cpu);
extern const struct smp_operations omap4_smp_ops;
extern void omap5_secondary_startup(void);
extern void omap5_secondary_hyp_startup(void);
#endif
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
extern int omap4_mpuss_init(void);
extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
extern int omap4_finish_suspend(unsigned long cpu_state);
extern void omap4_cpu_resume(void);
extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
#else
static inline int omap4_enter_lowpower(unsigned int cpu,
@ -305,14 +289,41 @@ static inline int omap4_mpuss_init(void)
return 0;
}
#endif
#ifdef CONFIG_ARCH_OMAP4
void omap4_secondary_startup(void);
void omap4460_secondary_startup(void);
int omap4_finish_suspend(unsigned long cpu_state);
void omap4_cpu_resume(void);
#else
static inline void omap4_secondary_startup(void)
{
}
static inline void omap4460_secondary_startup(void)
{
}
static inline int omap4_finish_suspend(unsigned long cpu_state)
{
return 0;
}
static inline void omap4_cpu_resume(void)
{}
{
}
#endif
#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
void omap5_secondary_startup(void);
void omap5_secondary_hyp_startup(void);
#else
static inline void omap5_secondary_startup(void)
{
}
static inline void omap5_secondary_hyp_startup(void)
{
}
#endif
void pdata_quirks_init(const struct of_device_id *);

80
arch/arm/mach-omap2/cpuidle44xx.c
View File

@ -21,6 +21,7 @@
#include "common.h"
#include "pm.h"
#include "prm.h"
#include "soc.h"
#include "clockdomain.h"
#define MAX_CPUS 2
@ -30,6 +31,7 @@ struct idle_statedata {
u32 cpu_state;
u32 mpu_logic_state;
u32 mpu_state;
u32 mpu_state_vote;
};
static struct idle_statedata omap4_idle_data[] = {
@ -50,12 +52,26 @@ static struct idle_statedata omap4_idle_data[] = {
},
};
static struct idle_statedata omap5_idle_data[] = {
{
.cpu_state = PWRDM_POWER_ON,
.mpu_state = PWRDM_POWER_ON,
.mpu_logic_state = PWRDM_POWER_ON,
},
{
.cpu_state = PWRDM_POWER_RET,
.mpu_state = PWRDM_POWER_RET,
.mpu_logic_state = PWRDM_POWER_RET,
},
};
static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
static struct clockdomain *cpu_clkdm[MAX_CPUS];
static atomic_t abort_barrier;
static bool cpu_done[MAX_CPUS];
static struct idle_statedata *state_ptr = &omap4_idle_data[0];
static DEFINE_RAW_SPINLOCK(mpu_lock);
/* Private functions */
@ -77,6 +93,32 @@ static int omap_enter_idle_simple(struct cpuidle_device *dev,
return index;
}
static int omap_enter_idle_smp(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
struct idle_statedata *cx = state_ptr + index;
unsigned long flag;
raw_spin_lock_irqsave(&mpu_lock, flag);
cx->mpu_state_vote++;
if (cx->mpu_state_vote == num_online_cpus()) {
pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
}
raw_spin_unlock_irqrestore(&mpu_lock, flag);
omap4_enter_lowpower(dev->cpu, cx->cpu_state);
raw_spin_lock_irqsave(&mpu_lock, flag);
if (cx->mpu_state_vote == num_online_cpus())
omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
cx->mpu_state_vote--;
raw_spin_unlock_irqrestore(&mpu_lock, flag);
return index;
}
static int omap_enter_idle_coupled(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@ -220,6 +262,32 @@ static struct cpuidle_driver omap4_idle_driver = {
.safe_state_index = 0,
};
static struct cpuidle_driver omap5_idle_driver = {
.name = "omap5_idle",
.owner = THIS_MODULE,
.states = {
{
/* C1 - CPU0 ON + CPU1 ON + MPU ON */
.exit_latency = 2 + 2,
.target_residency = 5,
.enter = omap_enter_idle_simple,
.name = "C1",
.desc = "CPUx WFI, MPUSS ON"
},
{
/* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
.exit_latency = 48 + 60,
.target_residency = 100,
.flags = CPUIDLE_FLAG_TIMER_STOP,
.enter = omap_enter_idle_smp,
.name = "C2",
.desc = "CPUx CSWR, MPUSS CSWR",
},
},
.state_count = ARRAY_SIZE(omap5_idle_data),
.safe_state_index = 0,
};
/* Public functions */
/**
@ -230,6 +298,16 @@ static struct cpuidle_driver omap4_idle_driver = {
*/
int __init omap4_idle_init(void)
{
struct cpuidle_driver *idle_driver;
if (soc_is_omap54xx()) {
state_ptr = &omap5_idle_data[0];
idle_driver = &omap5_idle_driver;
} else {
state_ptr = &omap4_idle_data[0];
idle_driver = &omap4_idle_driver;
}
mpu_pd = pwrdm_lookup("mpu_pwrdm");
cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
@ -244,5 +322,5 @@ int __init omap4_idle_init(void)
/* Configure the broadcast timer on each cpu */
on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
return cpuidle_register(idle_driver, cpu_online_mask);
}

1
arch/arm/mach-omap2/devices.c
View File

@ -30,7 +30,6 @@
#include "soc.h"
#include "common.h"
#include "mux.h"
#include "control.h"
#include "display.h"

37
arch/arm/mach-omap2/dss-common.c
View File

@ -1,37 +0,0 @@
/*
* Copyright (C) 2012 Texas Instruments, Inc..
* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
/*
* NOTE: this is a transitional file to help with DT adaptation.
* This file will be removed when DSS supports DT.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/platform_data/omapdss.h>
#include <video/omap-panel-data.h>
#include "soc.h"
#include "dss-common.h"
#include "mux.h"
#include "display.h"

13
arch/arm/mach-omap2/dss-common.h
View File

@ -1,13 +0,0 @@
#ifndef __OMAP_DSS_COMMON__
#define __OMAP_DSS_COMMON__
/*
* NOTE: this is a transitional file to help with DT adaptation.
* This file will be removed when DSS supports DT.
*/
void __init omap4_panda_display_init_of(void);
void __init omap_4430sdp_display_init_of(void);
void __init omap3_igep2_display_init_of(void);
#endif

100
arch/arm/mach-omap2/gpmc-smsc911x.c
View File

@ -1,100 +0,0 @@
/*
* linux/arch/arm/mach-omap2/gpmc-smsc911x.c
*
* Copyright (C) 2009 Li-Pro.Net
* Stephan Linz <linz@li-pro.net>
*
* Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include "gpmc.h"
#include "gpmc-smsc911x.h"
static struct resource gpmc_smsc911x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
static struct smsc911x_platform_config gpmc_smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
};
/*
* Initialize smsc911x device connected to the GPMC. Note that we
* assume that pin multiplexing is done in the board-*.c file,
* or in the bootloader.
*/
void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
{
struct platform_device *pdev;
unsigned long cs_mem_base;
int ret;
if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
pr_err("Failed to request GPMC mem region\n");
return;
}
gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "smsc911x irq")) {
pr_err("Failed to request IRQ GPIO%d\n", gpmc_cfg->gpio_irq);
goto free1;
}
gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
ret = gpio_request_one(gpmc_cfg->gpio_reset,
GPIOF_OUT_INIT_HIGH, "smsc911x reset");
if (ret) {
pr_err("Failed to request reset GPIO%d\n",
gpmc_cfg->gpio_reset);
goto free2;
}
gpio_set_value(gpmc_cfg->gpio_reset, 0);
msleep(100);
gpio_set_value(gpmc_cfg->gpio_reset, 1);
}
gpmc_smsc911x_config.flags = gpmc_cfg->flags ? : SMSC911X_USE_16BIT;
pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
&gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
if (IS_ERR(pdev)) {
pr_err("Unable to register platform device\n");
gpio_free(gpmc_cfg->gpio_reset);
goto free2;
}
return;
free2:
gpio_free(gpmc_cfg->gpio_irq);
free1:
gpmc_cs_free(gpmc_cfg->cs);
pr_err("Could not initialize smsc911x device\n");
}

35
arch/arm/mach-omap2/gpmc-smsc911x.h
View File

@ -1,35 +0,0 @@
/*
* arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
*
* Copyright (C) 2009 Li-Pro.Net
* Stephan Linz <linz@li-pro.net>
*
* Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
struct omap_smsc911x_platform_data {
int id;
int cs;
int gpio_irq;
int gpio_reset;
u32 flags;
};
#if IS_ENABLED(CONFIG_SMSC911X)
extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
#else
static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
{
}
#endif
#endif

88
arch/arm/mach-omap2/hsmmc.c
View File

@ -22,7 +22,6 @@
#include "omap_device.h"
#include "omap-pm.h"
#include "mux.h"
#include "hsmmc.h"
#include "control.h"
@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
return 0;
}
static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
*mmc_controller, int controller_nr)
{
if (gpio_is_valid(mmc_controller->gpio_cd) &&
(mmc_controller->gpio_cd < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_cd,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller->gpio_cod) &&
(mmc_controller->gpio_cod < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_cod,
OMAP_PIN_INPUT_PULLUP);
if (gpio_is_valid(mmc_controller->gpio_wp) &&
(mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7
* need to be muxed in the board-*.c files
*/
if (mmc_controller->caps &
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->caps &
MMC_CAP_8_BIT_DATA) {
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
}
}
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_hsmmc_platform_data *mmc)
{
@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
if (res < 0)
goto free_mmc;
omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
name = "omap_hsmmc";
res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
"mmc%d", ctrl_nr);

97
arch/arm/mach-omap2/i2c.c
View File

@ -26,7 +26,6 @@
#include "prm.h"
#include "common.h"
#include "mux.h"
#include "i2c.h"
/* In register I2C_CON, Bit 15 is the I2C enable bit */
@ -36,20 +35,6 @@
#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
static void __init omap2_i2c_mux_pins(int bus_id)
{
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
/* First I2C bus is not muxable */
if (bus_id == 1)
return;
sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}
/**
* omap_i2c_reset - reset the omap i2c module.
* @oh: struct omap_hwmod *
@ -107,85 +92,3 @@ int omap_i2c_reset(struct omap_hwmod *oh)
return 0;
}
static int __init omap_i2c_nr_ports(void)
{
int ports = 0;
if (cpu_is_omap24xx())
ports = 2;
else if (cpu_is_omap34xx())
ports = 3;
else if (cpu_is_omap44xx())
ports = 4;
return ports;
}
/*
* XXX This function is a temporary compatibility wrapper - only
* needed until the I2C driver can be converted to call
* omap_pm_set_max_dev_wakeup_lat() and handle a return code.
*/
static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
{
omap_pm_set_max_mpu_wakeup_lat(dev, t);
}
static const char name[] = "omap_i2c";
int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
int bus_id)
{
int l;
struct omap_hwmod *oh;
struct platform_device *pdev;
char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
struct omap_i2c_bus_platform_data *pdata;
struct omap_i2c_dev_attr *dev_attr;
if (bus_id > omap_i2c_nr_ports())
return -EINVAL;
omap2_i2c_mux_pins(bus_id);
l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
"String buffer overflow in I2C%d device setup\n", bus_id);
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return -EEXIST;
}
pdata = i2c_pdata;
/*
* pass the hwmod class's CPU-specific knowledge of I2C IP revision in
* use, and functionality implementation flags, up to the OMAP I2C
* driver via platform data
*/
pdata->rev = oh->class->rev;
dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
pdata->flags = dev_attr->flags;
/*
* When waiting for completion of a i2c transfer, we need to
* set a wake up latency constraint for the MPU. This is to
* ensure quick enough wakeup from idle, when transfer
* completes.
* Only omap3 has support for constraints
*/
if (cpu_is_omap34xx())
pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
pdev = omap_device_build(name, bus_id, oh, pdata,
sizeof(struct omap_i2c_bus_platform_data));
WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
return PTR_ERR_OR_ZERO(pdev);
}
static int __init omap_i2c_cmdline(void)
{
return omap_register_i2c_bus_cmdline();
}
omap_subsys_initcall(omap_i2c_cmdline);

4
arch/arm/mach-omap2/io.c
View File

@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void)
static void __init __maybe_unused omap_common_late_init(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap_soc_device_init();
}
@ -717,10 +716,11 @@ void __init omap5_init_early(void)
OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap2_control_base_init();
omap4_pm_init_early();
omap2_prcm_base_init();
omap5xxx_check_revision();
omap4_sar_ram_init();
omap4_mpuss_early_init();
omap4_pm_init_early();
omap54xx_voltagedomains_init();
omap54xx_powerdomains_init();
omap54xx_clockdomains_init();

1
arch/arm/mach-omap2/msdi.c
View File

@ -30,7 +30,6 @@
#include "control.h"
#include "omap_hwmod.h"
#include "omap_device.h"
#include "mux.h"
#include "mmc.h"
/*

1153
arch/arm/mach-omap2/mux.c
View File

File diff suppressed because it is too large Load Diff

352
arch/arm/mach-omap2/mux.h
View File

@ -1,352 +0,0 @@
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009-2010 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "mux34xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
/* 34xx mux mode options for each pin. See TRM for options */
#define OMAP_MUX_MODE0 0
#define OMAP_MUX_MODE1 1
#define OMAP_MUX_MODE2 2
#define OMAP_MUX_MODE3 3
#define OMAP_MUX_MODE4 4
#define OMAP_MUX_MODE5 5
#define OMAP_MUX_MODE6 6
#define OMAP_MUX_MODE7 7
/* 24xx/34xx mux bit defines */
#define OMAP_PULL_ENA (1 << 3)
#define OMAP_PULL_UP (1 << 4)
#define OMAP_ALTELECTRICALSEL (1 << 5)
/* omap3/4/5 specific mux bit defines */
#define OMAP_INPUT_EN (1 << 8)
#define OMAP_OFF_EN (1 << 9)
#define OMAP_OFFOUT_EN (1 << 10)
#define OMAP_OFFOUT_VAL (1 << 11)
#define OMAP_OFF_PULL_EN (1 << 12)
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
#define OMAP_WAKEUP_EVENT (1 << 15)
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
| OMAP_PULL_UP)
#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
/* Off mode states */
#define OMAP_PIN_OFF_NONE 0
#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
| OMAP_OFFOUT_VAL)
#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
| OMAP_OFF_PULL_UP)
#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
partition->gpio)
#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
/* Flags for omapX_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */
#define OMAP_MUX_NR_MODES 8 /* Available modes */
#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
/*
* omap_mux_init flags definition:
*
* OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
* register which includes values from 0-7.
* OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
* The default value is 16 bits.
*/
#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
#define OMAP_MUX_REG_8BIT (1 << 3)
/**
* struct omap_board_data - board specific device data
* @id: instance id
* @flags: additional flags for platform init code
* @pads: array of device specific pads
* @pads_cnt: ARRAY_SIZE() of pads
*/
struct omap_board_data {
int id;
u32 flags;
struct omap_device_pad *pads;
int pads_cnt;
};
/**
* struct mux_partition - contain partition related information
* @name: name of the current partition
* @flags: flags specific to this partition
* @gpio: gpio mux mode
* @phys: physical address
* @size: partition size
* @base: virtual address after ioremap
* @muxmodes: list of nodes that belong to a partition
* @node: list node for the partitions linked list
*/
struct omap_mux_partition {
const char *name;
u32 flags;
u32 gpio;
u32 phys;
u32 size;
void __iomem *base;
struct list_head muxmodes;
struct list_head node;
};
/**
* struct omap_mux - data for omap mux register offset and it's value
* @reg_offset: mux register offset from the mux base
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
* @balls: available balls on the package
*/
struct omap_mux {
u16 reg_offset;
u16 gpio;
#ifdef CONFIG_OMAP_MUX
char *muxnames[OMAP_MUX_NR_MODES];
#ifdef CONFIG_DEBUG_FS
char *balls[OMAP_MUX_NR_SIDES];
#endif
#endif
};
/**
* struct omap_ball - data for balls on omap package
* @reg_offset: mux register offset from the mux base
* @balls: available balls on the package
*/
struct omap_ball {
u16 reg_offset;
char *balls[OMAP_MUX_NR_SIDES];
};
/**
* struct omap_board_mux - data for initializing mux registers
* @reg_offset: mux register offset from the mux base
* @mux_value: desired mux value to set
*/
struct omap_board_mux {
u16 reg_offset;
u16 value;
};
#define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
needs enable, idle and off
values */
#define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */
/**
* struct omap_device_pad - device specific pad configuration
* @name: signal name
* @flags: pad specific runtime flags
* @enable: runtime value for a pad
* @idle: idle value for a pad
* @off: off value for a pad, defaults to safe mode
* @partition: mux partition
* @mux: mux register
*/
struct omap_device_pad {
char *name;
u8 flags;
u16 enable;
u16 idle;
u16 off;
struct omap_mux_partition *partition;
struct omap_mux *mux;
};
struct omap_hwmod_mux_info;
#define OMAP_MUX_STATIC(signal, mode) \
{ \
.name = (signal), \
.enable = (mode), \
}
#if defined(CONFIG_OMAP_MUX)
/**
* omap_mux_init_gpio - initialize a signal based on the GPIO number
* @gpio: GPIO number
* @val: Options for the mux register value
*/
int omap_mux_init_gpio(int gpio, int val);
/**
* omap_mux_init_signal - initialize a signal based on the signal name
* @muxname: Mux name in mode0_name.signal_name format
* @val: Options for the mux register value
*/
int omap_mux_init_signal(const char *muxname, int val);
/**
* omap_hwmod_mux_init - initialize hwmod specific mux data
* @bpads: Board specific device signal names
* @nr_pads: Number of signal names for the device
*/
extern struct omap_hwmod_mux_info *
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
/**
* omap_hwmod_mux - omap hwmod specific pin muxing
* @hmux: Pads for a hwmod
* @state: Desired _HWMOD_STATE
*
* Called only from omap_hwmod.c, do not use.
*/
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
int omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux);
#else
static inline int omap_mux_get_by_name(const char *muxname,
struct omap_mux_partition **found_partition,
struct omap_mux **found_mux)
{
return 0;
}
static inline int omap_mux_init_gpio(int gpio, int val)
{
return 0;
}
static inline int omap_mux_init_signal(char *muxname, int val)
{
return 0;
}
static inline struct omap_hwmod_mux_info *
omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
{
return NULL;
}
static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
}
static struct omap_board_mux *board_mux __maybe_unused;
#endif
/**
* omap_mux_get_gpio() - get mux register value based on GPIO number
* @gpio: GPIO number
*
*/
u16 omap_mux_get_gpio(int gpio);
/**
* omap_mux_set_gpio() - set mux register value based on GPIO number
* @val: New mux register value
* @gpio: GPIO number
*
*/
void omap_mux_set_gpio(u16 val, int gpio);
/**
* omap_mux_get() - get a mux partition by name
* @name: Name of the mux partition
*
*/
struct omap_mux_partition *omap_mux_get(const char *name);
/**
* omap_mux_read() - read mux register
* @partition: Mux partition
* @mux_offset: Offset of the mux register
*
*/
u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
/**
* omap_mux_write() - write mux register
* @partition: Mux partition
* @val: New mux register value
* @mux_offset: Offset of the mux register
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
/**
* omap_mux_write_array() - write an array of mux registers
* @partition: Mux partition
* @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write_array(struct omap_mux_partition *p,
struct omap_board_mux *board_mux);
/**
* omap2420_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap2430_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap3_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap4_mux_init() - initialize mux system with board specific set
* @board_subset: Board specific mux table
* @board_wkup_subset: Board specific mux table for wakeup instance
* @flags: OMAP package type used for the board
*/
int omap4_mux_init(struct omap_board_mux *board_subset,
struct omap_board_mux *board_wkup_subset, int flags);
/**
* omap_mux_init - private mux init function, do not call
*/
int omap_mux_init(const char *name, u32 flags,
u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls);

2061
arch/arm/mach-omap2/mux34xx.c
View File

File diff suppressed because it is too large Load Diff

402
arch/arm/mach-omap2/mux34xx.h
View File

@ -1,402 +0,0 @@
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
#define OMAP3_MUX(mode0, mux_value) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
.value = (mux_value), \
}
/*
* OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
*
* Extracted from the TRM. Add 0x48002030 to these values to get the
* absolute addresses. The name in the macro is the mode-0 name of
* the pin. NOTE: These registers are 16-bits wide.
*
* Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
* of CHASSIS for some registers. For the defines, we follow the
* 36XX naming, and use SDMMC and CHASSIS.
*/
#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
/* 36xx only */
#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
#define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24
#define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26
#define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28
#define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a
#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
(OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2)

37
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -48,6 +48,7 @@
#include <asm/smp_scu.h>
#include <asm/pgalloc.h>
#include <asm/suspend.h>
#include <asm/virt.h>
#include <asm/hardware/cache-l2x0.h>
#include "soc.h"
@ -244,10 +245,9 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
save_state = 1;
break;
case PWRDM_POWER_RET:
if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
save_state = 0;
break;
}
break;
default:
/*
* CPUx CSWR is invalid hardware state. Also CPUx OSWR
@ -371,8 +371,12 @@ int __init omap4_mpuss_init(void)
pm_info = &per_cpu(omap4_pm_info, 0x0);
if (sar_base) {
pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
pm_info->wkup_sar_addr = sar_base +
CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
if (cpu_is_omap44xx())
pm_info->wkup_sar_addr = sar_base +
CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
else
pm_info->wkup_sar_addr = sar_base +
OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
}
pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
@ -391,8 +395,12 @@ int __init omap4_mpuss_init(void)
pm_info = &per_cpu(omap4_pm_info, 0x1);
if (sar_base) {
pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
pm_info->wkup_sar_addr = sar_base +
CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
if (cpu_is_omap44xx())
pm_info->wkup_sar_addr = sar_base +
CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
else
pm_info->wkup_sar_addr = sar_base +
OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
}
@ -453,15 +461,24 @@ void __init omap4_mpuss_early_init(void)
{
unsigned long startup_pa;
if (!cpu_is_omap44xx())
if (!(cpu_is_omap44xx() || soc_is_omap54xx()))
return;
sar_base = omap4_get_sar_ram_base();
if (cpu_is_omap443x())
startup_pa = virt_to_phys(omap4_secondary_startup);
else
else if (cpu_is_omap446x())
startup_pa = virt_to_phys(omap4460_secondary_startup);
else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
else
startup_pa = virt_to_phys(omap5_secondary_startup);
writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
if (cpu_is_omap44xx())
writel_relaxed(startup_pa, sar_base +
CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
else
writel_relaxed(startup_pa, sar_base +
OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
}

2
arch/arm/mach-omap2/omap4-sar-layout.h
View File

@ -31,6 +31,8 @@
/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00
#define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04
#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500)
#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504)

107
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -160,7 +160,6 @@
#include "prm44xx.h"
#include "prm33xx.h"
#include "prminst44xx.h"
#include "mux.h"
#include "pm.h"
/* Name of the OMAP hwmod for the MPU */
@ -217,9 +216,6 @@ static LIST_HEAD(omap_hwmod_list);
/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
static struct omap_hwmod *mpu_oh;
/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
static DEFINE_SPINLOCK(io_chain_lock);
/*
* linkspace: ptr to a buffer that struct omap_hwmod_link records are
* allocated from - used to reduce the number of small memory
@ -593,51 +589,6 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
return 0;
}
/**
* _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
* @oh: struct omap_hwmod *
* @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
*
* Set or clear the I/O pad wakeup flag in the mux entries for the
* hwmod @oh. This function changes the @oh->mux->pads_dynamic array
* in memory. If the hwmod is currently idled, and the new idle
* values don't match the previous ones, this function will also
* update the SCM PADCTRL registers. Otherwise, if the hwmod is not
* currently idled, this function won't touch the hardware: the new
* mux settings are written to the SCM PADCTRL registers when the
* hwmod is idled. No return value.
*/
static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
{
struct omap_device_pad *pad;
bool change = false;
u16 prev_idle;
int j;
if (!oh->mux || !oh->mux->enabled)
return;
for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
pad = oh->mux->pads_dynamic[j];
if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
continue;
prev_idle = pad->idle;
if (set_wake)
pad->idle |= OMAP_WAKEUP_EN;
else
pad->idle &= ~OMAP_WAKEUP_EN;
if (prev_idle != pad->idle)
change = true;
}
if (change && oh->_state == _HWMOD_STATE_IDLE)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
}
/**
* _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
* @oh: struct omap_hwmod *
@ -2017,29 +1968,6 @@ static int _reset(struct omap_hwmod *oh)
return r;
}
/**
* _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
*
* Call the appropriate PRM function to clear any logged I/O chain
* wakeups and to reconfigure the chain. This apparently needs to be
* done upon every mux change. Since hwmods can be concurrently
* enabled and idled, hold a spinlock around the I/O chain
* reconfiguration sequence. No return value.
*
* XXX When the PRM code is moved to drivers, this function can be removed,
* as the PRM infrastructure should abstract this.
*/
static void _reconfigure_io_chain(void)
{
unsigned long flags;
spin_lock_irqsave(&io_chain_lock, flags);
omap_prm_reconfigure_io_chain();
spin_unlock_irqrestore(&io_chain_lock, flags);
}
/**
* _omap4_update_context_lost - increment hwmod context loss counter if
* hwmod context was lost, and clear hardware context loss reg
@ -2109,18 +2037,9 @@ static int _enable(struct omap_hwmod *oh)
/*
* hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
* state at init. Now that someone is really trying to enable
* them, just ensure that the hwmod mux is set.
* state at init.
*/
if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
/*
* If the caller has mux data populated, do the mux'ing
* which wouldn't have been done as part of the _enable()
* done during setup.
*/
if (oh->mux)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
return 0;
}
@ -2145,16 +2064,6 @@ static int _enable(struct omap_hwmod *oh)
if (_are_all_hardreset_lines_asserted(oh))
return 0;
/* Mux pins for device runtime if populated */
if (oh->mux && (!oh->mux->enabled ||
((oh->_state == _HWMOD_STATE_IDLE) &&
oh->mux->pads_dynamic))) {
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
_reconfigure_io_chain();
} else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
_reconfigure_io_chain();
}
_add_initiator_dep(oh, mpu_oh);
if (oh->clkdm) {
@ -2260,14 +2169,6 @@ static int _idle(struct omap_hwmod *oh)
clkdm_hwmod_disable(oh->clkdm, oh);
}
/* Mux pins for device idle if populated */
if (oh->mux && oh->mux->pads_dynamic) {
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
_reconfigure_io_chain();
} else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
_reconfigure_io_chain();
}
oh->_state = _HWMOD_STATE_IDLE;
return 0;
@ -2334,10 +2235,6 @@ static int _shutdown(struct omap_hwmod *oh)
for (i = 0; i < oh->rst_lines_cnt; i++)
_assert_hardreset(oh, oh->rst_lines[i].name);
/* Mux pins to safe mode or use populated off mode values */
if (oh->mux)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
oh->_state = _HWMOD_STATE_DISABLED;
return 0;
@ -3729,7 +3626,6 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
_write_sysconfig(v, oh);
}
_set_idle_ioring_wakeup(oh, true);
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
@ -3762,7 +3658,6 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
_write_sysconfig(v, oh);
}
_set_idle_ioring_wakeup(oh, false);
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;

149
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
View File

@ -17,156 +17,11 @@
#include "omap_hwmod_common_data.h"
struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
{
.pa_start = 0x4809c000,
.pa_end = 0x4809c1ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
{
.pa_start = 0x480b4000,
.pa_end = 0x480b41ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x48070000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x48072000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x48050000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x48050400 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050800 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050C00 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x48086000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x48088000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
{
.pa_start = 0x4808a000,
.pa_end = 0x4808a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x48098000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b8000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x48056000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48074000,
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
{
.pa_start = 0x480b2000,
.pa_end = 0x480b2fff,
.flags = ADDR_TYPE_RT,
},
{ }
{ },
};

201
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
View File

@ -45,204 +45,31 @@ struct omap_hwmod_class omap2_venc_hwmod_class = {
.name = "venc",
};
/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 50, },
{ .name = "tx", .dma_req = 49, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 52, },
{ .name = "tx", .dma_req = 51, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 54, },
{ .name = "tx", .dma_req = 53, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 27 },
{ .name = "rx", .dma_req = 28 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 29 },
{ .name = "rx", .dma_req = 30 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
{ .dma_req = -1 }
};
/* Other IP block data */
/*
* omap_hwmod class data
*/
struct omap_hwmod_class l3_hwmod_class = {
.name = "l3"
.name = "l3",
};
struct omap_hwmod_class l4_hwmod_class = {
.name = "l4"
.name = "l4",
};
struct omap_hwmod_class mpu_hwmod_class = {
.name = "mpu"
.name = "mpu",
};
struct omap_hwmod_class iva_hwmod_class = {
.name = "iva"
.name = "iva",
};
/* Common MPU IRQ line data */
struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
{ .irq = 37 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
{ .irq = 38 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
{ .irq = 39 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
{ .irq = 40 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
{ .irq = 41 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
{ .irq = 42 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
{ .irq = 43 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
{ .irq = 44 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
{ .irq = 45 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
{ .irq = 46 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
{ .irq = 47 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
{ .irq = 72 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
{ .irq = 73 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
{ .irq = 74 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
{ .irq = 25 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
{ .irq = 56 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
{ .irq = 57 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
{ .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
{ .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
{ .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
{ .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
{ .irq = -1 },
{ .irq = -1, },
};
struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
@ -250,17 +77,7 @@ struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
{ .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
{ .irq = 65 + OMAP_INTC_START, },
{ .irq = -1 },
};
struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
{ .irq = 66 + OMAP_INTC_START, },
{ .irq = -1 },
{ .irq = -1, },
};
struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
@ -277,9 +94,3 @@ struct omap_hwmod_class omap2_hdq1w_class = {
.sysc = &omap2_hdq1w_sysc,
.reset = &omap_hdq1w_reset,
};
struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
{ .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
};

4
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
View File

@ -191,7 +191,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
.master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_core_hwmod,
.clk = "dss_ick",
.addr = omap2_dss_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@ -206,7 +205,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
.master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_dispc_hwmod,
.clk = "dss_ick",
.addr = omap2_dss_dispc_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@ -221,7 +219,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
.master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_rfbi_hwmod,
.clk = "dss_ick",
.addr = omap2_dss_rfbi_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@ -236,7 +233,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
.master = &omap2xxx_l4_core_hwmod,
.slave = &omap2xxx_dss_venc_hwmod,
.clk = "dss_ick",
.addr = omap2_dss_venc_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,

1
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View File

@ -569,7 +569,6 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = {
struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap2_dispc_hwmod_class,
.mpu_irqs = omap2_dispc_irqs,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {

2
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View File

@ -68,6 +68,7 @@ extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart6;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
extern struct omap_hwmod_ocp_if am33xx_l4_per__rng;
extern struct omap_hwmod am33xx_l3_main_hwmod;
extern struct omap_hwmod am33xx_l3_s_hwmod;
@ -80,6 +81,7 @@ extern struct omap_hwmod am33xx_gfx_hwmod;
extern struct omap_hwmod am33xx_prcm_hwmod;
extern struct omap_hwmod am33xx_aes0_hwmod;
extern struct omap_hwmod am33xx_sha0_hwmod;
extern struct omap_hwmod am33xx_rng_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;

8
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View File

@ -547,3 +547,11 @@ struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
.addr = am33xx_aes0_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per -> rng */
struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_rng_hwmod,
.clk = "rng_fck",
.user = OCP_USER_MPU,
};

29
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -268,6 +268,33 @@ struct omap_hwmod am33xx_sha0_hwmod = {
},
};
/* rng */
static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
.rev_offs = 0x1fe0,
.sysc_offs = 0x1fe4,
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO,
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_rng_hwmod_class = {
.name = "rng",
.sysc = &am33xx_rng_sysc,
};
struct omap_hwmod am33xx_rng_hwmod = {
.name = "rng",
.class = &am33xx_rng_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "rng_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
@ -1315,6 +1342,7 @@ static void omap_hwmod_am33xx_clkctrl(void)
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
}
static void omap_hwmod_am33xx_rst(void)
@ -1388,6 +1416,7 @@ static void omap_hwmod_am43xx_clkctrl(void)
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
}
static void omap_hwmod_am43xx_rst(void)

35
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -503,41 +503,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.flags = OCPIF_SWSUP_IDLE,
};
/* rng */
static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
.rev_offs = 0x1fe0,
.sysc_offs = 0x1fe4,
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO,
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_rng_hwmod_class = {
.name = "rng",
.sysc = &am33xx_rng_sysc,
};
static struct omap_hwmod am33xx_rng_hwmod = {
.name = "rng",
.class = &am33xx_rng_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "rng_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_rng_hwmod,
.clk = "rng_fck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,

787
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

File diff suppressed because it is too large Load Diff

34
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View File

@ -442,6 +442,31 @@ static struct omap_hwmod am43xx_adc_tsc_hwmod = {
},
};
static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
.rev_offs = 0x30,
.sysc_offs = 0x34,
.syss_offs = 0x38,
.sysc_flags = SYSS_HAS_RESET_STATUS,
};
static struct omap_hwmod_class am43xx_des_hwmod_class = {
.name = "des",
.sysc = &am43xx_des_sysc,
};
static struct omap_hwmod am43xx_des_hwmod = {
.name = "des",
.class = &am43xx_des_hwmod_class,
.clkdm_name = "l3_clkdm",
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* dss */
static struct omap_hwmod am43xx_dss_core_hwmod = {
@ -870,6 +895,13 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
.master = &am33xx_l3_main_hwmod,
.slave = &am43xx_des_hwmod,
.clk = "l3_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__synctimer,
&am43xx_l4_ls__timer8,
@ -917,6 +949,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_per__i2c2,
&am33xx_l4_per__i2c3,
&am33xx_l4_per__mailbox,
&am33xx_l4_per__rng,
&am33xx_l4_ls__mcasp0,
&am33xx_l4_ls__mcasp1,
&am33xx_l4_ls__mmc0,
@ -950,6 +983,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_cpgmac0__mdio,
&am33xx_l3_main__sha0,
&am33xx_l3_main__aes0,
&am43xx_l3_main__des,
&am43xx_l4_ls__ocp2scp0,
&am43xx_l4_ls__ocp2scp1,
&am43xx_l3_s__usbotgss0,

182
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -690,6 +690,78 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
.parent_hwmod = &dra7xx_dss_hwmod,
};
/* AES (the 'P' (public) device) */
static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
.rev_offs = 0x0080,
.sysc_offs = 0x0084,
.syss_offs = 0x0088,
.sysc_flags = SYSS_HAS_RESET_STATUS,
};
static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
.name = "aes",
.sysc = &dra7xx_aes_sysc,
.rev = 2,
};
/* AES1 */
static struct omap_hwmod dra7xx_aes1_hwmod = {
.name = "aes1",
.class = &dra7xx_aes_hwmod_class,
.clkdm_name = "l4sec_clkdm",
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* AES2 */
static struct omap_hwmod dra7xx_aes2_hwmod = {
.name = "aes2",
.class = &dra7xx_aes_hwmod_class,
.clkdm_name = "l4sec_clkdm",
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* sha0 HIB2 (the 'P' (public) device) */
static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
.rev_offs = 0x100,
.sysc_offs = 0x110,
.syss_offs = 0x114,
.sysc_flags = SYSS_HAS_RESET_STATUS,
};
static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
.name = "sham",
.sysc = &dra7xx_sha0_sysc,
.rev = 2,
};
struct omap_hwmod dra7xx_sha0_hwmod = {
.name = "sham",
.class = &dra7xx_sha0_hwmod_class,
.clkdm_name = "l4sec_clkdm",
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'elm' class
*
@ -2541,6 +2613,62 @@ static struct omap_hwmod dra7xx_uart10_hwmod = {
},
};
/* DES (the 'P' (public) device) */
static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
.rev_offs = 0x0030,
.sysc_offs = 0x0034,
.syss_offs = 0x0038,
.sysc_flags = SYSS_HAS_RESET_STATUS,
};
static struct omap_hwmod_class dra7xx_des_hwmod_class = {
.name = "des",
.sysc = &dra7xx_des_sysc,
};
/* DES */
static struct omap_hwmod dra7xx_des_hwmod = {
.name = "des",
.class = &dra7xx_des_hwmod_class,
.clkdm_name = "l4sec_clkdm",
.main_clk = "l3_iclk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/* rng */
static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
.rev_offs = 0x1fe0,
.sysc_offs = 0x1fe4,
.sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO,
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
.name = "rng",
.sysc = &dra7xx_rng_sysc,
};
static struct omap_hwmod dra7xx_rng_hwmod = {
.name = "rng",
.class = &dra7xx_rng_hwmod_class,
.flags = HWMOD_SWSUP_SIDLE,
.clkdm_name = "l4sec_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'usb_otg_ss' class
*
@ -2929,6 +3057,30 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> aes1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_aes1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> aes2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_aes2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> sha0 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_sha0_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
.master = &dra7xx_l4_per2_hwmod,
@ -3642,6 +3794,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> des */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_des_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> uart8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
.master = &dra7xx_l4_per2_hwmod,
@ -3666,6 +3826,13 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> rng */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_rng_hwmod,
.user = OCP_USER_MPU,
};
/* l4_per3 -> usb_otg_ss1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
.master = &dra7xx_l4_per3_hwmod,
@ -3800,6 +3967,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
&dra7xx_l3_main_1__hdmi,
&dra7xx_l3_main_1__aes1,
&dra7xx_l3_main_1__aes2,
&dra7xx_l3_main_1__sha0,
&dra7xx_l4_per1__elm,
&dra7xx_l4_wkup__gpio1,
&dra7xx_l4_per1__gpio2,
@ -3845,7 +4015,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__pciess2,
&dra7xx_l4_cfg__pciess2,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_per3__rtcss,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
&dra7xx_l4_cfg__smartreflex_mpu,
@ -3875,6 +4044,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per2__uart8,
&dra7xx_l4_per2__uart9,
&dra7xx_l4_wkup__uart10,
&dra7xx_l4_per1__des,
&dra7xx_l4_per3__usb_otg_ss1,
&dra7xx_l4_per3__usb_otg_ss2,
&dra7xx_l4_per3__usb_otg_ss3,
@ -3892,6 +4062,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
/* GP-only hwmod links */
static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_wkup__timer12,
&dra7xx_l4_per1__rng,
NULL,
};
@ -3905,6 +4076,11 @@ static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
NULL,
};
static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per3__rtcss,
NULL,
};
int __init dra7xx_hwmod_init(void)
{
int ret;
@ -3920,5 +4096,9 @@ int __init dra7xx_hwmod_init(void)
if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
/* now for the IPs *NOT* in dra71 */
if (!ret && !of_machine_is_compatible("ti,dra718"))
ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
return ret;
}

15
arch/arm/mach-omap2/omap_hwmod_common_data.h
View File

@ -19,22 +19,7 @@
#include "display.h"
/* Common address space across OMAP2xxx/3xxx */
extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
extern struct omap_hwmod_addr_space omap2_dss_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
/* Common IP block data across OMAP2xxx */
extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;

1
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -31,7 +31,6 @@
#include "common.h"
#include "common-board-devices.h"
#include "dss-common.h"
#include "control.h"
#include "omap_device.h"
#include "omap-pm.h"

66
arch/arm/mach-omap2/pm.c
View File

@ -30,7 +30,6 @@
#include "powerdomain.h"
#include "clockdomain.h"
#include "pm.h"
#include "twl-common.h"
#ifdef CONFIG_SUSPEND
/*
@ -72,42 +71,6 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
}
#endif
static int __init _init_omap_device(char *name)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
oh = omap_hwmod_lookup(name);
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
__func__, name))
return -ENODEV;
pdev = omap_device_build(oh->name, 0, oh, NULL, 0);
if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
__func__, name))
return -ENODEV;
return 0;
}
/*
* Build omap_devices for processors and bus.
*/
static void __init omap2_init_processor_devices(void)
{
_init_omap_device("mpu");
if (omap3_has_iva())
_init_omap_device("iva");
if (cpu_is_omap44xx()) {
_init_omap_device("l3_main_1");
_init_omap_device("dsp");
_init_omap_device("iva");
} else {
_init_omap_device("l3_main");
}
}
int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
{
clkdm_allow_idle(clkdm);
@ -215,7 +178,7 @@ static int omap_pm_enter(suspend_state_t suspend_state)
static int omap_pm_begin(suspend_state_t state)
{
cpu_idle_poll_ctrl(true);
if (cpu_is_omap34xx())
if (soc_is_omap34xx())
omap_prcm_irq_prepare();
return 0;
}
@ -227,7 +190,7 @@ static void omap_pm_end(void)
static void omap_pm_finish(void)
{
if (cpu_is_omap34xx())
if (soc_is_omap34xx())
omap_prcm_irq_complete();
}
@ -252,7 +215,7 @@ void omap_common_suspend_init(void *pm_suspend)
static void __init omap3_init_voltages(void)
{
if (!cpu_is_omap34xx())
if (!soc_is_omap34xx())
return;
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
@ -261,7 +224,7 @@ static void __init omap3_init_voltages(void)
static void __init omap4_init_voltages(void)
{
if (!cpu_is_omap44xx())
if (!soc_is_omap44xx())
return;
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
@ -269,18 +232,8 @@ static void __init omap4_init_voltages(void)
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
}
static inline void omap_init_cpufreq(void)
{
struct platform_device_info devinfo = { .name = "omap-cpufreq" };
if (!of_have_populated_dt())
platform_device_register_full(&devinfo);
}
static int __init omap2_common_pm_init(void)
{
if (!of_have_populated_dt())
omap2_init_processor_devices();
omap_pm_if_init();
return 0;
@ -289,13 +242,9 @@ omap_postcore_initcall(omap2_common_pm_init);
int __init omap2_common_pm_late_init(void)
{
if (of_have_populated_dt()) {
omap3_twl_init();
omap4_twl_init();
}
/* Init the voltage layer */
omap_pmic_late_init();
omap3_twl_init();
omap4_twl_init();
omap_voltage_late_init();
/* Initialize the voltages */
@ -305,8 +254,5 @@ int __init omap2_common_pm_late_init(void)
/* Smartreflex device init */
omap_devinit_smartreflex();
/* cpufreq dummy device instantiation */
omap_init_cpufreq();
return 0;
}

2
arch/arm/mach-omap2/pm44xx.c
View File

@ -287,7 +287,7 @@ int __init omap4_pm_init(void)
/* Overwrite the default cpu_do_idle() */
arm_pm_idle = omap_default_idle;
if (cpu_is_omap44xx())
if (cpu_is_omap44xx() || soc_is_omap54xx())
omap4_idle_init();
err2:

2
arch/arm/mach-omap2/prcm43xx.h
View File

@ -92,6 +92,7 @@
#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8
#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0
#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8
#define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0
#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500
#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508
#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528
@ -133,6 +134,7 @@
#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050
#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058
#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028
#define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030
#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560
#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568
#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570

51
arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
View File

@ -1,51 +0,0 @@
/*
* SDRC register values for the Hynix H8MBX00U0MER-0EM
*
* Copyright (C) 2009 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
#define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
#include "sdrc.h"
/* Hynix H8MBX00U0MER-0EM */
static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
[0] = {
.rate = 200000000,
.actim_ctrla = 0xa2e1b4c6,
.actim_ctrlb = 0x0002131c,
.rfr_ctrl = 0x0005e601,
.mr = 0x00000032,
},
[1] = {
.rate = 166000000,
.actim_ctrla = 0x629db4c6,
.actim_ctrlb = 0x00012214,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 100000000,
.actim_ctrla = 0x51912284,
.actim_ctrlb = 0x0002120e,
.rfr_ctrl = 0x0002d101,
.mr = 0x00000022,
},
[3] = {
.rate = 83000000,
.actim_ctrla = 0x31512283,
.actim_ctrlb = 0x0001220a,
.rfr_ctrl = 0x00025501,
.mr = 0x00000022,
},
[4] = {
.rate = 0
},
};
#endif

55
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
View File

@ -1,55 +0,0 @@
/*
* SDRC register values for the Micron MT46H32M32LF-6
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Nokia Corporation
*
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
#include "sdrc.h"
/* Micron MT46H32M32LF-6 */
/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
[0] = {
.rate = 166000000,
.actim_ctrla = 0x9a9db4c6,
.actim_ctrlb = 0x00011217,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[1] = {
.rate = 165941176,
.actim_ctrla = 0x9a9db4c6,
.actim_ctrlb = 0x00011217,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 83000000,
.actim_ctrla = 0x51512283,
.actim_ctrlb = 0x0001120c,
.rfr_ctrl = 0x00025501,
.mr = 0x00000032,
},
[3] = {
.rate = 82970588,
.actim_ctrla = 0x51512283,
.actim_ctrlb = 0x0001120c,
.rfr_ctrl = 0x00025501,
.mr = 0x00000032,
},
[4] = {
.rate = 0
},
};
#endif

299
arch/arm/mach-omap2/sdram-nokia.c
View File

@ -1,299 +0,0 @@
/*
* SDRC register values for Nokia boards
*
* Copyright (C) 2008, 2010-2011 Nokia Corporation
*
* Lauri Leukkunen <lauri.leukkunen@nokia.com>
*
* Original code by Juha Yrjola <juha.yrjola@solidboot.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include "common.h"
#include "sdram-nokia.h"
#include "sdrc.h"
/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
struct sdram_timings {
u32 casl;
u32 tDAL;
u32 tDPL;
u32 tRRD;
u32 tRCD;
u32 tRP;
u32 tRAS;
u32 tRC;
u32 tRFC;
u32 tXSR;
u32 tREF; /* in ns */
u32 tXP;
u32 tCKE;
u32 tWTR;
};
static const struct sdram_timings nokia_97dot6mhz_timings[] = {
{
.casl = 3,
.tDAL = 30725,
.tDPL = 15362,
.tRRD = 10241,
.tRCD = 20483,
.tRP = 15362,
.tRAS = 40967,
.tRC = 56330,
.tRFC = 138266,
.tXSR = 204839,
.tREF = 7798,
.tXP = 2,
.tCKE = 4,
.tWTR = 2,
},
};
static const struct sdram_timings nokia_166mhz_timings[] = {
{
.casl = 3,
.tDAL = 33000,
.tDPL = 15000,
.tRRD = 12000,
.tRCD = 22500,
.tRP = 18000,
.tRAS = 42000,
.tRC = 66000,
.tRFC = 138000,
.tXSR = 200000,
.tREF = 7800,
.tXP = 2,
.tCKE = 2,
.tWTR = 2
},
};
static const struct sdram_timings nokia_195dot2mhz_timings[] = {
{
.casl = 3,
.tDAL = 30725,
.tDPL = 15362,
.tRRD = 10241,
.tRCD = 20483,
.tRP = 15362,
.tRAS = 40967,
.tRC = 56330,
.tRFC = 138266,
.tXSR = 204839,
.tREF = 7752,
.tXP = 2,
.tCKE = 4,
.tWTR = 2,
},
};
static const struct sdram_timings nokia_200mhz_timings[] = {
{
.casl = 3,
.tDAL = 30000,
.tDPL = 15000,
.tRRD = 10000,
.tRCD = 20000,
.tRP = 15000,
.tRAS = 40000,
.tRC = 55000,
.tRFC = 140000,
.tXSR = 200000,
.tREF = 7800,
.tXP = 2,
.tCKE = 4,
.tWTR = 2
},
};
static const struct {
long rate;
struct sdram_timings const *data;
} nokia_timings[] = {
{ 83000000, nokia_166mhz_timings },
{ 97600000, nokia_97dot6mhz_timings },
{ 100000000, nokia_200mhz_timings },
{ 166000000, nokia_166mhz_timings },
{ 195200000, nokia_195dot2mhz_timings },
{ 200000000, nokia_200mhz_timings },
};
static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
static unsigned long sdrc_get_fclk_period(long rate)
{
/* In picoseconds */
return 1000000000 / rate;
}
static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate)
{
unsigned long tick_ps;
/* Calculate in picosecs to yield more exact results */
tick_ps = sdrc_get_fclk_period(rate);
return (time_ps + tick_ps - 1) / tick_ps;
}
#undef DEBUG
#ifdef DEBUG
static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
int ticks, long rate, const char *name)
#else
static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
int ticks)
#endif
{
int mask, nr_bits;
nr_bits = end_bit - st_bit + 1;
if (ticks >= 1 << nr_bits)
return -1;
mask = (1 << nr_bits) - 1;
*regval &= ~(mask << st_bit);
*regval |= ticks << st_bit;
#ifdef DEBUG
printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks,
(unsigned int)sdrc_get_fclk_period(rate) * ticks /
1000);
#endif
return 0;
}
#ifdef DEBUG
#define SDRC_SET_ONE(reg, st, end, field, rate) \
if (set_sdrc_timing_regval((reg), (st), (end), \
memory_timings->field, (rate), #field) < 0) \
err = -1;
#else
#define SDRC_SET_ONE(reg, st, end, field, rate) \
if (set_sdrc_timing_regval((reg), (st), (end), \
memory_timings->field) < 0) \
err = -1;
#endif
#ifdef DEBUG
static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
int time, long rate, const char *name)
#else
static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
int time, long rate)
#endif
{
int ticks, ret;
ret = 0;
if (time == 0)
ticks = 0;
else
ticks = sdrc_ps_to_ticks(time, rate);
#ifdef DEBUG
ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks,
rate, name);
#else
ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks);
#endif
return ret;
}
#ifdef DEBUG
#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
if (set_sdrc_timing_regval_ps((reg), (st), (end), \
memory_timings->field, \
(rate), #field) < 0) \
err = -1;
#else
#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
if (set_sdrc_timing_regval_ps((reg), (st), (end), \
memory_timings->field, (rate)) < 0) \
err = -1;
#endif
static int sdrc_timings(int id, long rate,
const struct sdram_timings *memory_timings)
{
u32 ticks_per_ms;
u32 rfr, l;
u32 actim_ctrla = 0, actim_ctrlb = 0;
u32 rfr_ctrl;
int err = 0;
long l3_rate = rate / 1000;
SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
SDRC_SET_ONE_PS(&actim_ctrlb, 0, 7, tXSR, l3_rate);
SDRC_SET_ONE(&actim_ctrlb, 8, 10, tXP, l3_rate);
SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate);
SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
ticks_per_ms = l3_rate;
rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
if (rfr > 65535 + 50)
rfr = 65535;
else
rfr -= 50;
#ifdef DEBUG
printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr);
#endif
l = rfr << 8;
rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
nokia_sdrc_params[id].rate = rate;
nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
nokia_sdrc_params[id].mr = 0x32;
nokia_sdrc_params[id + 1].rate = 0;
return err;
}
struct omap_sdrc_params *nokia_get_sdram_timings(void)
{
int err = 0;
int i;
for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
err |= sdrc_timings(i, nokia_timings[i].rate,
nokia_timings[i].data);
if (err)
pr_err("%s: error with rate %ld: %d\n", __func__,
nokia_timings[i].rate, err);
}
return err ? NULL : nokia_sdrc_params;
}

12
arch/arm/mach-omap2/sdram-nokia.h
View File

@ -1,12 +0,0 @@
/*
* SDRC register values for Nokia boards
*
* Copyright (C) 2010 Nokia
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
struct omap_sdrc_params *nokia_get_sdram_timings(void);

51
arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
View File

@ -1,51 +0,0 @@
/*
* SDRC register values for the Numonyx M65KXXXXAM
*
* Copyright (C) 2009 Integration Software and Electronic Engineering.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
#define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
#include "sdrc.h"
/* Numonyx M65KXXXXAM */
static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
[0] = {
.rate = 200000000,
.actim_ctrla = 0xe321d4c6,
.actim_ctrlb = 0x00022328,
.rfr_ctrl = 0x0005e601,
.mr = 0x00000032,
},
[1] = {
.rate = 166000000,
.actim_ctrla = 0xba9dc485,
.actim_ctrlb = 0x00022321,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 133000000,
.actim_ctrla = 0x9a19b485,
.actim_ctrlb = 0x0002231b,
.rfr_ctrl = 0x0003de01,
.mr = 0x00000032,
},
[3] = {
.rate = 83000000,
.actim_ctrla = 0x594ca242,
.actim_ctrlb = 0x00022310,
.rfr_ctrl = 0x00025501,
.mr = 0x00000032,
},
[4] = {
.rate = 0
},
};
#endif

54
arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
View File

@ -1,54 +0,0 @@
/*
* SDRC register values for the Qimonda HYB18M512160AF-6
*
* Copyright (C) 2008-2009 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Nokia Corporation
*
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
#include "sdrc.h"
/* Qimonda HYB18M512160AF-6 */
static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
[0] = {
.rate = 166000000,
.actim_ctrla = 0x629db4c6,
.actim_ctrlb = 0x00012214,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[1] = {
.rate = 165941176,
.actim_ctrla = 0x629db4c6,
.actim_ctrlb = 0x00012214,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
},
[2] = {
.rate = 83000000,
.actim_ctrla = 0x31512283,
.actim_ctrlb = 0x0001220a,
.rfr_ctrl = 0x00025501,
.mr = 0x00000022,
},
[3] = {
.rate = 82970588,
.actim_ctrla = 0x31512283,
.actim_ctrlb = 0x0001220a,
.rfr_ctrl = 0x00025501,
.mr = 0x00000022,
},
[4] = {
.rate = 0
},
};
#endif

332
arch/arm/mach-omap2/serial.c
View File

@ -1,332 +0,0 @@
/*
* arch/arm/mach-omap2/serial.c
*
* OMAP2 serial support.
*
* Copyright (C) 2005-2008 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
* Major rework for PM support by Kevin Hilman
*
* Based off of arch/arm/mach-omap/omap1/serial.c
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/console.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/serial-omap.h>
#include "common.h"
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
#include "soc.h"
#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
#include "mux.h"
#include "serial.h"
/*
* NOTE: By default the serial auto_suspend timeout is disabled as it causes
* lost characters over the serial ports. This means that the UART clocks will
* stay on until power/autosuspend_delay is set for the uart from sysfs.
* This also causes that any deeper omap sleep states are blocked.
*/
#define DEFAULT_AUTOSUSPEND_DELAY -1
#define MAX_UART_HWMOD_NAME_LEN 16
struct omap_uart_state {
int num;
struct list_head node;
struct omap_hwmod *oh;
struct omap_device_pad default_omap_uart_pads[2];
};
static LIST_HEAD(uart_list);
static u8 num_uarts;
static u8 console_uart_id = -1;
static u8 uart_debug;
#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
#define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */
#define DEFAULT_RXDMA_TIMEOUT (3 * HZ)/* RX DMA timeout (jiffies) */
static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
{
.dma_enabled = false,
.dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
.dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
.dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
.autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
},
};
#ifdef CONFIG_PM
static void omap_uart_enable_wakeup(struct device *dev, bool enable)
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_device *od = to_omap_device(pdev);
if (!od)
return;
if (enable)
omap_hwmod_enable_wakeup(od->hwmods[0]);
else
omap_hwmod_disable_wakeup(od->hwmods[0]);
}
#else
static void omap_uart_enable_wakeup(struct device *dev, bool enable)
{}
#endif /* CONFIG_PM */
#ifdef CONFIG_OMAP_MUX
#define OMAP_UART_DEFAULT_PAD_NAME_LEN 28
static char rx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN],
tx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN] __initdata;
static void __init
omap_serial_fill_uart_tx_rx_pads(struct omap_board_data *bdata,
struct omap_uart_state *uart)
{
uart->default_omap_uart_pads[0].name = rx_pad_name;
uart->default_omap_uart_pads[0].flags = OMAP_DEVICE_PAD_REMUX |
OMAP_DEVICE_PAD_WAKEUP;
uart->default_omap_uart_pads[0].enable = OMAP_PIN_INPUT |
OMAP_MUX_MODE0;
uart->default_omap_uart_pads[0].idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0;
uart->default_omap_uart_pads[1].name = tx_pad_name;
uart->default_omap_uart_pads[1].enable = OMAP_PIN_OUTPUT |
OMAP_MUX_MODE0;
bdata->pads = uart->default_omap_uart_pads;
bdata->pads_cnt = ARRAY_SIZE(uart->default_omap_uart_pads);
}
static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
struct omap_uart_state *uart)
{
struct omap_mux_partition *tx_partition = NULL, *rx_partition = NULL;
struct omap_mux *rx_mux = NULL, *tx_mux = NULL;
char *rx_fmt, *tx_fmt;
int uart_nr = bdata->id + 1;
if (bdata->id != 2) {
rx_fmt = "uart%d_rx.uart%d_rx";
tx_fmt = "uart%d_tx.uart%d_tx";
} else {
rx_fmt = "uart%d_rx_irrx.uart%d_rx_irrx";
tx_fmt = "uart%d_tx_irtx.uart%d_tx_irtx";
}
snprintf(rx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, rx_fmt,
uart_nr, uart_nr);
snprintf(tx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, tx_fmt,
uart_nr, uart_nr);
if (omap_mux_get_by_name(rx_pad_name, &rx_partition, &rx_mux) >= 0 &&
omap_mux_get_by_name
(tx_pad_name, &tx_partition, &tx_mux) >= 0) {
u16 tx_mode, rx_mode;
tx_mode = omap_mux_read(tx_partition, tx_mux->reg_offset);
rx_mode = omap_mux_read(rx_partition, rx_mux->reg_offset);
/*
* Check if uart is used in default tx/rx mode i.e. in mux mode0
* if yes then configure rx pin for wake up capability
*/
if (OMAP_MODE_UART(rx_mode) && OMAP_MODE_UART(tx_mode))
omap_serial_fill_uart_tx_rx_pads(bdata, uart);
}
}
#else
static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
struct omap_uart_state *uart)
{
}
#endif
static char *cmdline_find_option(char *str)
{
extern char *saved_command_line;
return strstr(saved_command_line, str);
}
static int __init omap_serial_early_init(void)
{
if (of_have_populated_dt())
return -ENODEV;
do {
char oh_name[MAX_UART_HWMOD_NAME_LEN];
struct omap_hwmod *oh;
struct omap_uart_state *uart;
char uart_name[MAX_UART_HWMOD_NAME_LEN];
snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
"uart%d", num_uarts + 1);
oh = omap_hwmod_lookup(oh_name);
if (!oh)
break;
uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
if (WARN_ON(!uart))
return -ENODEV;
uart->oh = oh;
uart->num = num_uarts++;
list_add_tail(&uart->node, &uart_list);
snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
"%s%d", OMAP_SERIAL_NAME, uart->num);
if (cmdline_find_option(uart_name)) {
console_uart_id = uart->num;
if (console_loglevel >= CONSOLE_LOGLEVEL_DEBUG) {
uart_debug = true;
pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
uart_name, uart->num);
}
}
} while (1);
return 0;
}
omap_postcore_initcall(omap_serial_early_init);
/**
* omap_serial_init_port() - initialize single serial port
* @bdata: port specific board data pointer
* @info: platform specific data pointer
*
* This function initialies serial driver for given port only.
* Platforms can call this function instead of omap_serial_init()
* if they don't plan to use all available UARTs as serial ports.
*
* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
* use only one of the two.
*/
void __init omap_serial_init_port(struct omap_board_data *bdata,
struct omap_uart_port_info *info)
{
struct omap_uart_state *uart;
struct omap_hwmod *oh;
struct platform_device *pdev;
void *pdata = NULL;
u32 pdata_size = 0;
char *name;
struct omap_uart_port_info omap_up;
if (WARN_ON(!bdata))
return;
if (WARN_ON(bdata->id < 0))
return;
if (WARN_ON(bdata->id >= num_uarts))
return;
list_for_each_entry(uart, &uart_list, node)
if (bdata->id == uart->num)
break;
if (!info)
info = omap_serial_default_info;
oh = uart->oh;
name = OMAP_SERIAL_DRIVER_NAME;
omap_up.dma_enabled = info->dma_enabled;
omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
omap_up.flags = UPF_BOOT_AUTOCONF;
omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
omap_up.enable_wakeup = omap_uart_enable_wakeup;
omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
omap_up.dma_rx_timeout = info->dma_rx_timeout;
omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
omap_up.autosuspend_timeout = info->autosuspend_timeout;
pdata = &omap_up;
pdata_size = sizeof(struct omap_uart_port_info);
if (WARN_ON(!oh))
return;
pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size);
if (IS_ERR(pdev)) {
WARN(1, "Could not build omap_device for %s: %s.\n", name,
oh->name);
return;
}
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
if (console_uart_id == bdata->id) {
omap_device_enable(pdev);
pm_runtime_set_active(&pdev->dev);
}
oh->dev_attr = uart;
if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
&& !uart_debug)
device_init_wakeup(&pdev->dev, true);
}
/**
* omap_serial_board_init() - initialize all supported serial ports
* @info: platform specific data pointer
*
* Initializes all available UARTs as serial ports. Platforms
* can call this function when they want to have default behaviour
* for serial ports (e.g initialize them all as serial ports).
*/
void __init omap_serial_board_init(struct omap_uart_port_info *info)
{
struct omap_uart_state *uart;
struct omap_board_data bdata;
list_for_each_entry(uart, &uart_list, node) {
bdata.id = uart->num;
bdata.flags = 0;
bdata.pads = NULL;
bdata.pads_cnt = 0;
omap_serial_check_wakeup(&bdata, uart);
if (!info)
omap_serial_init_port(&bdata, NULL);
else
omap_serial_init_port(&bdata, &info[uart->num]);
}
}
/**
* omap_serial_init() - initialize all supported serial ports
*
* Initializes all available UARTs.
* Platforms can call this function when they want to have default behaviour
* for serial ports (e.g initialize them all as serial ports).
*/
void __init omap_serial_init(void)
{
omap_serial_board_init(NULL);
}

564
arch/arm/mach-omap2/twl-common.c
View File

@ -1,564 +0,0 @@
/*
* twl-common.c
*
* Copyright (C) 2011 Texas Instruments, Inc..
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/i2c.h>
#include <linux/i2c/twl.h>
#include <linux/gpio.h>
#include <linux/string.h>
#include <linux/phy/phy.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include "soc.h"
#include "twl-common.h"
#include "pm.h"
#include "voltage.h"
#include "mux.h"
static struct i2c_board_info __initdata pmic_i2c_board_info = {
.addr = 0x48,
.flags = I2C_CLIENT_WAKE,
};
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static int twl_set_voltage(void *data, int target_uV)
{
struct voltagedomain *voltdm = (struct voltagedomain *)data;
return voltdm_scale(voltdm, target_uV);
}
static int twl_get_voltage(void *data)
{
struct voltagedomain *voltdm = (struct voltagedomain *)data;
return voltdm_get_voltage(voltdm);
}
#endif
void __init omap_pmic_init(int bus, u32 clkrate,
const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data)
{
omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
strlcpy(pmic_i2c_board_info.type, pmic_type,
sizeof(pmic_i2c_board_info.type));
pmic_i2c_board_info.irq = pmic_irq;
pmic_i2c_board_info.platform_data = pmic_data;
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
}
#ifdef CONFIG_ARCH_OMAP4
void __init omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data,
struct i2c_board_info *devices, int nr_devices)
{
/* PMIC part*/
unsigned int irq;
omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
/* Register additional devices on i2c1 bus if needed */
if (devices)
i2c_register_board_info(1, devices, nr_devices);
}
#endif
void __init omap_pmic_late_init(void)
{
/* Init the OMAP TWL parameters (if PMIC has been registerd) */
if (!pmic_i2c_board_info.irq)
return;
omap3_twl_init();
omap4_twl_init();
}
#if defined(CONFIG_ARCH_OMAP3)
static struct twl4030_usb_data omap3_usb_pdata = {
.usb_mode = T2_USB_MODE_ULPI,
};
static int omap3_batt_table[] = {
/* 0 C */
30800, 29500, 28300, 27100,
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
4040, 3910, 3790, 3670, 3550
};
static struct twl4030_bci_platform_data omap3_bci_pdata = {
.battery_tmp_tbl = omap3_batt_table,
.tblsize = ARRAY_SIZE(omap3_batt_table),
};
static struct twl4030_madc_platform_data omap3_madc_pdata = {
.irq_line = 1,
};
static struct twl4030_codec_data omap3_codec;
static struct twl4030_audio_data omap3_audio_pdata = {
.audio_mclk = 26000000,
.codec = &omap3_codec,
};
static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
};
static struct regulator_init_data omap3_vdac_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
.consumer_supplies = omap3_vdda_dac_supplies,
};
static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
};
static struct regulator_init_data omap3_vpll2_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
.consumer_supplies = omap3_vpll2_supplies,
};
static struct regulator_consumer_supply omap3_vdd1_supply[] = {
REGULATOR_SUPPLY("vcc", "cpu0"),
};
static struct regulator_consumer_supply omap3_vdd2_supply[] = {
REGULATOR_SUPPLY("vcc", "l3_main.0"),
};
static struct regulator_init_data omap3_vdd1 = {
.constraints = {
.name = "vdd_mpu_iva",
.min_uV = 600000,
.max_uV = 1450000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vdd1_supply),
.consumer_supplies = omap3_vdd1_supply,
};
static struct regulator_init_data omap3_vdd2 = {
.constraints = {
.name = "vdd_core",
.min_uV = 600000,
.max_uV = 1450000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_vdd2_supply),
.consumer_supplies = omap3_vdd2_supply,
};
static struct twl_regulator_driver_data omap3_vdd1_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags)
{
if (!pmic_data->vdd1) {
omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
pmic_data->vdd1 = &omap3_vdd1;
}
if (!pmic_data->vdd2) {
omap3_vdd2.driver_data = &omap3_vdd2_drvdata;
omap3_vdd2_drvdata.data = voltdm_lookup("core");
pmic_data->vdd2 = &omap3_vdd2;
}
/* Common platform data configurations */
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
pmic_data->usb = &omap3_usb_pdata;
if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
pmic_data->bci = &omap3_bci_pdata;
if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
pmic_data->madc = &omap3_madc_pdata;
if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
pmic_data->audio = &omap3_audio_pdata;
/* Common regulator configurations */
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
pmic_data->vdac = &omap3_vdac_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
pmic_data->vpll2 = &omap3_vpll2_idata;
}
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP4)
static struct twl4030_usb_data omap4_usb_pdata = {
};
static struct regulator_consumer_supply omap4_vdda_hdmi_dac_supplies[] = {
REGULATOR_SUPPLY("vdda_hdmi_dac", "omapdss_hdmi"),
};
static struct regulator_init_data omap4_vdac_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdda_hdmi_dac_supplies),
.consumer_supplies = omap4_vdda_hdmi_dac_supplies,
.supply_regulator = "V2V1",
};
static struct regulator_init_data omap4_vaux2_idata = {
.constraints = {
.min_uV = 1200000,
.max_uV = 2800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_vaux3_idata = {
.constraints = {
.min_uV = 1000000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_consumer_supply omap4_vmmc_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 card */
static struct regulator_init_data omap4_vmmc_idata = {
.constraints = {
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
.consumer_supplies = omap4_vmmc_supply,
};
static struct regulator_init_data omap4_vpp_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 2500000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_vana_idata = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_consumer_supply omap4_vcxio_supply[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.1"),
};
static struct regulator_init_data omap4_vcxio_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
.always_on = true,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vcxio_supply),
.consumer_supplies = omap4_vcxio_supply,
.supply_regulator = "V2V1",
};
static struct regulator_init_data omap4_vusb_idata = {
.constraints = {
.min_uV = 3300000,
.max_uV = 3300000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_clk32kg_idata = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_consumer_supply omap4_vdd1_supply[] = {
REGULATOR_SUPPLY("vcc", "cpu0"),
};
static struct regulator_consumer_supply omap4_vdd2_supply[] = {
REGULATOR_SUPPLY("vcc", "iva.0"),
};
static struct regulator_consumer_supply omap4_vdd3_supply[] = {
REGULATOR_SUPPLY("vcc", "l3_main.0"),
};
static struct regulator_init_data omap4_vdd1 = {
.constraints = {
.name = "vdd_mpu",
.min_uV = 500000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdd1_supply),
.consumer_supplies = omap4_vdd1_supply,
};
static struct regulator_init_data omap4_vdd2 = {
.constraints = {
.name = "vdd_iva",
.min_uV = 500000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdd2_supply),
.consumer_supplies = omap4_vdd2_supply,
};
static struct regulator_init_data omap4_vdd3 = {
.constraints = {
.name = "vdd_core",
.min_uV = 500000,
.max_uV = 1500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_vdd3_supply),
.consumer_supplies = omap4_vdd3_supply,
};
static struct twl_regulator_driver_data omap4_vdd1_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct twl_regulator_driver_data omap4_vdd2_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
.get_voltage = twl_get_voltage,
.set_voltage = twl_set_voltage,
};
static struct regulator_consumer_supply omap4_v1v8_supply[] = {
REGULATOR_SUPPLY("vio", "1-004b"),
};
static struct regulator_init_data omap4_v1v8_idata = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
.always_on = true,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_v1v8_supply),
.consumer_supplies = omap4_v1v8_supply,
};
static struct regulator_consumer_supply omap4_v2v1_supply[] = {
REGULATOR_SUPPLY("v2v1", "1-004b"),
};
static struct regulator_init_data omap4_v2v1_idata = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap4_v2v1_supply),
.consumer_supplies = omap4_v2v1_supply,
};
void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags)
{
if (!pmic_data->vdd1) {
omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
pmic_data->vdd1 = &omap4_vdd1;
}
if (!pmic_data->vdd2) {
omap4_vdd2.driver_data = &omap4_vdd2_drvdata;
omap4_vdd2_drvdata.data = voltdm_lookup("iva");
pmic_data->vdd2 = &omap4_vdd2;
}
if (!pmic_data->vdd3) {
omap4_vdd3.driver_data = &omap4_vdd3_drvdata;
omap4_vdd3_drvdata.data = voltdm_lookup("core");
pmic_data->vdd3 = &omap4_vdd3;
}
/* Common platform data configurations */
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
pmic_data->usb = &omap4_usb_pdata;
/* Common regulator configurations */
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
pmic_data->vdac = &omap4_vdac_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
pmic_data->vaux2 = &omap4_vaux2_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
pmic_data->vaux3 = &omap4_vaux3_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
pmic_data->vmmc = &omap4_vmmc_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
pmic_data->vpp = &omap4_vpp_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
pmic_data->vana = &omap4_vana_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
pmic_data->vcxio = &omap4_vcxio_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
pmic_data->vusb = &omap4_vusb_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
!pmic_data->clk32kg)
pmic_data->clk32kg = &omap4_clk32kg_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_V1V8 && !pmic_data->v1v8)
pmic_data->v1v8 = &omap4_v1v8_idata;
if (regulators_flags & TWL_COMMON_REGULATOR_V2V1 && !pmic_data->v2v1)
pmic_data->v2v1 = &omap4_v2v1_idata;
}
#endif /* CONFIG_ARCH_OMAP4 */
#if IS_ENABLED(CONFIG_SND_OMAP_SOC_OMAP_TWL4030)
#include <linux/platform_data/omap-twl4030.h>
/* Commonly used configuration */
static struct omap_tw4030_pdata omap_twl4030_audio_data;
static struct platform_device audio_device = {
.name = "omap-twl4030",
.id = -1,
};
void omap_twl4030_audio_init(char *card_name,
struct omap_tw4030_pdata *pdata)
{
if (!pdata)
pdata = &omap_twl4030_audio_data;
pdata->card_name = card_name;
audio_device.dev.platform_data = pdata;
platform_device_register(&audio_device);
}
#else /* SOC_OMAP_TWL4030 */
void omap_twl4030_audio_init(char *card_name,
struct omap_tw4030_pdata *pdata)
{
return;
}
#endif /* SOC_OMAP_TWL4030 */

66
arch/arm/mach-omap2/twl-common.h
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@ -1,66 +0,0 @@
#ifndef __OMAP_PMIC_COMMON__
#define __OMAP_PMIC_COMMON__
#include "common.h"
#define TWL_COMMON_PDATA_USB (1 << 0)
#define TWL_COMMON_PDATA_BCI (1 << 1)
#define TWL_COMMON_PDATA_MADC (1 << 2)
#define TWL_COMMON_PDATA_AUDIO (1 << 3)
/* Common LDO regulators for TWL4030/TWL6030 */
#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
/* TWL6030 LDO regulators */
#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
#define TWL_COMMON_REGULATOR_VPP (1 << 5)
#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
#define TWL_COMMON_REGULATOR_VANA (1 << 7)
#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
#define TWL_COMMON_REGULATOR_V1V8 (1 << 11)
#define TWL_COMMON_REGULATOR_V2V1 (1 << 12)
/* TWL4030 LDO regulators */
#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
struct twl4030_platform_data;
struct twl6040_platform_data;
struct omap_tw4030_pdata;
struct i2c_board_info;
void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data);
void omap_pmic_late_init(void);
static inline void omap2_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
}
static inline void omap3_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
}
void omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data,
struct i2c_board_info *devices, int nr_devices);
void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags);
void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags);
void omap_twl4030_audio_init(char *card_name, struct omap_tw4030_pdata *pdata);
#endif /* __OMAP_PMIC_COMMON__ */

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arch/arm/mach-omap2/usb-host.c
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@ -1,496 +0,0 @@
/*
* usb-host.c - OMAP USB Host
*
* This file will contain the board specific details for the
* Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
*
* Copyright (C) 2007-2011 Texas Instruments
* Author: Vikram Pandita <vikram.pandita@ti.com>
* Author: Keshava Munegowda <keshava_mgowda@ti.com>
*
* Generalization by:
* Felipe Balbi <balbi@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/string.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/usb/phy.h>
#include <linux/usb/usb_phy_generic.h>
#include "soc.h"
#include "omap_device.h"
#include "mux.h"
#include "usb.h"
#ifdef CONFIG_MFD_OMAP_USB_HOST
#define OMAP_USBHS_DEVICE "usbhs_omap"
#define OMAP_USBTLL_DEVICE "usbhs_tll"
#define USBHS_UHH_HWMODNAME "usb_host_hs"
#define USBHS_TLL_HWMODNAME "usb_tll_hs"
/* MUX settings for EHCI pins */
/*
* setup_ehci_io_mux - initialize IO pad mux for USBHOST
*/
static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
{
switch (port_mode[0]) {
case OMAP_EHCI_PORT_MODE_PHY:
omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("hsusb1_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb1_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[1]) {
case OMAP_EHCI_PORT_MODE_PHY:
omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("hsusb2_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb2_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[2]) {
case OMAP_EHCI_PORT_MODE_PHY:
printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
break;
case OMAP_EHCI_PORT_MODE_TLL:
omap_mux_init_signal("hsusb3_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb3_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
return;
}
static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
{
switch (port_mode[0]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("mm1_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm1_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("mm1_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("mm1_txse0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm1_txdat",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[1]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("mm2_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm2_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("mm2_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("mm2_txse0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm2_txdat",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
switch (port_mode[2]) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
omap_mux_init_signal("mm3_rxdp",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm3_rxdm",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
omap_mux_init_signal("mm3_rxrcv",
OMAP_PIN_INPUT_PULLDOWN);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
/* FALLTHROUGH */
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
omap_mux_init_signal("mm3_txse0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mm3_txdat",
OMAP_PIN_INPUT_PULLDOWN);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
/* FALLTHROUGH */
default:
break;
}
}
void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
{
struct omap_hwmod *uhh_hwm, *tll_hwm;
struct platform_device *pdev;
int bus_id = -1;
if (cpu_is_omap34xx()) {
setup_ehci_io_mux(pdata->port_mode);
setup_ohci_io_mux(pdata->port_mode);
if (omap_rev() <= OMAP3430_REV_ES2_1)
pdata->single_ulpi_bypass = true;
}
uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
if (!uhh_hwm) {
pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
return;
}
tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
if (!tll_hwm) {
pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
return;
}
pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
pdata, sizeof(*pdata));
if (IS_ERR(pdev)) {
pr_err("Could not build hwmod device %s\n",
USBHS_TLL_HWMODNAME);
return;
}
pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
pdata, sizeof(*pdata));
if (IS_ERR(pdev)) {
pr_err("Could not build hwmod devices %s\n",
USBHS_UHH_HWMODNAME);
return;
}
}
#else
void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
{
}
#endif
/* Template for PHY regulators */
static struct fixed_voltage_config hsusb_reg_config = {
/* .supply_name filled later */
.microvolts = 3300000,
.gpio = -1, /* updated later */
.startup_delay = 70000, /* 70msec */
.enable_high = 1, /* updated later */
.enabled_at_boot = 0, /* keep in RESET */
/* .init_data filled later */
};
static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */
static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
/**
* usbhs_add_regulator - Add a gpio based fixed voltage regulator device
* @name: name for the regulator
* @dev_id: device id of the device this regulator supplies power to
* @dev_supply: supply name that the device expects
* @gpio: GPIO number
* @polarity: 1 - Active high, 0 - Active low
*/
static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
int gpio, int polarity)
{
struct regulator_consumer_supply *supplies;
struct regulator_init_data *reg_data;
struct fixed_voltage_config *config;
struct platform_device *pdev;
struct platform_device_info pdevinfo;
int ret = -ENOMEM;
supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
if (!supplies)
return -ENOMEM;
supplies->supply = dev_supply;
supplies->dev_name = dev_id;
reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
if (!reg_data)
goto err_data;
reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
reg_data->consumer_supplies = supplies;
reg_data->num_consumer_supplies = 1;
config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
GFP_KERNEL);
if (!config)
goto err_config;
config->supply_name = kstrdup(name, GFP_KERNEL);
if (!config->supply_name)
goto err_supplyname;
config->gpio = gpio;
config->enable_high = polarity;
config->init_data = reg_data;
/* create a regulator device */
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.name = reg_name;
pdevinfo.id = PLATFORM_DEVID_AUTO;
pdevinfo.data = config;
pdevinfo.size_data = sizeof(*config);
pdev = platform_device_register_full(&pdevinfo);
if (IS_ERR(pdev)) {
ret = PTR_ERR(pdev);
pr_err("%s: Failed registering regulator %s for %s : %d\n",
__func__, name, dev_id, ret);
goto err_register;
}
return 0;
err_register:
kfree(config->supply_name);
err_supplyname:
kfree(config);
err_config:
kfree(reg_data);
err_data:
kfree(supplies);
return ret;
}
#define MAX_STR 20
int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
{
char rail_name[MAX_STR];
int i;
struct platform_device *pdev;
char *phy_id;
struct platform_device_info pdevinfo;
struct usb_phy_generic_platform_data nop_pdata;
for (i = 0; i < num_phys; i++) {
if (!phy->port) {
pr_err("%s: Invalid port 0. Must start from 1\n",
__func__);
continue;
}
/* do we need a NOP PHY device ? */
if (!gpio_is_valid(phy->reset_gpio) &&
!gpio_is_valid(phy->vcc_gpio))
continue;
phy_id = kmalloc(MAX_STR, GFP_KERNEL);
if (!phy_id) {
pr_err("%s: kmalloc() failed\n", __func__);
return -ENOMEM;
}
/* set platform data */
memset(&nop_pdata, 0, sizeof(nop_pdata));
if (gpio_is_valid(phy->vcc_gpio))
nop_pdata.needs_vcc = true;
nop_pdata.gpio_reset = phy->reset_gpio;
nop_pdata.type = USB_PHY_TYPE_USB2;
/* create a NOP PHY device */
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.name = nop_name;
pdevinfo.id = phy->port;
pdevinfo.data = &nop_pdata;
pdevinfo.size_data =
sizeof(struct usb_phy_generic_platform_data);
scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d",
phy->port);
pdev = platform_device_register_full(&pdevinfo);
if (IS_ERR(pdev)) {
pr_err("%s: Failed to register device %s : %ld\n",
__func__, phy_id, PTR_ERR(pdev));
kfree(phy_id);
continue;
}
usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
/* Do we need VCC regulator ? */
if (gpio_is_valid(phy->vcc_gpio)) {
scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
usbhs_add_regulator(rail_name, phy_id, "vcc",
phy->vcc_gpio, phy->vcc_polarity);
}
phy++;
}
return 0;
}

106
arch/arm/mach-omap2/usb-musb.c
View File

@ -1,106 +0,0 @@
/*
* linux/arch/arm/mach-omap2/usb-musb.c
*
* This file will contain the board specific details for the
* MENTOR USB OTG controller on OMAP3430
*
* Copyright (C) 2007-2008 Texas Instruments
* Copyright (C) 2008 Nokia Corporation
* Author: Vikram Pandita
*
* Generalization by:
* Felipe Balbi <felipe.balbi@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/usb/musb.h>
#include "omap_device.h"
#include "soc.h"
#include "mux.h"
#include "usb.h"
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12,
};
static struct musb_hdrc_platform_data musb_plat = {
.mode = MUSB_OTG,
/* .clock is set dynamically */
.config = &musb_config,
/* REVISIT charge pump on TWL4030 can supply up to
* 100 mA ... but this value is board-specific, like
* "mode", and should be passed to usb_musb_init().
*/
.power = 50, /* up to 100 mA */
};
static u64 musb_dmamask = DMA_BIT_MASK(32);
static struct omap_musb_board_data musb_default_board_data = {
.interface_type = MUSB_INTERFACE_ULPI,
.mode = MUSB_OTG,
.power = 100,
};
void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
struct device *dev;
int bus_id = -1;
const char *oh_name, *name;
struct omap_musb_board_data *board_data;
if (musb_board_data)
board_data = musb_board_data;
else
board_data = &musb_default_board_data;
/*
* REVISIT: This line can be removed once all the platforms using
* musb_core.c have been converted to use use clkdev.
*/
musb_plat.clock = "ick";
musb_plat.board_data = board_data;
musb_plat.power = board_data->power >> 1;
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
oh_name = "usb_otg_hs";
name = "musb-omap2430";
oh = omap_hwmod_lookup(oh_name);
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
__func__, oh_name))
return;
pdev = omap_device_build(name, bus_id, oh, &musb_plat,
sizeof(musb_plat));
if (IS_ERR(pdev)) {
pr_err("Could not build omap_device for %s %s\n",
name, oh_name);
return;
}
dev = &pdev->dev;
get_device(dev);
dev->dma_mask = &musb_dmamask;
dev->coherent_dma_mask = musb_dmamask;
put_device(dev);
}

21
arch/arm/mach-omap2/usb-tusb6010.c
View File

@ -22,8 +22,6 @@
#include "gpmc.h"
#include "mux.h"
static u8 async_cs, sync_cs;
static unsigned refclk_psec;
@ -226,25 +224,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
}
tusb_device.dev.platform_data = data;
/* REVISIT let the driver know what DMA channels work */
if (!dmachan)
tusb_device.dev.dma_mask = NULL;
else {
/* assume OMAP 2420 ES2.0 and later */
if (dmachan & (1 << 0))
omap_mux_init_signal("sys_ndmareq0", 0);
if (dmachan & (1 << 1))
omap_mux_init_signal("sys_ndmareq1", 0);
if (dmachan & (1 << 2))
omap_mux_init_signal("sys_ndmareq2", 0);
if (dmachan & (1 << 3))
omap_mux_init_signal("sys_ndmareq3", 0);
if (dmachan & (1 << 4))
omap_mux_init_signal("sys_ndmareq4", 0);
if (dmachan & (1 << 5))
omap_mux_init_signal("sys_ndmareq5", 0);
}
/* so far so good ... register the device */
status = platform_device_register(&tusb_device);
if (status < 0) {

7
arch/arm/mach-orion5x/Kconfig
View File

@ -84,13 +84,6 @@ config MACH_LINKSTATION_PRO
Buffalo Linkstation Pro/Live platform. Both v1 and
v2 devices are supported.
config MACH_LINKSTATION_LSCHL
bool "Buffalo Linkstation Live v3 (LS-CHL)"
select I2C_BOARDINFO if I2C
help
Say 'Y' here if you want your kernel to support the
Buffalo Linkstation Live v3 (LS-CHL) platform.
config MACH_LINKSTATION_MINI
bool "Buffalo Linkstation Mini (Flattened Device Tree)"
select ARCH_ORION5X_DT

1
arch/arm/mach-orion5x/Makefile
View File

@ -18,7 +18,6 @@ obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o
obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o
obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o
obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o
obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o
obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o
obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o

331
arch/arm/mach-orion5x/ls-chl-setup.c
View File

@ -1,331 +0,0 @@
/*
* arch/arm/mach-orion5x/ls-chl-setup.c
*
* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/leds.h>
#include <linux/gpio_keys.h>
#include <linux/gpio-fan.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/ata_platform.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
/*****************************************************************************
* Linkstation LS-CHL Info
****************************************************************************/
/*
* 256K NOR flash Device bus boot chip select
*/
#define LSCHL_NOR_BOOT_BASE 0xf4000000
#define LSCHL_NOR_BOOT_SIZE SZ_256K
/*****************************************************************************
* 256KB NOR Flash on BOOT Device
****************************************************************************/
static struct physmap_flash_data lschl_nor_flash_data = {
.width = 1,
};
static struct resource lschl_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = LSCHL_NOR_BOOT_BASE,
.end = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1,
};
static struct platform_device lschl_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &lschl_nor_flash_data,
},
.num_resources = 1,
.resource = &lschl_nor_flash_resource,
};
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data lschl_eth_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
/*****************************************************************************
* RTC 5C372a on I2C bus
****************************************************************************/
static struct i2c_board_info __initdata lschl_i2c_rtc = {
I2C_BOARD_INFO("rs5c372a", 0x32),
};
/*****************************************************************************
* LEDs attached to GPIO
****************************************************************************/
#define LSCHL_GPIO_LED_ALARM 2
#define LSCHL_GPIO_LED_INFO 3
#define LSCHL_GPIO_LED_FUNC 17
#define LSCHL_GPIO_LED_PWR 0
static struct gpio_led lschl_led_pins[] = {
{
.name = "alarm:red",
.gpio = LSCHL_GPIO_LED_ALARM,
.active_low = 1,
}, {
.name = "info:amber",
.gpio = LSCHL_GPIO_LED_INFO,
.active_low = 1,
}, {
.name = "func:blue:top",
.gpio = LSCHL_GPIO_LED_FUNC,
.active_low = 1,
}, {
.name = "power:blue:bottom",
.gpio = LSCHL_GPIO_LED_PWR,
},
};
static struct gpio_led_platform_data lschl_led_data = {
.leds = lschl_led_pins,
.num_leds = ARRAY_SIZE(lschl_led_pins),
};
static struct platform_device lschl_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &lschl_led_data,
},
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data lschl_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* LS-CHL specific power off method: reboot
****************************************************************************/
/*
* On the LS-CHL, the shutdown process is following:
* - Userland monitors key events until the power switch goes to off position
* - The board reboots
* - U-boot starts and goes into an idle mode waiting for the user
* to move the switch to ON position
*
*/
static void lschl_power_off(void)
{
orion5x_restart(REBOOT_HARD, NULL);
}
/*****************************************************************************
* General Setup
****************************************************************************/
#define LSCHL_GPIO_USB_POWER 9
#define LSCHL_GPIO_AUTO_POWER 17
#define LSCHL_GPIO_POWER 18
/****************************************************************************
* GPIO Attached Keys
****************************************************************************/
#define LSCHL_GPIO_KEY_FUNC 15
#define LSCHL_GPIO_KEY_POWER 8
#define LSCHL_GPIO_KEY_AUTOPOWER 10
#define LSCHL_SW_POWER 0x00
#define LSCHL_SW_AUTOPOWER 0x01
#define LSCHL_SW_FUNC 0x02
static struct gpio_keys_button lschl_buttons[] = {
{
.type = EV_SW,
.code = LSCHL_SW_POWER,
.gpio = LSCHL_GPIO_KEY_POWER,
.desc = "Power-on Switch",
.active_low = 1,
}, {
.type = EV_SW,
.code = LSCHL_SW_AUTOPOWER,
.gpio = LSCHL_GPIO_KEY_AUTOPOWER,
.desc = "Power-auto Switch",
.active_low = 1,
}, {
.type = EV_SW,
.code = LSCHL_SW_FUNC,
.gpio = LSCHL_GPIO_KEY_FUNC,
.desc = "Function Switch",
.active_low = 1,
},
};
static struct gpio_keys_platform_data lschl_button_data = {
.buttons = lschl_buttons,
.nbuttons = ARRAY_SIZE(lschl_buttons),
};
static struct platform_device lschl_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &lschl_button_data,
},
};
#define LSCHL_GPIO_HDD_POWER 1
/****************************************************************************
* GPIO Fan
****************************************************************************/
#define LSCHL_GPIO_FAN_LOW 16
#define LSCHL_GPIO_FAN_HIGH 14
#define LSCHL_GPIO_FAN_LOCK 6
static struct gpio_fan_alarm lschl_alarm = {
.gpio = LSCHL_GPIO_FAN_LOCK,
};
static struct gpio_fan_speed lschl_speeds[] = {
{
.rpm = 0,
.ctrl_val = 3,
}, {
.rpm = 1500,
.ctrl_val = 2,
}, {
.rpm = 3250,
.ctrl_val = 1,
}, {
.rpm = 5000,
.ctrl_val = 0,
},
};
static int lschl_gpio_list[] = {
LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW,
};
static struct gpio_fan_platform_data lschl_fan_data = {
.num_ctrl = ARRAY_SIZE(lschl_gpio_list),
.ctrl = lschl_gpio_list,
.alarm = &lschl_alarm,
.num_speed = ARRAY_SIZE(lschl_speeds),
.speed = lschl_speeds,
};
static struct platform_device lschl_fan_device = {
.name = "gpio-fan",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &lschl_fan_data,
},
};
/****************************************************************************
* GPIO Data
****************************************************************************/
static unsigned int lschl_mpp_modes[] __initdata = {
MPP0_GPIO, /* LED POWER */
MPP1_GPIO, /* HDD POWER */
MPP2_GPIO, /* LED ALARM */
MPP3_GPIO, /* LED INFO */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_GPIO, /* FAN LOCK */
MPP7_GPIO, /* SW INIT */
MPP8_GPIO, /* SW POWER */
MPP9_GPIO, /* USB POWER */
MPP10_GPIO, /* SW AUTO POWER */
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_GPIO, /* FAN HIGH */
MPP15_GPIO, /* SW FUNC */
MPP16_GPIO, /* FAN LOW */
MPP17_GPIO, /* LED FUNC */
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static void __init lschl_init(void)
{
/*
* Setup basic Orion functions. Needs to be called early.
*/
orion5x_init();
orion5x_mpp_conf(lschl_mpp_modes);
/*
* Configure peripherals.
*/
orion5x_ehci0_init();
orion5x_ehci1_init();
orion5x_eth_init(&lschl_eth_data);
orion5x_i2c_init();
orion5x_sata_init(&lschl_sata_data);
orion5x_uart0_init();
orion5x_xor_init();
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
LSCHL_NOR_BOOT_BASE,
LSCHL_NOR_BOOT_SIZE);
platform_device_register(&lschl_nor_flash);
platform_device_register(&lschl_leds);
platform_device_register(&lschl_button_device);
platform_device_register(&lschl_fan_device);
i2c_register_board_info(0, &lschl_i2c_rtc, 1);
/* usb power on */
gpio_set_value(LSCHL_GPIO_USB_POWER, 1);
/* register power-off method */
pm_power_off = lschl_power_off;
pr_info("%s: finished\n", __func__);
}
MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
/* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = lschl_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END

30
arch/arm/mach-oxnas/Kconfig
View File

@ -1,9 +1,16 @@
menuconfig ARCH_OXNAS
bool "Oxford Semiconductor OXNAS Family SoCs"
select ARCH_HAS_RESET_CONTROLLER
select COMMON_CLK_OXNAS
select GPIOLIB
select MFD_SYSCON
select OXNAS_RPS_TIMER
select PINCTRL_OXNAS
select RESET_CONTROLLER
select RESET_OXNAS
select VERSATILE_FPGA_IRQ
select PINCTRL
depends on ARCH_MULTI_V5
depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
help
Support for OxNas SoC family developed by Oxford Semiconductor.
@ -11,16 +18,21 @@ if ARCH_OXNAS
config MACH_OX810SE
bool "Support OX810SE Based Products"
select ARCH_HAS_RESET_CONTROLLER
select COMMON_CLK_OXNAS
depends on ARCH_MULTI_V5
select CPU_ARM926T
select MFD_SYSCON
select OXNAS_RPS_TIMER
select PINCTRL_OXNAS
select RESET_CONTROLLER
select RESET_OXNAS
select VERSATILE_FPGA_IRQ
help
Include Support for the Oxford Semiconductor OX810SE SoC Based Products.
config MACH_OX820
bool "Support OX820 Based Products"
depends on ARCH_MULTI_V6
select ARM_GIC
select DMA_CACHE_RWFO if SMP
select CPU_V6K
select HAVE_SMP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
help
Include Support for the Oxford Semiconductor OX820 SoC Based Products.
endif

2
arch/arm/mach-oxnas/Makefile 100644
View File

@ -0,0 +1,2 @@
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

26
arch/arm/mach-oxnas/headsmp.S 100644
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
* Copyright (c) 2003 ARM Limited
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
__INIT
/*
* OX820 specific entry point for secondary CPUs.
*/
ENTRY(ox820_secondary_startup)
mov r4, #0
/* invalidate both caches and branch target cache */
mcr p15, 0, r4, c7, c7, 0
/*
* we've been released from the holding pen: secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup

109
arch/arm/mach-oxnas/hotplug.c 100644
View File

@ -0,0 +1,109 @@
/*
* Copyright (C) 2002 ARM Ltd.
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
asm volatile(
" mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x20\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C)
: "cc");
}
static inline void cpu_leave_lowpower(void)
{
unsigned int v;
asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
" orr %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
" mrc p15, 0, %0, c1, c0, 1\n"
" orr %0, %0, #0x20\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (CR_C)
: "cc");
}
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
/*
* there is no power-control hardware on this platform, so all
* we can do is put the core into WFI; this is safe as the calling
* code will have already disabled interrupts
*/
for (;;) {
/*
* here's the WFI
*/
asm(".word 0xe320f003\n"
:
:
: "memory", "cc");
if (pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/
break;
}
/*
* Getting here, means that we have come out of WFI without
* having been woken up - this shouldn't happen
*
* Just note it happening - when we're woken, we can report
* its occurrence.
*/
(*spurious)++;
}
}
/*
* platform-specific code to shutdown a CPU
*
* Called with IRQs disabled
*/
void ox820_cpu_die(unsigned int cpu)
{
int spurious = 0;
/*
* we're ready for shutdown now, so do it
*/
cpu_enter_lowpower();
platform_do_lowpower(cpu, &spurious);
/*
* bring this CPU back into the world of cache
* coherency, and then restore interrupts
*/
cpu_leave_lowpower();
if (spurious)
pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
}

102
arch/arm/mach-oxnas/platsmp.c 100644
View File

@ -0,0 +1,102 @@
/*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
* Copyright (C) 2002 ARM Ltd.
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
extern void ox820_secondary_startup(void);
extern void ox820_cpu_die(unsigned int cpu);
static void __iomem *cpu_ctrl;
static void __iomem *gic_cpu_ctrl;
#define HOLDINGPEN_CPU_OFFSET 0xc8
#define HOLDINGPEN_LOCATION_OFFSET 0xc4
#define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100)
#define GIC_CPU_CTRL 0x00
#define GIC_CPU_CTRL_ENABLE 1
int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/*
* Write the address of secondary startup into the
* system-wide flags register. The BootMonitor waits
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
writel(virt_to_phys(ox820_secondary_startup),
cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
/*
* Enable GIC cpu interface in CPU Interface Control Register
*/
writel(GIC_CPU_CTRL_ENABLE,
gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
/*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}
static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
void __iomem *scu_base;
np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
scu_base = of_iomap(np, 0);
of_node_put(np);
if (!scu_base)
return;
/* Remap CPU Interrupt Interface Registers */
np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
gic_cpu_ctrl = of_iomap(np, 1);
of_node_put(np);
if (!gic_cpu_ctrl)
goto unmap_scu;
np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
cpu_ctrl = of_iomap(np, 0);
of_node_put(np);
if (!cpu_ctrl)
goto unmap_scu;
scu_enable(scu_base);
flush_cache_all();
unmap_scu:
iounmap(scu_base);
}
static const struct smp_operations ox820_smp_ops __initconst = {
.smp_prepare_cpus = ox820_smp_prepare_cpus,
.smp_boot_secondary = ox820_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = ox820_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);

1
arch/arm/mach-pxa/corgi.c
View File

@ -35,7 +35,6 @@
#include <linux/mtd/sharpsl.h>
#include <linux/input/matrix_keypad.h>
#include <linux/gpio_keys.h>
#include <linux/module.h>
#include <linux/memblock.h>
#include <video/w100fb.h>

99
arch/arm/mach-pxa/em-x270.c
View File

@ -23,6 +23,7 @@
#include <linux/gpio.h>
#include <linux/mfd/da903x.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/spi/spi.h>
#include <linux/spi/tdo24m.h>
#include <linux/spi/libertas_spi.h>
@ -34,8 +35,6 @@
#include <linux/i2c/pxa-i2c.h>
#include <linux/regulator/userspace-consumer.h>
#include <media/soc_camera.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -958,8 +957,6 @@ static inline void em_x270_init_gpio_keys(void) {}
/* Quick Capture Interface and sensor setup */
#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
static struct regulator *em_x270_camera_ldo;
static int em_x270_sensor_init(void)
{
int ret;
@ -969,81 +966,53 @@ static int em_x270_sensor_init(void)
return ret;
gpio_direction_output(cam_reset, 0);
em_x270_camera_ldo = regulator_get(NULL, "vcc cam");
if (em_x270_camera_ldo == NULL) {
gpio_free(cam_reset);
return -ENODEV;
}
ret = regulator_enable(em_x270_camera_ldo);
if (ret) {
regulator_put(em_x270_camera_ldo);
gpio_free(cam_reset);
return ret;
}
gpio_set_value(cam_reset, 1);
return 0;
}
static struct regulator_consumer_supply camera_dummy_supplies[] = {
REGULATOR_SUPPLY("vdd", "0-005d"),
};
static struct regulator_init_data camera_dummy_initdata = {
.consumer_supplies = camera_dummy_supplies,
.num_consumer_supplies = ARRAY_SIZE(camera_dummy_supplies),
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
};
static struct fixed_voltage_config camera_dummy_config = {
.supply_name = "camera_vdd",
.input_supply = "vcc cam",
.microvolts = 2800000,
.gpio = -1,
.enable_high = 0,
.init_data = &camera_dummy_initdata,
};
static struct platform_device camera_supply_dummy_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &camera_dummy_config,
},
};
struct pxacamera_platform_data em_x270_camera_platform_data = {
.flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
.mclk_10khz = 2600,
};
static int em_x270_sensor_power(struct device *dev, int on)
{
int ret;
int is_on = regulator_is_enabled(em_x270_camera_ldo);
if (on == is_on)
return 0;
gpio_set_value(cam_reset, !on);
if (on)
ret = regulator_enable(em_x270_camera_ldo);
else
ret = regulator_disable(em_x270_camera_ldo);
if (ret)
return ret;
gpio_set_value(cam_reset, on);
return 0;
}
static struct i2c_board_info em_x270_i2c_cam_info[] = {
{
I2C_BOARD_INFO("mt9m111", 0x48),
},
};
static struct soc_camera_link iclink = {
.bus_id = 0,
.power = em_x270_sensor_power,
.board_info = &em_x270_i2c_cam_info[0],
.i2c_adapter_id = 0,
};
static struct platform_device em_x270_camera = {
.name = "soc-camera-pdrv",
.id = -1,
.dev = {
.platform_data = &iclink,
},
.sensor_i2c_adapter_id = 0,
.sensor_i2c_address = 0x5d,
};
static void __init em_x270_init_camera(void)
{
if (em_x270_sensor_init() == 0) {
if (em_x270_sensor_init() == 0)
pxa_set_camera_info(&em_x270_camera_platform_data);
platform_device_register(&em_x270_camera);
}
platform_device_register(&camera_supply_dummy_device);
}
#else
static inline void em_x270_init_camera(void) {}

206
arch/arm/mach-pxa/ezx.c
View File

@ -17,14 +17,14 @@
#include <linux/delay.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/leds-lp3944.h>
#include <linux/i2c/pxa-i2c.h>
#include <media/soc_camera.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -723,43 +723,33 @@ static struct platform_device a780_gpio_keys = {
};
/* camera */
static int a780_camera_init(void)
{
int err;
static struct regulator_consumer_supply camera_dummy_supplies[] = {
REGULATOR_SUPPLY("vdd", "0-005d"),
};
/*
* GPIO50_nCAM_EN is active low
* GPIO19_GEN1_CAM_RST is active on rising edge
*/
err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN");
if (err) {
pr_err("%s: Failed to request nCAM_EN\n", __func__);
goto fail;
}
static struct regulator_init_data camera_dummy_initdata = {
.consumer_supplies = camera_dummy_supplies,
.num_consumer_supplies = ARRAY_SIZE(camera_dummy_supplies),
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
};
err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST");
if (err) {
pr_err("%s: Failed to request CAM_RST\n", __func__);
goto fail_gpio_cam_rst;
}
gpio_direction_output(GPIO50_nCAM_EN, 1);
gpio_direction_output(GPIO19_GEN1_CAM_RST, 0);
return 0;
fail_gpio_cam_rst:
gpio_free(GPIO50_nCAM_EN);
fail:
return err;
}
static int a780_camera_power(struct device *dev, int on)
{
gpio_set_value(GPIO50_nCAM_EN, !on);
return 0;
}
static struct fixed_voltage_config camera_dummy_config = {
.supply_name = "camera_vdd",
.microvolts = 2800000,
.gpio = GPIO50_nCAM_EN,
.enable_high = 0,
.init_data = &camera_dummy_initdata,
};
static struct platform_device camera_supply_dummy_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &camera_dummy_config,
},
};
static int a780_camera_reset(struct device *dev)
{
gpio_set_value(GPIO19_GEN1_CAM_RST, 0);
@ -769,35 +759,44 @@ static int a780_camera_reset(struct device *dev)
return 0;
}
static int a780_camera_init(void)
{
int err;
/*
* GPIO50_nCAM_EN is active low
* GPIO19_GEN1_CAM_RST is active on rising edge
*/
err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST");
if (err) {
pr_err("%s: Failed to request CAM_RST\n", __func__);
return err;
}
gpio_direction_output(GPIO19_GEN1_CAM_RST, 0);
a780_camera_reset(NULL);
return 0;
}
struct pxacamera_platform_data a780_pxacamera_platform_data = {
.flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN |
PXA_CAMERA_PCP,
.mclk_10khz = 5000,
.sensor_i2c_adapter_id = 0,
.sensor_i2c_address = 0x5d,
};
static struct i2c_board_info a780_camera_i2c_board_info = {
I2C_BOARD_INFO("mt9m111", 0x5d),
};
static struct soc_camera_link a780_iclink = {
.bus_id = 0,
.flags = SOCAM_SENSOR_INVERT_PCLK,
.i2c_adapter_id = 0,
.board_info = &a780_camera_i2c_board_info,
.power = a780_camera_power,
.reset = a780_camera_reset,
};
static struct platform_device a780_camera = {
.name = "soc-camera-pdrv",
.id = 0,
.dev = {
.platform_data = &a780_iclink,
static struct i2c_board_info a780_i2c_board_info[] = {
{
I2C_BOARD_INFO("mt9m111", 0x5d),
},
};
static struct platform_device *a780_devices[] __initdata = {
&a780_gpio_keys,
&camera_supply_dummy_device,
};
static void __init a780_init(void)
@ -811,19 +810,19 @@ static void __init a780_init(void)
pxa_set_stuart_info(NULL);
pxa_set_i2c_info(NULL);
i2c_register_board_info(0, ARRAY_AND_SIZE(a780_i2c_board_info));
pxa_set_fb_info(NULL, &ezx_fb_info_1);
pxa_set_keypad_info(&a780_keypad_platform_data);
if (a780_camera_init() == 0) {
if (a780_camera_init() == 0)
pxa_set_camera_info(&a780_pxacamera_platform_data);
platform_device_register(&a780_camera);
}
pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
platform_add_devices(ARRAY_AND_SIZE(a780_devices));
regulator_has_full_constraints();
}
MACHINE_START(EZX_A780, "Motorola EZX A780")
@ -1001,43 +1000,6 @@ static struct platform_device a910_gpio_keys = {
};
/* camera */
static int a910_camera_init(void)
{
int err;
/*
* GPIO50_nCAM_EN is active low
* GPIO28_GEN2_CAM_RST is active on rising edge
*/
err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN");
if (err) {
pr_err("%s: Failed to request nCAM_EN\n", __func__);
goto fail;
}
err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST");
if (err) {
pr_err("%s: Failed to request CAM_RST\n", __func__);
goto fail_gpio_cam_rst;
}
gpio_direction_output(GPIO50_nCAM_EN, 1);
gpio_direction_output(GPIO28_GEN2_CAM_RST, 0);
return 0;
fail_gpio_cam_rst:
gpio_free(GPIO50_nCAM_EN);
fail:
return err;
}
static int a910_camera_power(struct device *dev, int on)
{
gpio_set_value(GPIO50_nCAM_EN, !on);
return 0;
}
static int a910_camera_reset(struct device *dev)
{
gpio_set_value(GPIO28_GEN2_CAM_RST, 0);
@ -1047,30 +1009,33 @@ static int a910_camera_reset(struct device *dev)
return 0;
}
static int a910_camera_init(void)
{
int err;
/*
* GPIO50_nCAM_EN is active low
* GPIO28_GEN2_CAM_RST is active on rising edge
*/
err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST");
if (err) {
pr_err("%s: Failed to request CAM_RST\n", __func__);
return err;
}
gpio_direction_output(GPIO28_GEN2_CAM_RST, 0);
a910_camera_reset(NULL);
return 0;
}
struct pxacamera_platform_data a910_pxacamera_platform_data = {
.flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN |
PXA_CAMERA_PCP,
.mclk_10khz = 5000,
};
static struct i2c_board_info a910_camera_i2c_board_info = {
I2C_BOARD_INFO("mt9m111", 0x5d),
};
static struct soc_camera_link a910_iclink = {
.bus_id = 0,
.i2c_adapter_id = 0,
.board_info = &a910_camera_i2c_board_info,
.power = a910_camera_power,
.reset = a910_camera_reset,
};
static struct platform_device a910_camera = {
.name = "soc-camera-pdrv",
.id = 0,
.dev = {
.platform_data = &a910_iclink,
},
.sensor_i2c_adapter_id = 0,
.sensor_i2c_address = 0x5d,
};
/* leds-lp3944 */
@ -1122,10 +1087,14 @@ static struct i2c_board_info __initdata a910_i2c_board_info[] = {
I2C_BOARD_INFO("lp3944", 0x60),
.platform_data = &a910_lp3944_leds,
},
{
I2C_BOARD_INFO("mt9m111", 0x5d),
},
};
static struct platform_device *a910_devices[] __initdata = {
&a910_gpio_keys,
&camera_supply_dummy_device,
};
static void __init a910_init(void)
@ -1145,14 +1114,13 @@ static void __init a910_init(void)
pxa_set_keypad_info(&a910_keypad_platform_data);
if (a910_camera_init() == 0) {
if (a910_camera_init() == 0)
pxa_set_camera_info(&a910_pxacamera_platform_data);
platform_device_register(&a910_camera);
}
pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
platform_add_devices(ARRAY_AND_SIZE(a910_devices));
regulator_has_full_constraints();
}
MACHINE_START(EZX_A910, "Motorola EZX A910")

18
arch/arm/mach-pxa/generic.c
View File

@ -43,21 +43,6 @@ void clear_reset_status(unsigned int mask)
}
}
unsigned long get_clock_tick_rate(void)
{
unsigned long clock_tick_rate;
if (cpu_is_pxa25x())
clock_tick_rate = 3686400;
else if (machine_is_mainstone())
clock_tick_rate = 3249600;
else
clock_tick_rate = 3250000;
return clock_tick_rate;
}
EXPORT_SYMBOL(get_clock_tick_rate);
/*
* For non device-tree builds, keep legacy timer init
*/
@ -69,8 +54,7 @@ void __init pxa_timer_init(void)
pxa27x_clocks_init();
if (cpu_is_pxa3xx())
pxa3xx_clocks_init();
pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000),
get_clock_tick_rate());
pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));
}
/*

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