drm/i915: enable/disable hooks for shared dplls
Looks at first like a bit of overkill, but - Haswell actually wants different enable/disable functions for different plls. - And once we have full dpll hw state tracking we can move the full register setup into the ->enable hook. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -132,6 +132,8 @@ enum hpd_pin {
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list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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if ((intel_encoder)->base.crtc == (__crtc))
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struct drm_i915_private;
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enum intel_dpll_id {
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DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
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/* real shared dpll ids must be >= 0 */
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@ -147,6 +149,10 @@ struct intel_shared_dpll {
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const char *name;
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/* should match the index in the dev_priv->shared_dplls array */
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enum intel_dpll_id id;
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void (*enable)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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void (*disable)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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};
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/* Used by dp and fdi links */
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@ -202,7 +208,6 @@ struct opregion_header;
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struct opregion_acpi;
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struct opregion_swsci;
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struct opregion_asle;
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struct drm_i915_private;
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struct intel_opregion {
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struct opregion_header __iomem *header;
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@ -1419,8 +1419,6 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
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int reg;
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u32 val;
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/* PCH PLLs only available on ILK, SNB and IVB */
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BUG_ON(dev_priv->info->gen < 5);
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@ -1434,9 +1432,6 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
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pll->name, pll->active, pll->on,
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crtc->base.base.id);
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/* PCH refclock must be enabled first */
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assert_pch_refclk_enabled(dev_priv);
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if (pll->active++) {
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WARN_ON(!pll->on);
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assert_shared_dpll_enabled(dev_priv, pll, NULL);
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@ -1445,14 +1440,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
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WARN_ON(pll->on);
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DRM_DEBUG_KMS("enabling %s\n", pll->name);
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reg = PCH_DPLL(pll->id);
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val = I915_READ(reg);
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val |= DPLL_VCO_ENABLE;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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udelay(200);
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pll->enable(dev_priv, pll);
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pll->on = true;
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}
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@ -1460,8 +1448,6 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
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int reg;
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u32 val;
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/* PCH only available on ILK+ */
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BUG_ON(dev_priv->info->gen < 5);
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@ -1486,17 +1472,7 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
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return;
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DRM_DEBUG_KMS("disabling %s\n", pll->name);
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/* Make sure transcoder isn't still depending on us */
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assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
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reg = PCH_DPLL(pll->id);
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val = I915_READ(reg);
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val &= ~DPLL_VCO_ENABLE;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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udelay(200);
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pll->disable(dev_priv, pll);
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pll->on = false;
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}
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@ -8729,6 +8705,43 @@ static void intel_cpu_pll_init(struct drm_device *dev)
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intel_ddi_pll_init(dev);
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}
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static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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uint32_t reg, val;
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/* PCH refclock must be enabled first */
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assert_pch_refclk_enabled(dev_priv);
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reg = PCH_DPLL(pll->id);
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val = I915_READ(reg);
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val |= DPLL_VCO_ENABLE;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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udelay(200);
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}
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static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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struct drm_device *dev = dev_priv->dev;
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struct intel_crtc *crtc;
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uint32_t reg, val;
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/* Make sure no transcoder isn't still depending on us. */
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
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if (intel_crtc_to_shared_dpll(crtc) == pll)
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assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
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}
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reg = PCH_DPLL(pll->id);
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val = I915_READ(reg);
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val &= ~DPLL_VCO_ENABLE;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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udelay(200);
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}
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static char *ibx_pch_dpll_names[] = {
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"PCH DPLL A",
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"PCH DPLL B",
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@ -8736,7 +8749,7 @@ static char *ibx_pch_dpll_names[] = {
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static void ibx_pch_dpll_init(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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dev_priv->num_shared_dpll = 2;
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@ -8744,12 +8757,14 @@ static void ibx_pch_dpll_init(struct drm_device *dev)
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for (i = 0; i < dev_priv->num_shared_dpll; i++) {
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dev_priv->shared_dplls[i].id = i;
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dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
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dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
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dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
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}
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}
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static void intel_shared_dpll_init(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
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ibx_pch_dpll_init(dev);
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